CN107610040A - A kind of method, apparatus and system of the segmentation of super-pixel image - Google Patents
A kind of method, apparatus and system of the segmentation of super-pixel image Download PDFInfo
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- CN107610040A CN107610040A CN201710874129.9A CN201710874129A CN107610040A CN 107610040 A CN107610040 A CN 107610040A CN 201710874129 A CN201710874129 A CN 201710874129A CN 107610040 A CN107610040 A CN 107610040A
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Abstract
The invention discloses a kind of method of super-pixel segmentation, view data with segmentation can be transferred to FPGA ends by host side, and treating segmentation figure picture by FPGA development boards carries out dividing processing, after processing terminates, result is obtained by host side again, final segmentation result is obtained by host side.This programme can realize the isomery processing to super-pixel image segmentation algorithm using the combination of FPGA development boards and host side, while the processing speed of FPGA development boards is higher, is effectively improved the performance of super-pixel image segmentation.The embodiment of the present invention also provides a kind of device of super-pixel segmentation, a kind of system of super-pixel segmentation, can equally realize above-mentioned technique effect.
Description
Technical field
The present invention relates to image real time transfer field, method, dress more specifically to a kind of segmentation of super-pixel image
Put and system.
Background technology
Having for the adjacent pixel composition that super-pixel segmentation technology refers to have the features such as similar grain, color, brightness is certain
The irregular block of pixels of visual meaningaaa.It utilizes the similitude of feature between pixel by group pixels, with a small amount of super-pixel generation
Express picture feature for substantial amounts of pixel, largely reduce the complexity of post processing of image, thus usually as point
Cut the pre-treatment step of algorithm.The computers such as image segmentation, pose estimation, target following, target identification are widely used for regard
Feel application.
Due to exploding for information age data volume, when having had a strong impact on the response of user's request to the speed of data processing
Between.Especially for the application under cloud computing, the quick response of mass data processing needs to take a large amount of computing resources, has a strong impact on
The performance and power consumption of cloud computing data processing centre.At present, computer vision application is increasingly dependent on super-pixel processing, respectively
Kind superpixel segmentation method is also continued to bring out, and much research and technology are improved SLIC superpixel segmentation methods,
Further to improve performance.However, the improvement to the technology is carried out in CPU/GPU hardware environment, data can not be realized
Parallel processing, therefore performance boost space is limited.
Therefore, the performance of super-pixel image segmentation how is improved, is that those skilled in the art need to solve the problems, such as.
The content of the invention
It is an object of the invention to provide the method, apparatus and system of a kind of super-pixel image segmentation, to improve super-pixel
The performance of image segmentation.
To achieve the above object, the embodiments of the invention provide following technical scheme：
A kind of method of super-pixel image segmentation, including：
The caching deposited needed for image to be split is created in the DDR of FPGA development boards, and the image to be split is sent out
Deliver to the caching；So that the FPGA development boards handle the image to be split using super-pixel image segmentation algorithm；
Obtain the result in the FPGA development boards and obtain the super picture of image to be split using the result
Plain image segmentation result.
A kind of device of super-pixel segmentation, including：
Sending module, for creating the caching deposited needed for image to be split in the DDR of FPGA development boards, and by described in
Image to be split is sent to the caching；So that the FPGA development boards using super-pixel image segmentation algorithm handle described in treat point
Cut image；
Acquisition module, for obtaining the result in the FPGA development boards and obtaining treating point using the result
Cut the super-pixel image segmentation result of image；
A kind of device of super-pixel segmentation, including：
First memory, for storing computer program；
First processor, a kind of super-pixel point as claimed in claim 1 is realized during for performing the computer program
The step of method cut.
A kind of method of super-pixel image segmentation, including：
The image to be split sent by host side is deposited to the storage created by the host side the figure to be split into DDR
As required caching；
The image to be split, which is handled, using super-pixel image segmentation algorithm obtains result；So that the host side obtains
The result is taken to obtain the super-pixel image segmentation result of image to be split.
Wherein, it is described to obtain result using the super-pixel image segmentation algorithm processing image to be split, including：
The image to be split is read to caching on piece from the DDR；
Using the seed point of the described upper initial image to be split of caching, and it is described in the seed vertex neighborhood
Each pixel distribution class label of image to be split obtains result；
The result is sent to DDR.
Wherein, the seed point using the described upper initial image to be split of caching, and it is adjacent in the seed point
After each pixel distribution class label in domain for the image to be split obtains result, in addition to：
Distance metric, the result optimized are carried out to the data in the result.
A kind of device of super-pixel segmentation, including：
Preserving module, for the image to be split sent by host side to be deposited into being created by the host side into DDR
Storage image to be split needed for caching；
Processing module, result is obtained for handling the image to be split using super-pixel image segmentation algorithm；With
Toilet states host side and obtains the result to obtain the super-pixel image segmentation result of image to be split.
Wherein, the processing module, including：
Data-reading unit to be split, for the image to be split to be read to caching on piece from the DDR；
Processing unit, for the seed point using the described upper initial image to be split of caching, and in the seed
Each pixel in vertex neighborhood for the image to be split distributes class label and obtains result；
Transmitting element, for the result to be sent to DDR.
A kind of device of super-pixel segmentation, including：
Second memory, for storing computer program；
Second processor, realize as described in any one in claim 4 to 6 during for performing the computer program
The step of a kind of method of super-pixel segmentation.
A kind of system of super-pixel segmentation, including：
Host side, for creating the caching deposited needed for image to be split in the DDR of FPGA development boards, and treated described
Segmentation figure picture is sent the result to the caching, obtained in the FPGA development boards and treated using the result
The super-pixel image segmentation result of segmentation figure picture；
The FPGA development boards, after the view data to be split sent for receiving the host side, utilize super-pixel
The image segmentation algorithm processing image to be split obtains result.
By above scheme, a kind of method of super-pixel segmentation provided in an embodiment of the present invention, in FPGA development boards
DDR in create the caching deposited needed for image to be split, and the image to be split is sent to the caching；It is so that described
FPGA development boards handle the image to be split using super-pixel image segmentation algorithm；Obtain the processing in the FPGA development boards
As a result and using the result super-pixel image segmentation result of image to be split is obtained.
As can be seen here, the method for a kind of super-pixel segmentation provided in an embodiment of the present invention, host side can be by with segmentations
View data is transferred to FPGA ends, and treating segmentation figure picture by FPGA development boards carries out dividing processing, after processing terminates, then by main frame
End obtains result, and final segmentation result is obtained by host side.This programme utilizes the combination of FPGA development boards and host side
The isomery processing to super-pixel image segmentation algorithm can be realized, while the processing speed of FPGA development boards is higher, effectively carries
The high performance of super-pixel image segmentation.The embodiment of the present invention also provides a kind of device of super-pixel segmentation, a kind of super-pixel point
The system cut, it can equally realize above-mentioned technique effect.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
There is the required accompanying drawing used in technology description to be briefly described, it should be apparent that, drawings in the following description are only this
Some embodiments of invention, for those of ordinary skill in the art, on the premise of not paying creative work, can be with
Other accompanying drawings are obtained according to these accompanying drawings.
Fig. 1 is a kind of method flow diagram of super-pixel image segmentation disclosed in the embodiment of the present invention；
Fig. 2 is a kind of apparatus structure schematic diagram of super-pixel image segmentation disclosed in the embodiment of the present invention；
Fig. 3 is a kind of apparatus structure schematic diagram of super-pixel image segmentation disclosed in the embodiment of the present invention；
Fig. 4 is a kind of method flow diagram of super-pixel image segmentation disclosed in the embodiment of the present invention；
Fig. 5 is a kind of apparatus structure schematic diagram of super-pixel image segmentation disclosed in the embodiment of the present invention；
Fig. 6 is a kind of apparatus structure schematic diagram of super-pixel image segmentation disclosed in the embodiment of the present invention；
Fig. 7 is a kind of system structure diagram of super-pixel image segmentation disclosed in the embodiment of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation describes, it is clear that described embodiment is only part of the embodiment of the present invention, rather than whole embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art are obtained every other under the premise of creative work is not made
Embodiment, belong to the scope of protection of the invention.
The embodiment of the invention discloses the method, apparatus and system of a kind of super-pixel image segmentation, to improve super-pixel figure
As the performance of segmentation.
Referring to Fig. 1, a kind of method of super-pixel image segmentation provided in an embodiment of the present invention, specifically include：
S101, creates the caching deposited needed for image to be split in the DDR of FPGA development boards, and by the figure to be split
As sending to the caching；So that the FPGA development boards handle the image to be split using super-pixel image segmentation algorithm；
Specifically, size of the processor as host side according to image to be split, created in the DDR internal memories of FPGA development boards
One piece of caching is built, then sends view data to be split to caching, treating partition data by FPGA carries out super-pixel segmentation
Processing.
S102, obtain the result in the FPGA development boards and obtain image to be split using the result
Super-pixel image segmentation result.
Specifically, FPGA development boards treat segmentation image real time transfer terminate after, host side obtain FPGA development boards in
Result, so as to obtain final super-pixel segmentation result.
It should be noted that super-pixel segmentation algorithm, can be SLIC super-pixel segmentation algorithms.
By above scheme, a kind of method of super-pixel segmentation provided in an embodiment of the present invention, host side can incite somebody to action
View data with segmentation is transferred to FPGA ends, and treating segmentation figure picture by FPGA development boards carries out dividing processing, after processing terminates,
Result is obtained by host side again, final segmentation result is obtained by host side.This programme utilizes FPGA development boards and main frame
The combination at end can realize the isomery processing to super-pixel image segmentation algorithm, while the processing speed of FPGA development boards is higher,
It is effectively improved the performance of super-pixel image segmentation.The embodiment of the present invention also provides a kind of device of super-pixel segmentation and is
System, can equally realize above-mentioned technique effect.
Below to a kind of device of super-pixel segmentation provided in an embodiment of the present invention, a kind of super-pixel segmentation described below
Device can be with cross-referenced with a kind of above-described method of super-pixel segmentation.
A kind of reference picture 2, device of super-pixel segmentation provided in an embodiment of the present invention, is specifically included：
Sending module 201, for creating the caching deposited needed for image to be split in the DDR of FPGA development boards, and will
The image to be split is sent to the caching；So that the FPGA development boards are using described in the processing of super-pixel image segmentation algorithm
Image to be split；
Specifically, sending module 201 creates one according to the size of image to be split in the DDR internal memories of FPGA development boards
Block caches, and then sends view data to be split to caching, and treating partition data by FPGA carries out super-pixel segmentation processing.
Acquisition module 202, for obtaining the result in the FPGA development boards and being obtained using the result
The super-pixel image segmentation result of image to be split.
Specifically, FPGA development boards treat segmentation image real time transfer terminate after, acquisition module 202 obtain FPGA exploitation
Result in plate, so as to obtain final super-pixel segmentation result.
It should be noted that super-pixel segmentation algorithm, can be SLIC super-pixel segmentation algorithms.
By above scheme, a kind of method of super-pixel segmentation provided in an embodiment of the present invention, sending module 201 can
So that the view data with segmentation is transferred into FPGA ends, segmentation figure picture is treated by FPGA development boards and carries out dividing processing, processing knot
Shu Hou, then result is obtained by acquisition module 202, final segmentation result is obtained by host side.This programme is opened using FPGA
The combination of hair plate and host side can realize the isomery processing to super-pixel image segmentation algorithm, while the processing of FPGA development boards
Speed is higher, is effectively improved the performance of super-pixel image segmentation.The embodiment of the present invention also provides a kind of super-pixel segmentation
Apparatus and system, it can equally realize above-mentioned technique effect.
Below to a kind of device of super-pixel segmentation provided in an embodiment of the present invention, a kind of super-pixel segmentation described below
Device can be with cross-referenced with a kind of above-described method of super-pixel segmentation.
A kind of reference picture 3, device of super-pixel segmentation provided in an embodiment of the present invention, is specifically included：
First memory 301, for storing computer program；
First processor 302, one kind super picture as described in above-mentioned embodiment is realized during for performing the computer program
The step of method of element segmentation.
Referring to Fig. 4, a kind of method of super-pixel image segmentation provided in an embodiment of the present invention, specifically include：
S401, the image to be split sent by host side is deposited into the storage created by the host side into DDR and treated
Caching of the segmentation figure as needed for；
Specifically, the view data to be split that FPGA development boards Receiving Host end is sent is deposited into DDR, and host side can be
FPGA ends set the parameter information of image segmentation algorithm.
S402, handle the image to be split using super-pixel image segmentation algorithm and obtain result；So as to the master
Generator terminal obtains the result to obtain the super-pixel image segmentation result of image to be split.
Specifically, after host side controls and starts super-pixel segmentation algorithm, FPGA ends can treat segmentation view data and carry out
Processing, obtains result.If algorithm is SLIC super-pixel segmentation algorithms, FPGA ends first have to just after starting algorithm
Beginning seed point, that is, cluster centre, and be that each pixel distributes class label in data in seed neighborhood of a point.To be terrible
Distance metric can also be carried out again to more excellent result, then obtains result.Processing terminates aft engine end and obtained to FPGA ends
Result, so as to obtain the segmentation result of final data image to be split.
It should be noted that after processing terminates, the signal that processing is completed can be sent to host side so that host side and
When acquisition result.
The embodiment of the present invention provides a kind of method of specific super-pixel image segmentation, is different from above-described embodiment, this hair
Bright embodiment has done specifically defined and explanation, other step contents and above-described embodiment substantially phase to S402 in above-described embodiment
Together, above-described embodiment is specifically may be referred to, here is omitted.Specifically, S402 includes：
The image to be split is read to caching on piece from the DDR；
Using the seed point of the described upper initial image to be split of caching, and it is described in the seed vertex neighborhood
Each pixel distribution class label of image to be split obtains result；
The result is sent to DDR.
In particular it is required that when handling view data to be split, FPGA development boards first are by the image to be split in DDR internal memories
Read in being cached on the piece in FPGA, it is necessary to which explanation, the operation of reading can be that batch is carried out, i.e., by the pending number of target
According to being read in bulk in the DDR from FPGA development boards to caching on the piece of FPGA development boards.In being cached on piece, initialize first
Seed point, also with regard to cluster centre, and it is each pixel distribution class label in emphasis neighborhood, obtains result, will handle
As a result it is written back in FPGA DDR.
More excellent to make to handle result after image to be split in FPGA ends, the embodiment of the present invention provides a kind of specific super picture
The method of element segmentation, based on above-described embodiment, the embodiment of the present invention is described initial described to be split using caching on described
The seed point of image, and in the seed vertex neighborhood be the image to be split each pixel distribution class label at
After managing result, in addition to：
Distance metric, the result optimized are carried out to the data in the result.
Specifically, after class label is distributed, can also to result carry out distance metric, measurement include measurement color away from
From and space length, be iterated optimization, enhancing is connective.
A kind of device of super-pixel segmentation provided in an embodiment of the present invention is introduced below, it is described below a kind of super
The device of pixel segmentation and a kind of above-described method of super-pixel segmentation are cross-referenced.
With reference to figure 5, a kind of device of super-pixel segmentation provided in an embodiment of the present invention, specifically include：
Preserving module 501, for the image to be split sent by host side to be deposited into being created by the host side into DDR
The caching needed for storage image to be split built；
Specifically, the view data to be split that the Receiving Host end of preserving module 501 is sent is deposited into DDR, host side meeting
At FPGA ends, the parameter information of image segmentation algorithm is set.
Processing module 502, result is obtained for handling the image to be split using super-pixel image segmentation algorithm；
So that the host side obtains the result to obtain the super-pixel image segmentation result of image to be split.
Specifically, after host side controls and starts super-pixel segmentation algorithm, processing module 502 can treat segmentation view data
Handled, obtain result.If algorithm is SLIC super-pixel segmentation algorithms, FPGA ends are after starting algorithm, first
Initial seed point, that is, cluster centre are wanted, and is that each pixel distributes class label in data in seed neighborhood of a point.For
Distance metric can also be carried out again by obtaining more excellent result, then obtain result.Processing terminates aft engine end to FPGA ends
Result is obtained, so as to obtain the segmentation result of final data image to be split.
It should be noted that after processing terminates, the signal that processing is completed can be sent to host side so that host side and
When acquisition result.
The embodiment of the present invention provides a kind of device of specific super-pixel image segmentation and is introduced, and is different from above-mentioned implementation
Example, the embodiment of the present invention processing module in above-described embodiment 502 has been done it is specifically defined and explanation, other step contents with it is upper
It is roughly the same to state embodiment, specifically may be referred to above-described embodiment, here is omitted.Specifically, processing module 502 includes：
Data-reading unit to be split, for the image to be split to be read to caching on piece from the DDR；
Processing unit, for the seed point using the described upper initial image to be split of caching, and in the seed
Each pixel in vertex neighborhood for the image to be split distributes class label and obtains result；
Transmitting element, for the result to be sent to DDR.
In particular it is required that when handling view data to be split, data-reading unit to be split first will be treated in DDR internal memories
Segmentation figure as read cached on the piece in FPGA in, it is necessary to which explanation, the operation of reading can be carried out in batches, i.e., by target
Pending data is read to caching on the piece of FPGA development boards in bulk from the DDR of FPGA development boards.In being cached on piece, place
Unit initialization seed point first is managed, also with regard to cluster centre, and is each pixel distribution class label in emphasis neighborhood, obtains
Result is written back in FPGA DDR by result, transmitting element.
A kind of device of super-pixel segmentation provided in an embodiment of the present invention is introduced below, it is described below a kind of super
The device of pixel segmentation and a kind of above-described method of super-pixel segmentation are cross-referenced.
With reference to figure 6, a kind of device of super-pixel segmentation provided in an embodiment of the present invention, specifically include：
Second memory 601, for storing computer program；
Second processor 602, one kind super picture as described in above-mentioned embodiment is realized during for performing the computer program
The step of method of element segmentation.
A kind of system of super-pixel segmentation provided in an embodiment of the present invention is introduced below, it is described below a kind of super
The system and a kind of above-described method, apparatus of super-pixel segmentation of pixel segmentation are cross-referenced.
With reference to figure 7, a kind of system of super-pixel segmentation provided in an embodiment of the present invention, specifically include：
Host side 701, for creating the caching deposited needed for image to be split in the DDR of FPGA development boards, and by institute
Image to be split is stated to send the result to the caching, obtained in the FPGA development boards and obtain using the result
To the super-pixel image segmentation result of image to be split；
Specifically, host side creates caching according to the size of image to be split in the DDR of FPGA development boards, will be to be split
Image be sent to caching so that FPGA development boards are handled using super-pixel segmentation algorithm, after processing terminates, host side is again
Obtain result and obtain final super-pixel image segmentation result.
The FPGA development boards 702, after the view data to be split sent for receiving the host side, utilize super picture
Plain image segmentation algorithm handles the image to be split and obtains result.
Specifically, FPGA development boards are after the data to be split of host side transmission are received, using in FPGA development boards
The super-pixel image segmentation algorithm processing image to be split obtains result, can send signal notice main frame after treatment
End is so that host side timely processing result, obtains final super-pixel image segmentation result.
It should be noted that completing the description of SLIC super-pixel segmentation algorithms using OpenCL high-level languages, generate respectively
The host side program run on CPU, and the Kernel programs towards FPGA platform.Then, using GCC compilers to main frame
End program is compiled, and generates the executable program file that can be performed on general processor CPU；Using Altera SDK for
OpenCL (AOC) High Level Synthesis instruments are compiled synthesis to Kernel program files, what generation can be run on FPGA
AOCX files.Finally, host side program is run on general processor CPU, calls the SLIC super-pixel segmentation cores on FPGA
The progress of hardware algorithm circuit is hardware-accelerated, is connected between CPU and FPGA using PCI-E interface, enters row data communication, using FPGA
DDR3 internal memories on development board are as data buffer storage Buffer.
Being co-operated by CPU and FPGA can realize that the operation of super-pixel segmentation algorithm accelerates, meanwhile, using OpenCL languages
Speech, which completes arthmetic statement, can realize that FPGA hardware performs the automation mapping of bit stream faster.
Each embodiment is described by the way of progressive in this specification, what each embodiment stressed be and other
The difference of embodiment, between each embodiment identical similar portion mutually referring to.
The foregoing description of the disclosed embodiments, professional and technical personnel in the field are enable to realize or using the present invention.
A variety of modifications to these embodiments will be apparent for those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, it is of the invention
The embodiments shown herein is not intended to be limited to, and is to fit to and principles disclosed herein and features of novelty phase one
The most wide scope caused.
Claims (10)
- A kind of 1. method of super-pixel image segmentation, it is characterised in that including：Create the caching deposited needed for image to be split in the DDR of FPGA development boards, and by the image to be split send to The caching；So that the FPGA development boards handle the image to be split using super-pixel image segmentation algorithm；Obtain the result in the FPGA development boards and obtain the super-pixel figure of image to be split using the result As segmentation result.
- A kind of 2. device of super-pixel segmentation, it is characterised in that including：Sending module, treated point for creating the caching deposited needed for image to be split in the DDR of FPGA development boards, and by described Image is cut to send to the caching；So that the FPGA development boards handle the figure to be split using super-pixel image segmentation algorithm Picture；Acquisition module, for obtaining the result in the FPGA development boards and obtaining figure to be split using the result The super-pixel image segmentation result of picture.
- A kind of 3. device of super-pixel segmentation, it is characterised in that including：First memory, for storing computer program；First processor, a kind of super-pixel segmentation as claimed in claim 1 is realized during for performing the computer program The step of method.
- A kind of 4. method of super-pixel image segmentation, it is characterised in that including：The image to be split sent by host side is deposited to the storage created by the host side the image institute to be split into DDR The caching needed；The image to be split, which is handled, using super-pixel image segmentation algorithm obtains result；So that the host side obtains institute Result is stated to obtain the super-pixel image segmentation result of image to be split.
- 5. according to the method for claim 4, it is characterised in that described to be treated using described in the processing of super-pixel image segmentation algorithm Segmentation figure picture obtains result, including：The image to be split is read to caching on piece from the DDR；Using the seed point of the described upper initial image to be split of caching, and it is described treat point in the seed vertex neighborhood The each pixel distribution class label for cutting image obtains result；The result is sent to DDR.
- 6. according to the method for claim 5, it is characterised in that described to utilize the described upper initial figure to be split of caching The seed point of picture, and be that each pixel distribution class label of the image to be split is handled in the seed vertex neighborhood As a result after, in addition to：Distance metric, the result optimized are carried out to the data in the result.
- A kind of 7. device of super-pixel segmentation, it is characterised in that including：Preserving module, for the image to be split sent by host side to be deposited into being deposited by what the host side created into DDR Put the caching needed for image to be split；Processing module, result is obtained for handling the image to be split using super-pixel image segmentation algorithm；With toilet State host side and obtain the result to obtain the super-pixel image segmentation result of image to be split.
- 8. device according to claim 7, it is characterised in that the processing module, including：Data-reading unit to be split, for the image to be split to be read to caching on piece from the DDR；Processing unit, for the seed point using the described upper initial image to be split of caching, and in seed point neighbour Each pixel in domain for the image to be split distributes class label and obtains result；Transmitting element, for the result to be sent to DDR.
- A kind of 9. device of super-pixel segmentation, it is characterised in that including：Second memory, for storing computer program；Second processor, one kind as described in any one in claim 4 to 6 is realized during for performing the computer program The step of method of super-pixel segmentation.
- A kind of 10. system of super-pixel segmentation, it is characterised in that including：Host side, for creating the caching deposited needed for image to be split in the DDR of FPGA development boards, and will be described to be split Image is sent the result to the caching, obtained in the FPGA development boards and obtained using the result to be split The super-pixel image segmentation result of image；The FPGA development boards, after the view data to be split sent for receiving the host side, utilize super-pixel image The partitioning algorithm processing image to be split obtains result.
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Application publication date: 20180119 |