CN107608548A - A kind of semiconductor pressure sensor, display panel and display device - Google Patents
A kind of semiconductor pressure sensor, display panel and display device Download PDFInfo
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- CN107608548A CN107608548A CN201710770446.6A CN201710770446A CN107608548A CN 107608548 A CN107608548 A CN 107608548A CN 201710770446 A CN201710770446 A CN 201710770446A CN 107608548 A CN107608548 A CN 107608548A
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Abstract
The embodiment of the invention discloses semiconductor pressure sensor, display panel and display device, semiconductor pressure sensor includes pressure sensing cell, bias voltage applying circuit and voltage detecting circuit；The principal direction of stress of first semiconductor layer of pressure sensing cell and the principal direction of stress of the second semiconductor layer are vertical；First power supply signal input of the first semiconductor layer and the 4th power supply signal end of the second semiconductor layer are electrically connected by the first power signal line with bias voltage applying circuit, the second source signal input part of first semiconductor layer is electrically connected with the 3rd power supply signal input of the second semiconductor layer by second source signal wire with bias voltage applying circuit, and the first induced signal measurement end of the first semiconductor layer and the second induced signal measurement end of the second semiconductor layer electrically connect with voltage detecting circuit respectively.To sum up, the principal direction of stress of the first semiconductor layer of setting and the principal direction of stress of the second semiconductor layer are vertical, and semiconductor pressure sensor pressure detecting is sensitive.
Description
Technical Field
The embodiment of the invention relates to the technical field of semiconductors, in particular to a semiconductor pressure sensor, a display panel and a display device.
Background
At present, more and more electronic devices are equipped with touch display screens, such as information detection machines in a hall in a public place, computers, mobile phones, and the like used by users in daily life and work. Therefore, the user can operate the electronic equipment by touching the mark on the touch display screen with fingers, the keyboard and mouse operation is avoided, and the man-machine interaction is more straightforward. In order to better meet the user requirement, a pressure sensor for detecting the magnitude of the touch pressure of the user during the process of touching the touch display screen is generally arranged in the touch display screen.
The bridge type strain sensor is a pressure sensor capable of detecting the magnitude of touch pressure, and the bridge type strain sensor calculates the magnitude of touch pressure by detecting in-plane deformation caused by z-direction strain and measuring the resistance change of the sensor.
The semiconductor pressure sensor is one of bridge type strain sensors, and in the prior art, the semiconductor pressure sensor has different deformations along the x direction and the y direction caused by the same touch position, so that the sensitivity of the semiconductor pressure sensor is low.
Disclosure of Invention
In view of this, embodiments of the present invention provide a semiconductor pressure sensor, a display panel and a display device to solve the technical problem of low sensitivity of the semiconductor pressure sensor in the prior art.
In a first aspect, an embodiment of the present invention provides a semiconductor pressure sensor, including a pressure detection unit, a bias voltage application circuit, and a voltage detection circuit;
the pressure detection unit comprises a first semiconductor layer and a second semiconductor layer, and the main stress direction of the first semiconductor layer is vertical to the main stress direction of the second semiconductor layer; the first semiconductor layer comprises a first power signal input end, a second power signal input end and a first induction signal measuring end positioned between the first power signal input end and the second power signal input end, and the second semiconductor layer comprises a third power signal input end, a fourth power signal input end and a second induction signal measuring end positioned between the third power signal input end and the fourth power signal input end;
the first power supply signal input terminal and the fourth power supply signal input terminal are electrically connected to the bias voltage applying circuit through a first power supply signal line, and the second power supply signal input terminal and the third power supply signal input terminal are electrically connected to the bias voltage applying circuit through a second power supply signal line;
the first induction signal measuring end is electrically connected with the voltage detection circuit through a first induction measuring line, and the second induction signal measuring end is electrically connected with the voltage detection circuit through a second induction measuring line.
In a second aspect, an embodiment of the present invention further provides a display panel, including the semiconductor pressure sensor in the first aspect, further including a substrate, a thin film transistor located on one side of the substrate, where the thin film transistor includes an active layer;
when the first semiconductor layer and the second semiconductor layer are located on different film layers, the first semiconductor layer or the second semiconductor layer and the active layer are arranged on the same layer;
when the first semiconductor layer and the second semiconductor layer are located on the same film layer, the first semiconductor layer and the second semiconductor layer are arranged on the same layer as the active layer.
In a third aspect, an embodiment of the present invention further provides a display device, including the display panel according to the second aspect.
The semiconductor pressure sensor provided by the embodiment of the invention, the semiconductor pressure sensor comprises a first semiconductor layer and a second semiconductor layer, the main stress direction of the first semiconductor layer is perpendicular to the main stress direction of the second semiconductor layer, a first power supply signal input end of the first semiconductor layer and a fourth power supply signal end of the second semiconductor layer are electrically connected with a bias voltage applying circuit through a first power supply signal line, a second power supply signal input end of the first semiconductor layer and a third power supply signal input end of the second semiconductor layer are electrically connected with the bias voltage applying circuit through a second power supply signal line, a first induction signal measuring end of the first semiconductor layer is electrically connected with a voltage detecting circuit through a first induction measuring line, and a second induction signal measuring end of the second semiconductor layer is electrically connected with the voltage detecting circuit through a second induction measuring line. The first semiconductor layer and the second semiconductor layer are arranged to be respectively electrically connected with the bias voltage applying circuit and the voltage detection circuit, the main stress direction of the first semiconductor layer is perpendicular to the main stress direction of the second semiconductor layer, when the semiconductor pressure sensor is under the action of pressure, the pressure is determined by respectively detecting the main stress change sensed on the first semiconductor layer and the main stress change sensed on the second semiconductor layer, the stress change sensed on the first semiconductor layer is equivalent to the stress change sensed on the second semiconductor layer, and the pressure detection sensitivity of the semiconductor pressure sensor is ensured.
Drawings
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures. Throughout this specification, the same or similar reference numbers refer to the same or similar structures, elements, or processes. It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict.
FIG. 1 is a diagram illustrating an exemplary structure of a semiconductor pressure sensor in the prior art;
fig. 2 is an equivalent circuit diagram of the semiconductor pressure sensor shown in fig. 1;
fig. 3 is a schematic structural diagram of a semiconductor pressure sensor according to an embodiment of the present invention;
fig. 4 is an equivalent circuit diagram of the semiconductor pressure sensor shown in fig. 3;
3 FIG. 3 5 3 is 3 a 3 cross 3- 3 sectional 3 view 3 of 3 the 3 semiconductor 3 pressure 3 sensor 3 shown 3 in 3 FIG. 3 3 3 along 3 section 3 line 3 A 3- 3 A 3' 3; 3
FIG. 6 is a schematic structural diagram of another semiconductor pressure sensor provided in an embodiment of the present invention;
fig. 7 is an equivalent circuit diagram of the semiconductor pressure sensor shown in fig. 6;
FIG. 8 is a schematic structural diagram of another semiconductor pressure sensor provided in an embodiment of the present invention;
fig. 9 is an equivalent circuit diagram of the semiconductor pressure sensor shown in fig. 8;
fig. 10 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
FIG. 11 is a cross-sectional view of the display panel shown in FIG. 10 along the line B-B';
FIG. 12 is a cross-sectional view of the display panel shown in FIG. 10 along the line B-B';
fig. 13 is a schematic cross-sectional view illustrating a display panel according to an embodiment of the invention;
FIG. 14 is a graph illustrating a variation of a strain voltage of a semiconductor layer according to an angle between the semiconductor layer and a first edge of a display panel according to an embodiment of the present invention;
fig. 15 is a schematic structural diagram of a display device according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be fully described by the detailed description with reference to the accompanying drawings in the embodiments of the present invention. It is obvious that the described embodiments are a part of the embodiments of the present invention, not all embodiments, and all other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without inventive efforts fall within the scope of the present invention.
Fig. 1 is a schematic view showing a structure of a semiconductor pressure sensor in the prior art, fig. 2 is an equivalent circuit diagram of the semiconductor pressure sensor shown in fig. 1, as shown in fig. 1, the semiconductor pressure sensor in the prior art is generally quadrilateral, the first connection terminal 101, the second connection terminal 102, the third connection terminal 103 and the fourth connection terminal 104 are respectively located on the first side, the second side, the third side and the fourth side of the semiconductor pressure sensor, the first side and the second side of the semiconductor pressure sensor are oppositely arranged, the third side and the fourth side are oppositely arranged, the first connection terminal 101 is electrically connected to the first power input signal line Vcc1, the second connection terminal 102 is electrically connected to the second power input signal line Vcc2, the third connection terminal 103 is electrically connected to the first sensing signal measurement signal line V +, and the fourth connection terminal 104 is electrically connected to the second sensing signal measurement signal line V-. The first power input signal line Vcc1 and the second power input signal line Vcc2 are used for inputting power driving signals to the semiconductor pressure sensor; the first and second sensing signal measurement signal lines V + and V-are used to output a touch pressure detection signal from the semiconductor pressure sensor. Fig. 2 is an equivalent circuit diagram of the semiconductor pressure sensor shown in fig. 1, and as shown in fig. 2, the semiconductor pressure sensor may be equivalent to a wheatstone bridge structure, the first pressure-sensitive resistor R1, the second pressure-sensitive resistor R2, the third pressure-sensitive resistor R3 and the fourth pressure-sensitive resistor R4 are connected to form a quadrilateral ABCD, which is called four arms of a bridge, the first pressure-sensitive resistor R1 and the third pressure-sensitive resistor R3 are used for sensing a stress change in the first direction 100, and the second pressure-sensitive resistor R2 and the fourth pressure-sensitive resistor R4 are used for sensing a stress change in the second direction 200. A diagonal BD of the quadrilateral ABCD is connected with a galvanometer G, two poles of the galvanometer G are connected with a first induction signal measuring signal line V + and a second induction signal measuring signal line V-, and A, C on a diagonal AC of the quadrilateral ABCD is respectively connected with a first power supply input signal line Vcc1 and a second power supply input signal line Vcc 2. When the semiconductor pressure sensor is rectangular in shape, the deformations of the first pressure-sensitive resistor R1 and the third pressure-sensitive resistor R3 caused by the same point pressure are different from the deformations of the second pressure-sensitive resistor R2 and the fourth pressure-sensitive resistor R4, resulting in a low pressure detection sensitivity of the semiconductor pressure sensor.
Based on the above technical problem, an embodiment of the present invention provides a semiconductor pressure sensor, including a pressure detection unit, a bias voltage application circuit, and a voltage detection circuit;
the pressure detection unit comprises a first semiconductor layer and a second semiconductor layer, and the main stress direction of the first semiconductor layer is vertical to the main stress direction of the second semiconductor layer; the first semiconductor layer comprises a first power signal input end, a second power signal input end and a first induction signal measuring end positioned between the first power signal input end and the second power signal input end, and the second semiconductor layer comprises a third power signal input end, a fourth power signal input end and a second induction signal measuring end positioned between the third power signal input end and the fourth power signal input end; the first power supply signal input terminal and the fourth power supply signal input terminal are electrically connected to the bias voltage applying circuit through a first power supply signal line, and the second power supply signal input terminal and the third power supply signal input terminal are electrically connected to the bias voltage applying circuit through a second power supply signal line; the first induction signal measuring end is electrically connected with the voltage detection circuit through a first induction measuring line, and the second induction signal measuring end is electrically connected with the voltage detection circuit through a second induction measuring line. The first semiconductor layer and the second semiconductor layer are arranged to be respectively electrically connected with the bias voltage applying circuit and the voltage detection circuit, the main stress direction of the first semiconductor layer is perpendicular to the main stress direction of the second semiconductor layer, when the semiconductor pressure sensor is under the action of pressure, the pressure is determined by respectively detecting the main stress change sensed on the first semiconductor layer and the main stress change sensed on the second semiconductor layer, the stress change sensed on the first semiconductor layer is equivalent to the stress change sensed on the second semiconductor layer, and the pressure detection sensitivity of the semiconductor pressure sensor is ensured.
The above is the core idea of the present invention, and the technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the drawings in the embodiment of the present invention. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present invention without any creative work belong to the protection scope of the present invention.
Fig. 3 is a schematic structural diagram of a semiconductor pressure sensor according to an embodiment of the present invention, and as shown in fig. 3, the semiconductor pressure sensor according to an embodiment of the present invention may include a pressure detection unit 10, a bias voltage applying circuit 20, and a voltage detection circuit 30;
the pressure detection unit 10 may include a first semiconductor layer 11 and a second semiconductor layer 12, where a main stress direction of the first semiconductor layer 11 is a first main stress direction 300, a main stress direction of the second semiconductor layer 12 is a second main stress direction 400, and the first main stress direction 300 is perpendicular to the second main stress direction 400; the first semiconductor layer 11 may include a first power signal input terminal 111 and a second power signal input terminal 112 and a first induced signal measurement terminal 113 between the first power signal input terminal 111 and the second power signal input terminal 112, and the second semiconductor layer 12 may include a third power signal input terminal 121 and a fourth power signal input terminal 122 and a second induced signal measurement terminal 123 between the third power signal input terminal 121 and the fourth power signal input terminal 122;
the first power supply signal input terminal 111 and the fourth power supply signal input terminal 122 are electrically connected to the bias voltage applying circuit 20 via the first power supply signal line 13, and the second power supply signal input terminal 112 and the third power supply signal input terminal 121 are electrically connected to the bias voltage applying circuit 20 via the second power supply signal line 14;
the first sensing signal measuring terminal 113 is electrically connected to the voltage detecting circuit 30 through the first sensing measuring line 15, and the second sensing signal measuring terminal 123 is electrically connected to the voltage detecting circuit 30 through the second sensing measuring line 16.
It should be noted that the first semiconductor layer 11 and the second semiconductor layer 12 of the present application are respectively formed in a shape having a long axis and a short axis, wherein the long axis and the short axis of each semiconductor layer are perpendicular to each other in a plane in which the semiconductor layers are located, and a main stress direction of each semiconductor layer refers to an extending direction of the long axis of the semiconductor layer. It should be noted that the long axis of the semiconductor layer in the present application refers to the connection line between the two end points of the semiconductor layer which are farthest away in the plane in which the semiconductor layer is located. In the present application, the specific shape of the semiconductor layer is not limited, and the specific shape of each semiconductor layer may be a rectangle, an ellipse, a serpentine, a polygon, or the like.
Fig. 4 is an equivalent circuit diagram of the semiconductor pressure sensor shown in fig. 3, in which since the first power signal input terminal 111 and the second power signal input terminal 112 of the first semiconductor layer 11 are electrically connected to the bias voltage applying circuit 20 through the first power signal line 13 and the second power signal line 14, respectively, and the first sensing signal measuring terminal 113 between the first power signal input terminal 111 and the second power signal input terminal 112 is electrically connected to the voltage detecting circuit 30 through the first sensing measuring line 15, a first pressure sensing resistor R1 may be equivalent between the first power signal input terminal 111 and the first sensing signal measuring terminal 113, and a second pressure sensing resistor R2 may be equivalent between the second power signal input terminal 112 and the first sensing signal measuring terminal 113; similarly, the third pressure-sensitive resistor R3 may be equivalent between the third power signal input terminal 121 and the second sensing signal measuring terminal 123, and the fourth pressure-sensitive resistor R4 may be equivalent between the fourth power signal input terminal 122 and the second sensing signal measuring terminal 123, as shown in fig. 4, the semiconductor pressure sensor formed by the first semiconductor layer 11 and the second semiconductor layer 12 may be equivalent to a wheatstone bridge structure, the first pressure-sensitive resistor R1 and the second pressure-sensitive resistor R2 are configured to sense the stress variation in the first main stress direction 300, and the third pressure-sensitive resistor R3 and the fourth pressure-sensitive resistor R4 are configured to sense the stress variation in the second main stress direction 400. When the semiconductor pressure sensor is used for detecting pressure, the first semiconductor layer 11 is used for detecting stress change in a first main stress direction 300, the second semiconductor layer 12 is used for detecting stress change in a second main stress direction 400, the first semiconductor layer 11 and the second semiconductor layer 12 are not affected each other when detecting the stress change, the deformation amount of the first semiconductor layer 11 is equivalent to that of the second semiconductor layer 12, and pressure detection sensitivity of the semiconductor pressure sensor is guaranteed.
Alternatively, the shape of the first semiconductor layer 11 may be rectangular, and the shape of the second semiconductor layer 12 may be rectangular, as shown in fig. 3, the extending direction of the long side of the first semiconductor layer 11 is the main stress direction of the first semiconductor layer 11; since the direction in which the long sides of the second semiconductor layer 12 extend is the main stress direction of the second semiconductor layer 12 and the main stress direction of the first semiconductor layer 11 is perpendicular to the main stress direction of the second semiconductor layer 12, it can be seen from fig. 3 that the direction in which the long sides of the first semiconductor layer 11 extend is perpendicular to the direction in which the long sides of the second semiconductor layer 12 extend.
Alternatively, when the first semiconductor layer 11 and the second semiconductor layer 12 are rectangular in shape, the extension length of the long sides of the first semiconductor layer 11 and the second semiconductor layer 12 may be 100 μm to 150 μm.
3 alternatively 3, 3 fig. 3 5 3 is 3 a 3 schematic 3 cross 3- 3 sectional 3 structure 3 view 3 of 3 the 3 semiconductor 3 pressure 3 sensor 3 shown 3 in 3 fig. 3 3 3 along 3 a 3 sectional 3 line 3 a 3- 3 a 3' 3, 3 and 3 as 3 shown 3 in 3 fig. 3 5 3, 3 in 3 the 3 semiconductor 3 pressure 3 sensor 3 provided 3 in 3 the 3 embodiment 3 of 3 the 3 invention 3, 3 the 3 first 3 semiconductor 3 layer 3 11 3 and 3 the 3 second 3 semiconductor 3 layer 3 12 3 in 3 the 3 pressure 3 detection 3 unit 3 10 3 may 3 be 3 located 3 on 3 different 3 film 3 layers 3, 3 and 3 the 3 insulating 3 layer 3 17 3 is 3 disposed 3 between 3 the 3 first 3 semiconductor 3 layer 3 11 3 and 3 the 3 second 3 semiconductor 3 layer 3 12 3. 3 As shown in fig. 5, when the first semiconductor layer 11 and the second semiconductor layer 12 are located on different layers, a vertical projection of the first semiconductor layer 11 on a plane where the second semiconductor layer 12 is located may be perpendicular to and intersect with the second semiconductor layer 12, or a vertical projection of the first semiconductor layer 11 on a plane where the second semiconductor layer 12 is located may be perpendicular to and intersect with only the second semiconductor layer 12. When the vertical projection of the semiconductor layer 11 on the plane of the second semiconductor layer 12 is perpendicular to and intersects with the second semiconductor layer 12, the pressure detection unit is ensured to be compactly arranged, the occupied space of the pressure detection unit is reduced, and the space utilization rate of the whole semiconductor pressure sensor can be improved; when the vertical projection of the first semiconductor layer 11 on the plane where the second semiconductor layer 12 is located is only perpendicular to but not intersected with the second semiconductor layer 12, it is ensured that the wiring arrangement mode of the semiconductor pressure detection unit is simple, it is not necessary to punch holes in the overlapped area of the first semiconductor layer 11 and the second semiconductor layer 12 to lead out wirings, and it is ensured that the semiconductor pressure sensor is simple in preparation method and high in preparation efficiency. Alternatively, the material of the insulating layer 17 may be silicon dioxide or silicon nitride, which ensures that the first semiconductor layer 11 and the second semiconductor layer 12 are arranged in an insulating manner.
Optionally, fig. 6 is a schematic structural diagram of another semiconductor pressure sensor provided in an embodiment of the present invention, and fig. 7 is an equivalent circuit diagram of the semiconductor pressure sensor shown in fig. 6, as shown in fig. 6 and fig. 7, in the pressure detection unit 10, the first semiconductor layer 11 and the second semiconductor layer 12 may be located in the same film layer, and the first semiconductor layer 11 and the second semiconductor layer 12 are vertical and do not intersect. The first semiconductor layer 11 and the second semiconductor layer 12 are located on the same film layer and are not intersected vertically, so that the first semiconductor layer 11 and the second semiconductor layer 12 can be prepared simultaneously, and the preparation method of the first semiconductor layer 11 and the second semiconductor layer 12 is simple; and because there is not the overlap region in first semiconductor layer 11 and second semiconductor layer 12, the deformation that first semiconductor layer 11 takes place when receiving the stress and the deformation that second semiconductor layer 12 takes place when receiving the stress can not influence each other, guarantee that semiconductor pressure sensor pressure detection is sensitive. Meanwhile, the first semiconductor layer 11 and the second semiconductor layer 12 are located on the same film layer and are not intersected, and the first semiconductor layer 11 and the second semiconductor layer 12 are not required to be arranged in an insulating mode through an insulating layer, so that the film layer of the whole semiconductor pressure sensor is simple in arrangement relation, the semiconductor pressure sensor is arranged in a thin mode, and the occupied space of the semiconductor pressure sensor is saved.
Alternatively, fig. 8 is a schematic structural diagram of another semiconductor pressure sensor according to an embodiment of the present invention, fig. 9 is an equivalent circuit diagram of the semiconductor pressure sensor shown in fig. 8, as shown in fig. 8 and fig. 9, the first semiconductor layer 11 and the second semiconductor layer 12 in the pressure detection unit 10 may be located in the same film layer, the first semiconductor layer 11 and the second semiconductor layer 12 are perpendicular, and the first power signal input end 111 of the first semiconductor layer 11 and the fourth power signal end 122 of the second semiconductor layer 12 intersect, or the second power signal input end 112 of the first semiconductor layer 11 and the third power signal end 121 of the second semiconductor layer 12 intersect, and fig. 5 only illustrates that the first power signal input end 111 and the fourth power signal end 122 intersect. As shown in fig. 8 and 9, the first semiconductor layer 11 and the second semiconductor layer 12 are located on the same film layer and are vertically disposed, so that the first semiconductor layer 11 and the second semiconductor layer 12 can be simultaneously prepared, and the preparation method of the first semiconductor layer 11 and the second semiconductor layer 12 is simple; and since the first power supply signal input terminal 111 and the fourth power supply signal input terminal 122 are both electrically connected to the bias voltage applying circuit 20 via the first power supply signal line 13, and the second power supply signal input terminal 112 and the third power supply signal input terminal 121 are both electrically connected to the bias voltage applying circuit 20 via the second power supply signal line 14, the first power supply signal input terminal 111 and the fourth power supply signal terminal 122 are set to intersect, or the second power supply signal input terminal 112 and the third power supply signal terminal 121 intersect, it is only necessary to connect the bias voltage applying circuit 20 via the first power supply signal line 13 or the second power supply signal line 14 at the intersection, and it is ensured that the connection relationship between the first semiconductor layer 11 and the second semiconductor layer 12 and the bias voltage applying circuit 20 is simple. Meanwhile, the first semiconductor layer 11 and the second semiconductor layer 12 are located on the same film layer, insulation setting is not needed to be carried out between the first semiconductor layer 11 and the second semiconductor layer 12 through an insulating layer, the film layer setting relation of the whole semiconductor pressure sensor is simple, thinning setting of the semiconductor pressure sensor is achieved, and the occupied space of the semiconductor pressure sensor is saved.
Alternatively, the material of the first semiconductor layer 11 and the second semiconductor layer 12 may be the same, and may be, for example, a polysilicon film or an amorphous silicon film. Moreover, the ion doping types of the first semiconductor layer 11 and the second semiconductor layer 12 may be the same, for example, both are P-type doping or both are N-type doping, which ensures that the preparation methods of the first semiconductor layer 11 and the second semiconductor layer 12 are simple.
Optionally, the resistances of the first semiconductor layer 11 and the second semiconductor layer 12 may be the same, and the resistances of the first semiconductor layer 11 and the second semiconductor layer 12 may be the same by setting the sizes of the first semiconductor layer 11 and the second semiconductor layer 12 to be the same, and the first semiconductor layer 11 and the second semiconductor layer 12 are doped in the same type and have the same concentration of doped ions, which ensures that the resistances of the first semiconductor layer 11 and the second semiconductor layer 12 are the same.
Optionally, with continued reference to fig. 3 and 4, the first sensing signal measuring terminal 113 may be located at a middle position of the first semiconductor layer 11, so as to ensure that the first pressure-sensitive resistor R1 and the resistance value are the same as the resistance value of the second pressure-sensitive resistor R2; the second sensing signal measuring terminal 123 may be located at a middle position of the second semiconductor layer 12, so as to ensure that the third pressure sensitive resistor R3 has the same resistance as the fourth pressure sensitive resistor R4. When the resistances of the first semiconductor layer 11 and the second semiconductor layer 12 are the same, the first sensing signal measuring terminal 113 is located at the middle position of the first semiconductor layer 11, and the second sensing signal measuring terminal 123 is located at the middle position of the second semiconductor layer 12, the resistances of the first pressure-sensitive resistor R1, the second pressure-sensitive resistor R2, the third pressure-sensitive resistor R3 and the fourth pressure-sensitive resistor R4 are all equal, so that the wheatstone bridge structure formed by the first pressure-sensitive resistor R1, the second pressure-sensitive resistor R2, the third pressure-sensitive resistor R3 and the fourth pressure-sensitive resistor R4 is in a balanced state without stress, and can be balanced as soon as possible under stress. It should be noted that the first sensing signal measuring terminal 113 is located at the middle position of the first semiconductor layer 11, and the second sensing signal measuring terminal 123 is located at the middle position of the second semiconductor layer 12, where the middle position refers to a position where the resistances of the first semiconductor layer 11 and the second semiconductor layer 12 are equally divided, and when the first semiconductor layer 11 and the second semiconductor layer 12 are in a regular shape, the middle position corresponds to the geometric center position of the regular shape; when the first semiconductor layer 11 and the second semiconductor layer 12 are irregular shapes, the middle position may correspond to a non-geometric center position of the irregular shapes, and the detailed description is omitted here.
Fig. 10 is a schematic structural diagram of a display panel according to an embodiment of the present invention, fig. 11 is a schematic structural diagram of a cross-section of the display panel shown in fig. 10 along a section line B-B', and in combination with fig. 10 and fig. 11, the display panel according to an embodiment of the present invention may include the semiconductor pressure sensor 40 according to the embodiment, and further include a substrate 50, a thin film transistor 60 located on one side of the substrate 50, and the thin film transistor 60 may include an active layer 601;
when the first semiconductor layer 11 and the second semiconductor layer 12 are located on different film layers, the first semiconductor layer 11 or the second semiconductor layer 12 is disposed on the same layer as the active layer 601;
when the first semiconductor layer 11 and the second semiconductor layer 12 are located at the same film layer, the first semiconductor layer 11 and the second semiconductor layer 12 are disposed at the same layer as the active layer 601.
For example, the semiconductor pressure sensor 40 and the thin film transistor 60 may be located on the same side of the substrate 50, and since the material of the active layer 601 of the thin film transistor 60 may be the same as the material of the first semiconductor layer 11 and the second semiconductor layer 12, such as a polysilicon film or an amorphous silicon film, the active layer 601 of the thin film transistor 60 may be located on the same layer as the first semiconductor layer 11 and the second semiconductor layer 12. When the first semiconductor layer 11 and the second semiconductor layer 12 are located at different film layers, one of the first semiconductor layer 11 or the second semiconductor layer 12 may be disposed at the same layer as the active layer 601 in the thin film transistor 60; when the first semiconductor layer 11 and the second semiconductor layer 12 are located on the same film layer, the first semiconductor layer 11 and the second semiconductor layer 12 are both arranged on the same layer as the active layer, so that the film layer arrangement relationship of the whole display panel is simple, and the thin arrangement of the display panel is facilitated; meanwhile, the first semiconductor layer 11 and/or the second semiconductor layer 12 can be prepared simultaneously with the active layer 601, so that the whole display panel is simple in preparation method and high in preparation efficiency. Fig. 11 illustrates the first semiconductor layer 11 and the second semiconductor layer 12 in different film layers, and the first semiconductor layer 11 and the active layer 601 are disposed in the same layer.
Optionally, the display panel provided in the embodiment of the present invention may be a liquid crystal display panel, an organic light emitting diode display panel, or a touch display panel, and when the display panel is a touch display panel, the display panel may further include a touch routing layer; when the display panel is an organic light emitting diode display panel, the display panel may further include a reflective electrode layer; when the display panel is an organic light emitting diode display panel with a touch control function, the display panel can further comprise a touch control routing layer and a reflection electrode layer; therefore, the display panel provided by the embodiment of the invention can comprise one or more layers of the touch routing layer and the reflective electrode layer. Meanwhile, the thin film transistor 60 may further include a gate electrode layer 602 and a source/drain electrode layer 603 in addition to the active layer 601, and the thin film transistor 60 may be a thin film transistor with a top gate structure or a thin film transistor with a bottom gate structure, which will be described below with respect to different situations that may exist in the display panel.
With reference to fig. 11, in fig. 11, the thin film transistor 60 is taken as a thin film transistor with a top gate structure, and the first semiconductor layer 11 and the second semiconductor layer 12 are located on different layers, and the display panel includes a touch routing layer 71 as an example for description.
Specifically, the first semiconductor layer 11 and the second semiconductor layer 12 are located on different film layers, the first semiconductor layer 11 is located on one side of the second semiconductor layer 12 away from the substrate base plate 50, and the first semiconductor layer 11 and the active layer 601 of the thin film transistor 60 are arranged on the same layer. The thin film transistor 60 further includes a gate electrode layer 602 and a source drain electrode layer 603 on a side of the active layer 601 away from the substrate 50, in which case the thin film transistor 60 is a top gate thin film transistor. When the tft 60 is a tft with a top-gate structure, the display panel may further include a light-shielding layer 72 located between the substrate 50 and the active layer 601, and since the tft 60 is a photosensitive element, the light-shielding layer 72 may be used to shield external light from entering a channel region in the active layer 601, so as to prevent light leakage of the tft 60. When the first semiconductor layer 11 and the second semiconductor layer 12 are located on different film layers, because the first sensing measurement signal terminal 113 in the first semiconductor layer 11 needs to be electrically connected to the voltage detection circuit 30 through the first sensing measurement line 15, and the second sensing measurement signal terminal 123 in the second semiconductor layer 12 needs to be electrically connected to the voltage detection circuit 30 through the second sensing measurement line 16, in the actual display panel manufacturing process, a via hole needs to be designed in the film layer on the side of the first semiconductor layer 11 away from the substrate 50, and a via hole needs to be designed in the film layer on the side of the second semiconductor layer 12 close to the substrate 50, so that the design requirements of electrically connecting the first sensing measurement signal terminal 113 and the second sensing measurement signal terminal 123 to the voltage detection circuit are met. Based on the above design requirements, the first sensing measurement line 15 and any one of the gate electrode layer 602, the source/drain electrode layer 603, the touch routing layer 71 and the reflective electrode (not shown in the figure) may be disposed in the same layer, and the second sensing measurement line 16 and the light shielding layer 72 may be disposed in the same layer, so that the design requirements that the first sensing measurement signal terminal 113 and the second sensing measurement signal terminal 123 are electrically connected to the voltage detection circuit 30 can be met, and meanwhile, the first sensing measurement line 15 and the second sensing measurement line 16 are disposed in the same layer as the existing film layer in the display panel, so that the first sensing measurement line 15 and the second sensing measurement line 16 are simple in preparation method, the film layer of the entire display panel is simple in arrangement relationship, and the thin design requirements of the display panel are easily met.
Further, the first power supply signal input terminal 111 of the first semiconductor layer 11 and the fourth power supply input terminal 122 of the second semiconductor layer 12 are electrically connected to the bias voltage applying circuit 20 through the first power supply signal line 13, and the second power supply signal input terminal 112 of the first semiconductor layer 11 and the third power supply input terminal 121 of the second semiconductor layer 12 are electrically connected to the bias voltage applying circuit 20 through the second power supply signal line 14, and therefore, the first power supply signal line 13 and the second power supply signal line 14 can be provided in the same layer. Optionally, via hole design may be performed on a film layer on the side of the first semiconductor layer 11 away from the substrate 50, and it is designed that the first power signal line 13 and the second power signal line 14 are disposed in the same layer as any one of the gate electrode layer 602, the source drain electrode layer 603, the touch wiring layer 71 and the reflective electrode layer (not shown in the figure) on the side of the first semiconductor layer 11 away from the substrate 50; it is also possible to design the first power supply signal line 13 and the second power supply signal line 14 to be provided in the same layer as the light-shielding layer 72 on the side of the first semiconductor layer 11 closer to the base substrate 50. Alternatively, the first power signal line 13 and the second power signal line 14 may be disposed in the same layer as the first induction measurement line 15 or the second induction measurement line 16, or the first power signal line 13 and the second power signal line 14 may be disposed in a different layer from the first induction measurement line 15 and the second induction measurement line 16, and the embodiment of the present invention defines whether the first power signal line 13 and the second power signal line 14 are disposed in a different layer from the first induction measurement line 15 or the second induction measurement line 16. In summary, the first power signal line 13 and the second power signal line 14 are disposed in the same layer as any one of the gate electrode layer 602, the source-drain electrode layer 603, the touch routing layer 71, the reflective electrode layer (not shown in the figure) and the light shielding layer 72, and the first power signal line 13 and the second power signal line 14 are disposed in the same layer as the existing film layer in the display panel, so that the preparation method of the first power signal line 13 and the second power signal line 14 is simple, the film layer arrangement relationship of the entire display panel is simple, and the thin design requirement of the display panel is easy to achieve. Fig. 11 exemplifies only an example in which the first power supply signal line 13, the second power supply signal line 14, and the first induction measuring line 15 are provided in the same layer as the gate electrode layer 602.
Fig. 12 is another cross-sectional structure view of the display panel shown in fig. 10 along a sectional line B-B', where fig. 12 illustrates a thin film transistor with a bottom gate structure of the thin film transistor 60, and the first semiconductor layer 11 and the second semiconductor layer 12 are located on different layers, and the display panel includes a touch routing layer 71 as an example.
As shown in fig. 12, the first semiconductor layer 11 and the second semiconductor layer 12 are located at different layers, the first semiconductor layer 11 is located at a side of the second semiconductor layer 12 away from the substrate 50, and the first semiconductor layer 11 is disposed at the same layer as the active layer 601 of the thin film transistor 60. The thin film transistor 60 further includes a gate electrode layer 602 located on one side of the active layer 601 close to the substrate 50 and a source drain electrode layer 603 located on one side of the active layer 601 far from the substrate 50, at this time, the thin film transistor 60 is a thin film transistor with a bottom gate structure, and at this time, the gate electrode layer 602 may be reused as a light shielding layer for shielding external light from entering a channel region in the active layer 601, so as to avoid light leakage of the thin film transistor 60. When the first semiconductor layer 11 and the second semiconductor layer 12 are located on different film layers, because the first sensing measurement signal terminal 113 in the first semiconductor layer 11 needs to be electrically connected to the voltage detection circuit 30 through the first sensing measurement line 15, and the second sensing measurement signal terminal 123 in the second semiconductor layer 12 needs to be electrically connected to the voltage detection circuit 30 through the second sensing measurement line 16, in the actual display panel manufacturing process, a via hole needs to be designed in the film layer on the side of the first semiconductor layer 11 away from the substrate 50, and a via hole needs to be designed in the film layer on the side of the second semiconductor layer 12 close to the substrate 50, so that the design requirements of electrically connecting the first sensing measurement signal terminal 113 and the second sensing measurement signal terminal 123 to the voltage detection circuit are met. Based on the above design requirements, the first sensing measurement line 15 and any one of the source/drain electrode layer 603, the touch routing layer 71 and the reflective electrode (not shown in the figure) may be arranged in the same layer, and the second sensing measurement line 16 and the gate electrode layer 602 are arranged in the same layer, so that the design requirement that the first sensing measurement signal terminal 113 and the second sensing measurement signal terminal 123 are electrically connected to the voltage detection circuit 30 can be met, and meanwhile, the first sensing measurement line 15 and the second sensing measurement line 16 are arranged in the same layer as the existing film layer in the display panel, so that the preparation method of the first sensing measurement line 15 and the second sensing measurement line 16 is simple, the film layer arrangement relationship of the whole display panel is simple, and the thin design requirement of the display panel is easy to meet.
Meanwhile, the first power signal line 13 and the second power signal line 14 are arranged in the same layer as any one of the gate electrode layer 602, the source-drain electrode layer 603, the touch routing layer 71 and the reflective electrode layer (not shown in the figure), so that the first power signal line 13 and the second power signal line 14 are arranged in the same layer as the existing film layer in the display panel, the preparation method of the first power signal line 13 and the second power signal line 14 is simple, the film layer arrangement relation of the whole display panel is simple, and the thin design requirement of the display panel is easy to realize. Fig. 12 exemplifies only the case where the first induction measuring line 15 is provided in the same layer as the source-drain electrode layer 603, and the first power supply signal line 13 and the second power supply signal line 14 are provided in the same layer as the gate electrode layer 602.
Fig. 13 is a schematic cross-sectional structure diagram of a display panel according to an embodiment of the present invention, and fig. 13 illustrates a thin film transistor with a top gate structure, in which the thin film transistor 60 is a thin film transistor, the first semiconductor layer 11 and the second semiconductor layer 12 are located in the same layer, and the display panel includes a touch routing layer 71 as an example.
As shown in fig. 13, the first semiconductor layer 11 and the second semiconductor layer 12 are located on the same layer and are both disposed on the same layer as the active layer 601 of the thin film transistor 60. The thin film transistor 60 further includes a gate electrode layer 602 and a source drain electrode layer 603 located on a side of the active layer 601 away from the substrate 50, where the thin film transistor 60 is a top gate thin film transistor, and the display panel may further include a light shielding layer 72 located between the substrate 50 and the active layer 601, where the light shielding layer 72 is used for shielding external light from entering a channel region in the active layer 601, so as to avoid light leakage of the thin film transistor 60. When the first semiconductor layer 11 and the second semiconductor layer 12 are located on the same layer of the same film layer, a via hole needs to be designed in the film layer on the side of the first semiconductor layer 11 away from the substrate 50 or the film layer on the side of the first semiconductor layer 11 close to the substrate 50, so as to meet the design requirement that the first sensing measurement signal terminal 113 and the second sensing measurement signal terminal 123 are electrically connected to the voltage detection circuit 30. Based on the above design requirements, the first sensing measurement line 15 and the second sensing measurement line 16 may be disposed in the same layer and disposed in the same layer as any one of the gate electrode layer 602, the source/drain electrode layer 603, the touch routing layer 71, the reflective electrode (not shown in the figure) and the light shielding layer 72, so that the design requirements that the first sensing measurement signal terminal 113 and the second sensing measurement signal terminal 123 are electrically connected to the voltage detection circuit 30 can be met, and meanwhile, the first sensing measurement line 15 and the second sensing measurement line 16 are disposed in the same layer as the existing film layer in the display panel, so that the first sensing measurement line 15 and the second sensing measurement line 16 are simple in preparation method, the film layer arrangement relationship of the entire display panel is simple, and the thin design requirements of the display panel are easy to meet.
Meanwhile, the first power signal line 13 and the second power signal line 14 may be disposed in the same layer as any one of the gate electrode layer 602, the source-drain electrode layer 603, the touch routing layer 71, the reflective electrode layer (not shown in the figure) and the light shielding layer 72, so as to ensure that the first power signal line 13 and the second power signal line 14 are disposed in the same layer as the existing film layer in the display panel, the preparation methods of the first power signal line 13 and the second power signal line 14 are simple, the film layer arrangement relationship of the whole display panel is simple, and the thin design requirement of the display panel is easy to achieve. Fig. 13 exemplifies only an example in which the first power supply signal line 13, the second power supply signal line 14, the first induction measuring line 15, and the second induction measuring line 16 are all provided in the same layer as the gate electrode layer 602.
Optionally, with reference to fig. 10, the display panel according to the embodiment of the present invention may be a rectangular display panel, where the rectangular display panel may include a first edge 51, an included angle between a first straight line 1 where the first power signal input end 111 and the second power signal input end 112 are located and the first edge 51 is 45 °, and an included angle between a second straight line 2 where the third power signal input end 121 and the fourth power signal input end 122 are located and the first edge 51 is 45 °.
the applicant has conducted extensive research and study to obtain a graph of a variation relationship between a strain Voltage value of a semiconductor layer and an Angle between the semiconductor layer and a first edge 51 of a display panel as shown in fig. 14, wherein an abscissa represents a size of an Angle α (Rotation Angle) between the first semiconductor layer 11 or the second semiconductor layer 12 and the first edge 51 of the display panel, and an ordinate represents a strain Voltage value (Output Voltage) Output by the first semiconductor layer 11 or the second semiconductor layer 12.
It should be noted that, in the embodiment of the present invention, the included angle between the first semiconductor layer 11 and the first edge 51 may be determined by the included angle between the first straight line 1 where the first power signal input end 111 and the second power signal input end 112 are located and the first edge 51, and the included angle between the second semiconductor layer 12 and the first edge 51 may be determined by the included angle between the second straight line 2 where the third power signal input end 121 and the fourth power signal input end 122 are located and the first edge 51, so that the included angle between the first straight line 1 where the first power signal input end 111 and the second power signal input end 112 are located and the first edge 51 is set to be 45 °, the included angle between the second straight line 2 where the third power signal input end 121 and the fourth power signal input end 122 are located and the first edge 51 is set to be 45 °, it can be ensured that the strain voltage value is larger when the stress variation occurs on the first semiconductor layer 11 and the second semiconductor layer 12, the high pressure detection sensitivity of the semiconductor pressure sensor is ensured.
Alternatively, with continued reference to fig. 10, the display panel may include a display area 81 and a non-display area 82 surrounding the display area 81, and the semiconductor pressure sensor 40 may be disposed in the non-display area 82, so as to ensure that the display panel has a high display aperture ratio when displaying.
Optionally, with reference to fig. 10, the pressure detecting units 10 located in the non-display area 82 may be arranged in a column, and the pressure detecting units 10 may multiplex the first power signal line 13, the second power signal line 14, the first sensing measurement line 15, and the second sensing measurement line 16, so as to ensure that the wiring of the whole display panel is simple, save the non-display area 82 of the display panel, ensure that the display panel has a larger display area 81, and improve the aperture ratio of the display panel. It will be appreciated by those skilled in the art that other implementations are possible, such as each pressure sensing unit 10 having separate first power signal line 13, second power signal line 14, first inductive measurement line 15 and second inductive measurement line 16, without multiplexing of the signal lines. This is not a limitation of the present application, as the case may be.
Fig. 15 is a schematic structural diagram of a display device according to an embodiment of the present invention, and referring to fig. 15, the display device 90 may include a display panel 901 according to any embodiment of the present invention. The display device 90 may be a mobile phone shown in fig. 15, or may be a computer, a television, an intelligent wearable display device, and the like, which is not particularly limited in this embodiment of the present invention.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious modifications, rearrangements, combinations and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (15)
1. A semiconductor pressure sensor is characterized by comprising a pressure detection unit, a bias voltage applying circuit and a voltage detection circuit;
the pressure detection unit comprises a first semiconductor layer and a second semiconductor layer, and the main stress direction of the first semiconductor layer is vertical to the main stress direction of the second semiconductor layer; the first semiconductor layer comprises a first power signal input end, a second power signal input end and a first induction signal measuring end positioned between the first power signal input end and the second power signal input end, and the second semiconductor layer comprises a third power signal input end, a fourth power signal input end and a second induction signal measuring end positioned between the third power signal input end and the fourth power signal input end;
the first power supply signal input terminal and the fourth power supply signal input terminal are electrically connected to the bias voltage applying circuit through a first power supply signal line, and the second power supply signal input terminal and the third power supply signal input terminal are electrically connected to the bias voltage applying circuit through a second power supply signal line;
the first induction signal measuring end is electrically connected with the voltage detection circuit through a first induction measuring line, and the second induction signal measuring end is electrically connected with the voltage detection circuit through a second induction measuring line.
2. The semiconductor pressure sensor according to claim 1, wherein the first semiconductor layer has a rectangular shape, the second semiconductor layer has a rectangular shape, and a direction in which the long side of the first semiconductor layer extends is perpendicular to a direction in which the long side of the second semiconductor layer extends.
3. The semiconductor pressure sensor according to claim 2, wherein the first semiconductor layer has an extension length of a long side of 100 μm to 150 μm, and the second semiconductor layer has an extension length of a long side of 100 μm to 150 μm.
4. The semiconductor pressure sensor of claim 1, wherein the first semiconductor layer and the second semiconductor layer are located on different film layers with an insulating layer disposed therebetween.
5. The semiconductor pressure sensor of claim 1, wherein the first semiconductor layer and the second semiconductor layer are located on a same membrane layer;
the first semiconductor layer and the second semiconductor layer are vertical and do not intersect; or,
the first semiconductor layer is perpendicular to the second semiconductor layer, and a first power signal input end of the first semiconductor layer intersects with a fourth power signal end of the second semiconductor layer, or a second power signal input end of the first semiconductor layer intersects with a third power signal end of the second semiconductor layer.
6. The semiconductor pressure sensor according to claim 1, wherein the resistance of the first semiconductor layer and the resistance of the second semiconductor are the same.
7. The semiconductor pressure sensor according to claim 6, wherein the first sensing signal measuring terminal is located at a middle position of the first semiconductor layer; the second sensing signal measuring end is located in the middle of the second semiconductor layer.
8. A display panel comprising the semiconductor pressure sensor according to any one of claims 1 to 7, further comprising a substrate base plate, a thin film transistor on one side of the substrate base plate, the thin film transistor including an active layer;
when the first semiconductor layer and the second semiconductor layer are located on different film layers, the first semiconductor layer or the second semiconductor layer and the active layer are arranged on the same layer;
when the first semiconductor layer and the second semiconductor layer are located on the same film layer, the first semiconductor layer and the second semiconductor layer are arranged on the same layer as the active layer.
9. The display panel according to claim 8, wherein the thin film transistor further comprises a gate electrode layer and a source drain electrode layer, and the display panel further comprises one or more layers of a touch routing layer and a reflective electrode layer located on a side of the thin film transistor away from the substrate.
10. The display panel according to claim 9, wherein the first semiconductor layer and the second semiconductor layer are located on different film layers, the first semiconductor layer is located on a side of the second semiconductor layer away from the substrate, and the first semiconductor layer and the active layer are disposed on the same layer;
the grid electrode is positioned on one side of the active layer far away from the substrate base plate, and the display panel further comprises a light shielding layer positioned between the substrate base plate and the active layer; the first induction measuring line and one of the grid electrode layer, the source drain electrode layer, the touch control wiring layer and the reflection electrode layer are arranged on the same layer, and the second induction measuring line and the shading layer are arranged on the same layer.
11. The display panel according to claim 10, wherein the first power supply signal line and the second power supply signal line are provided in the same layer;
the first power supply signal line and the second power supply signal line are arranged on the same layer as one layer of the grid electrode layer, the source drain electrode layer, the touch wiring layer, the reflecting electrode layer and the shading layer.
12. The display panel according to claim 9, wherein the first semiconductor layer and the second semiconductor layer are disposed on the same layer, and the first induction measuring line and the second induction measuring line are disposed on the same layer and are disposed on the same layer as one of the gate electrode layer, the source/drain electrode layer, the touch wiring layer, and the reflective electrode layer; the first power supply signal line and the second power supply signal line are arranged on the same layer, and are arranged on the same layer with one of the grid electrode layer, the source drain electrode layer, the touch wiring layer and the reflection electrode layer.
13. The display panel according to claim 8, wherein the display panel is a rectangular display panel, the rectangular display panel comprises a first edge, an included angle between a first straight line where the first power signal input terminal and the second power signal input terminal are located and the first edge is 45 °, and an included angle between a second straight line where the third power signal input terminal and the fourth power signal input terminal are located and the first edge is 45 °.
14. The display panel according to claim 8, wherein the display panel includes a display region and a non-display region surrounding the display region, and the semiconductor pressure sensor is provided in the non-display region.
15. A display device characterized by comprising the display panel according to any one of claims 8 to 14.
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| CN1293356A (en) * | 2000-11-01 | 2001-05-02 | 西安交通大学 | X-type silicon microstrain solid-state piezo-resistance sensor and its making technology |
| CN1696603A (en) * | 2005-06-10 | 2005-11-16 | 柳贵东 | Strain gage with controllable range mechanically and manufacturing method |
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