CN107592110A - Delay phase-locked loop clock line and semiconductor memory - Google Patents
Delay phase-locked loop clock line and semiconductor memory Download PDFInfo
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- CN107592110A CN107592110A CN201711027331.4A CN201711027331A CN107592110A CN 107592110 A CN107592110 A CN 107592110A CN 201711027331 A CN201711027331 A CN 201711027331A CN 107592110 A CN107592110 A CN 107592110A
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Abstract
The invention discloses delay phase-locked loop clock line, including：Delay phase-locked loop, it can correspond to external system and produce clock signal；Clock line control system, receive the clock signal from delay phase-locked loop transmission；High position data port section, the clock signal from clock line control system transmission is received, and for being exchanged with external system in high-order data bit width signal；And low data port section, receive the clock signal from clock line control system transmission, and for exchanging the data bit width signal in low level with external system, wherein, the longest path length from the delay phase-locked loop to the clock signal line of the high position data port section is different from the longest path length from the delay phase-locked loop to the clock signal line of the low data port section.The invention also discloses semiconductor memory.The present invention controls the flow direction of clock line so as to select optimal clock line by data bit width signal.
Description
Technical field
The present invention relates to semiconductor memory technologies field, more particularly to a kind of delay phase-locked loop clock line, further relates to wrap
The semiconductor memory of the clock line containing delay phase-locked loop.
Background technology
Delay phase-locked loop (Delay-Locked Loop, abbreviation DLL) technology is widely used in sequential field, delay
Phaselocked loop is used for the delay for automatically adjusting signal all the way, makes the phase of two paths of signals consistent (edge alignment).Specifically, needing
In the case that some data signals are synchronous with system clock, delay phase-locked loop aligns the edge of two-way clock, with what is be conditioned
Clock does control signal, it is possible to produce with the signal of system clock stringent synchronization, and this it is synchronous not with external condition such as temperature,
The change of voltage and change, therefore be widely used.
In the prior art, when being packaged according to the requirement of client, a chip needs the encapsulation with more than one
Mode, but in the case of different data bit width (configuration) X4/X8/X16 (DQ numbers), during delay phase-locked loop
The length of clock circuit is identical, therefore the power consumption of circuit is larger, so as to need that the delay phase-locked loop clock line is optimized.
Disclosed above- mentioned information is only used for strengthening the understanding of the background to the present invention in the introduction, therefore it may be wrapped
Containing the information for not being formed as the prior art that those of ordinary skill in the art are known.
The content of the invention
In view of this, the embodiment of the present invention aims to provide a kind of delay phase-locked loop clock line and semiconductor memory, with
At least solves technical problem present in prior art.
The technical scheme of the embodiment of the present invention is achieved in that according to one embodiment of present invention, there is provided Yi Zhongyan
Slow phase-locked loop clock circuit, the delay phase-locked loop clock line include：
Delay phase-locked loop, for producing clock signal；
Clock line control system, receive the clock signal from delay phase-locked loop transmission；
High position data port section, receive from the clock line control system transmission clock signal, and for
External system is exchanged in high-order data bit width signal；And
Low data port section, receive from the clock line control system transmission clock signal, and for
External system exchanges the data bit width signal in low level；
Wherein, from the delay phase-locked loop to the longest path path length of the clock signal line of the high position data port section
Degree is different from the longest path length from the delay phase-locked loop to the clock signal line of the low data port section.
According to an embodiment of the invention, due to from the delay phase-locked loop to the clock line of the high position data port section
The longest path length on road with from the delay phase-locked loop to the longest path of the clock line of the low data port section
Length is different, therefore, it is possible to by flexibly setting each FPDP part and the property of optimizing delay phase-locked loop clock circuit
Can and it design.
In a specific embodiment, from the delay phase-locked loop to the clock line of the low data port section
Longest path length is than the longest path length from the delay phase-locked loop to the clock line of the high position data port section
It is short.According to the present embodiment, the path length of the clock line by shortening low data port section, the work(of circuit can be reduced
Consume so as to improve the performance of delay phase-locked loop.
According to a specific embodiment, the clock line control system includes clock signal path selecting module, when outer
When portion's system needs to transmit high data bit width signal, the clock signal path selecting module is by clock signal transmission to the high position
FPDP part and the low data port section, when external system needs to transmit low bit bandwidth signals, the clock
Signal path selecting module is by clock signal transmission to the low data port section.The present embodiment is believed by being provided with clock
Number path selection module, the data bit width signal that transmits can be needed according to external system and select corresponding data terminal oral area
Point, therefore high data bit width signal and low bit bandwidth signals can be separately controlled, so as to easily and flexibly enter
Row control.
In a specific embodiment, the clock signal path selecting module includes first selector, works as external system
When needing to transmit high data bit width signal, the first selector is connected, therefore clock signal is transferred to the first selector.Root
According to the present embodiment, high data bit width signal is easily transmitted by setting first choice to realize.
According to a specific embodiment, the clock signal path selecting module also includes second selector and the 3rd selection
The signal input part of device, second selector and third selector connects the signal output part of first selector respectively, when described
When one selector is connected, the second selector and the third selector are also switched on, and are respectively used to clock signal
It is transferred to the high position data port section and the low data port section.By the present embodiment, a high position can will be in
It is transmitted respectively with the data bit width signal in low level, so as to be matched with external system.
Further, the clock line control system also includes high bit clock signal control unit, the high bit clock
The signal input part of signaling control unit connects the signal output part of the second selector, when the second selector is connected
When, the high bit clock signal control unit is used for clock signal transmission to the high position data port section.By this reality
Example is applied, the clock signal transmitted to high position data port section can further be controlled.
In another specific embodiment, the clock signal path selecting module also includes the 4th selector, when outside is
When system needs to transmit low bit bandwidth signals, the 4th selector is connected, therefore clock signal is transferred to the 4th selector.
According to the present embodiment, low bit bandwidth signals are easily transmitted by setting the 4th selector to realize.
The clock line control system also includes low level clock signal control unit, and the low level clock signal control is single
The signal input part of member connects the signal output part of the third selector and the 4th selector respectively, when the third selector
Or the 4th selector, when connecting, the low level clock signal control unit is used for clock signal transmission to the lower-order digit
According to port section.By the present embodiment, the clock signal transmitted to low data port section can further be controlled
System.
Another aspect of the present invention additionally provides a kind of semiconductor memory, including the above of the present invention and embodiment
Described in delay phase-locked loop clock line.
The embodiment of the present invention is due to using above technical scheme so that the clock line of low level bandwidth signals (X4/X8 signals)
Maximum length be almost the half of high-order bandwidth signals (such as X16 signals), so as to greatly reduce line during low level bandwidth signals
Road power consumption is while improve the performance (that is, short delay phase-locked loop feedback path) of delay phase-locked loop so that saves and excellent
The clock line under different pieces of information bit wide is changed, the flexible control for ensureing not having unnecessary circuit therefore can realize is to carry out
Selection.
Above-mentioned general introduction is merely to illustrate that the purpose of book, it is not intended to is limited in any way.Except foregoing description
Schematical aspect, outside embodiment and feature, it is further by reference to accompanying drawing and the following detailed description, the present invention
Aspect, embodiment and feature would is that what is be readily apparent that.
Brief description of the drawings
In the accompanying drawings, unless specified otherwise herein, otherwise represent same or analogous through multiple accompanying drawing identical references
Part or element.What these accompanying drawings were not necessarily to scale.It should be understood that these accompanying drawings depict only according to the present invention
Some disclosed embodiments, and should not serve to limit the scope of the present invention.
Fig. 1 is according to a kind of schematic diagram of delay phase-locked loop clock line.
Fig. 2 is the schematic diagram of the delay phase-locked loop clock line provided according to one embodiment of the invention.
Label declaration：
10 delay phase-locked loops；20 low data port sections；30 high position data port sections；
40th, 40 ' clock line control system；
41 clock signal path selecting modules；
411 first selectors；412 second selectors；413 third selectors；
42nd, 42 ' high bit clock signal control unit；
43rd, 43 ' low level clock signal control unit；
44th, 44 ' clock signal；
A, the longest path length of A ' low levels clock signal line；
B, the longest path length of the high-order clock signal lines of B '.
Embodiment
Hereinafter, some exemplary embodiments are simply just described.As one skilled in the art will recognize that
Like that, without departing from the spirit or scope of the present invention, described embodiment can be changed by various different modes.
Therefore, accompanying drawing and description are considered essentially illustrative rather than restrictive.
In the description of the invention, it is to be understood that term " " center ", " longitudinal direction ", " transverse direction ", " length ", " width ",
" thickness ", " on ", " under ", "front", "rear", "left", "right", " vertical ", " level ", " top ", " bottom ", " interior ", " outer ", " up time
The orientation or position relationship of the instruction such as pin ", " counterclockwise ", " axial direction ", " radial direction ", " circumference " be based on orientation shown in the drawings or
Position relationship, it is for only for ease of and describes the present invention and simplify description, rather than indicates or imply that signified device or element must
There must be specific orientation, with specific azimuth configuration and operation, therefore be not considered as limiting the invention.
In addition, term " first ", " second " are only used for describing purpose, and it is not intended that instruction or hint relative importance
Or the implicit quantity for indicating indicated technical characteristic.Thus, define " first ", the feature of " second " can be expressed or
Implicitly include one or more this feature.In the description of the invention, " multiple " are meant that two or more,
Unless otherwise specifically defined.
In the present invention, unless otherwise clearly defined and limited, term " installation ", " connected ", " connection ", " fixation " etc.
Term should be interpreted broadly, for example, it may be fixedly connected or be detachably connected, or integrally；Can be that machinery connects
Connect or electrically connect, can also be communication；Can be joined directly together, can also be indirectly connected by intermediary, can be with
It is connection or the interaction relationship of two elements of two element internals.For the ordinary skill in the art, may be used
To understand the concrete meaning of above-mentioned term in the present invention as the case may be.
In the present invention, unless otherwise clearly defined and limited, fisrt feature second feature it " on " or it " under "
Can directly it be contacted including the first and second features, it is not directly to contact but pass through it that can also include the first and second features
Between other characterisation contact.Moreover, fisrt feature second feature " on ", " side " and " above " include fisrt feature
Directly over second feature and oblique upper, or it is merely representative of fisrt feature level height and is higher than second feature.Fisrt feature is
Two features " under ", " lower section " and " following " fisrt feature that includes are directly over second feature and oblique upper, or be merely representative of the
One characteristic level is highly less than second feature.
Following disclosure provides many different embodiments or example is used for realizing the different structure of the present invention.In order to
Simplify disclosure of the invention, hereinafter the part and setting of specific examples are described.Certainly, they are only example, and
And purpose does not lie in the limitation present invention.In addition, the present invention can in different examples repeat reference numerals and/or reference letter,
This repetition is for purposes of simplicity and clarity, between itself not indicating discussed various embodiments and/or setting
Relation.In addition, the invention provides various specific techniques and material examples, but those of ordinary skill in the art can be with
Recognize the application of other techniques and/or the use of other materials.The specific reality according to the present invention is described now according to accompanying drawing
Apply example.
Describe in detail referring to the drawings according to an embodiment of the invention.
Fig. 1 shows a kind of delay phase-locked loop clock line that can apply to semiconductor memory.The delay phase-locked loop
Clock line adjusts the clock signal of chip according to the clock signal received from external system, so that the phase of chip
It is consistent with the phase of external system, and according to the data bit width signal of external system, select correspondingly to transmit clock signal
To corresponding high position data port section or low data port section, to exchange data with external system.
Data bit width signal refers to input and the signal of output data bit wide for representing chip, such as X4, X8 and X16.
In Fig. 1, the delay phase-locked loop clock line includes delay phase-locked loop 10 ', high position data port section 30 ' and low
Bit data end oral area point 20 ', wherein, the clock signal (CLK) that delay phase-locked loop 10 ' exports can be transferred to high position data end
Oral area point 30 ' and/or low data port section 20 '.
DQ serial numbers 8~15 included by high position data port section 30 ', for receiving in high-order data bit width letter
Number, DQ 8~15 data syn-chronization is discharged.DQ serial numbers 0~7 included by low data port section 20 ', use
In receiving the data bit width signal in low level, DQ 0~7 data syn-chronization is discharged.
The delay phase-locked loop clock line also includes clock line control system 40 ', for controlling from delay phase-locked loop 10 '
The transmission of the clock signal 44 ' of output.The clock line control system 40 ' includes high bit clock signal control unit 42 ' and low
Bit clock signal control unit 43 ', the two clock signal control units are used to control clock signal 44 ' to low data port
Part 20 ' and/or the transmission of high position data port section 30 '.
When external system needs the wide data-signal of transmitting high bit (such as X16), high bit clock signal control unit 42 ' and
Low level clock signal control unit 43 ' is turned on, and clock signal 44 ' is transferred to high position data port section 30 ' and lower-order digit
According to both port section 20 '.When external system needs to transmit low-bit width data-signal (such as X4/X8), low level clock letter
Number control unit 43 ' is connected, and clock signal 44 ' is transferred to low data port section 20 '；Also, high bit clock signal control
Unit 42 ' processed disconnects, and clock signal 44 ' is not transmitted to high position data port section 30 '.
Therefore, the clock signal 44 ' exported from delay phase-locked loop 10 ' is transferred to high order clock line road control unit 42 '
Or low level clock line control unit 43 '.Then, high position data end is respectively transmitted to by clock line control unit 42 ' or 43 '
Oral area point 30 ' or low data port section 20 '.
In Fig. 1, from delay phase-locked loop 10 ' to the longest path length of the clock line of high position data port section 30 '
For B ', the longest path length from delay phase-locked loop 10 ' to the clock line of low data port section 20 ' is A ', can by Fig. 1
With, it is evident that B ' and A ' the two path length it is identical or approximately the same.
Referring now to the delay phase-locked loop clock line shown in Fig. 2.
Delay phase-locked loop clock line shown in Fig. 2 includes delay phase-locked loop 10, low data port section 20, a high position
FPDP part 30 and clock line control system 40.Delay phase-locked loop 10 by clock line control system 40 respectively with
High position data port section 30 and low data port section 20 connect, and are used for high position data port section 30 and low level
Transmit clock signal 44 in FPDP part 20.
Delay phase-locked loop 10 can correspond to external system (not shown) and produce clock signal 44, and by the clock signal
44 are transferred to high position data port section 30 and/or low data port section 20 by clock line control system 40, with control
The delay of coremaking piece, so that chip is consistent with the phase of external system.
High position data port section 30 is used to receive the clock signal 44 come from the transmission of clock line control system 40, and
For exchanging the data bit width signal for being in high-order with external system.Data-signal in a high position is, for example, 8~DQ15 of DQ
Signal, wherein DQ represent the input/output port of chip.
Low data port section 20 is used to receive the clock signal 44 come from the transmission of clock line control system 40, and
The data bit width signal in low level is exchanged for external system.Data-signal in low level is, for example, 0~DQ7 of DQ letter
Number, wherein DQ represents the input/output port of chip.
Clock line control system 40 is used to control from the clock signal 44 that delay phase-locked loop 10 transmits out to high position data
The transmission of port section 30 and low data port section 20.
Clock line control system 40 include clock signal path selecting module 41, high order clock line road control unit 42 with
And low level clock line control unit 43, wherein, clock signal path selecting module 41 is used to receive to be passed from delay phase-locked loop 10
The clock signal 44 of output, and clock signal 44 is selectively transmitted to high order clock line road control unit 42 and low level
Clock line control unit 43, then by high order clock line road control unit 42 by clock signal transmission to high position data port part
Points 30, low level clock line control unit 43 is by clock signal transmission to low data port section 20.Specifically, when outside is
When system needs to transmit high data bit width signal, clock signal 44 is transmitted paramount bit data end by clock signal path selecting module 41
Oral area point 30 and low data port section 20；When external system needs to transmit low bit bandwidth signals, clock signal path
Clock signal 44 is transmitted to low data port section 20, clock signal 44 and is not transmitted to high position data port by selecting module 41
Part 30.
Clock signal path selecting module 41 include first selector 411, second selector 412, third selector 413 with
And the 4th selector 414.The signal input part of second selector 412 and third selector 413 connects first selector 411 respectively
Signal output part.
When external system needs to transmit high data bit width signal, first selector 411 is connected, and clock signal 44 is transmitted
Into the first selector 411.When first selector 411 is connected, second selector 412 and third selector 413 are also connect
It is logical, it is respectively used to clock signal 44 being transferred to the high position data port section 30 and the low data port section 20.
The signal output part of the signal input part connection second selector 412 of high bit clock signal control unit 42, when the
When two selectors 412 are connected, the high bit clock signal control unit 42 is used to clock signal 44 being transferred to high position data port
Part 30.
When external system needs to transmit low bit bandwidth signals, the 4th selector 414 is connected, and clock signal 44 is transmitted
Into the 4th selector 414.The signal input part of low level clock signal control unit 43 connects the He of third selector 413 respectively
The signal output part of 4th selector 414.When the selector 414 of third selector 413 or the 4th is connected, low level clock signal control
Unit 43 processed is used to clock signal 44 being transferred to low data port section 30.
In the embodiment of the present invention shown in fig. 2, first selector 411 includes logic NAND gate, second selector
412nd, the selector 414 of third selector 413 and the 4th includes logical AND gate.High bit clock signal control unit 42 and low level
Clock signal control unit 43 is logic NAND gate.Certainly, this Logic Circuit Design side is also not limited in practical application
Case, as long as can meet to control clock signal to high position data port section 30 and low data port part from first selector 411
Divide 20 transmission on request.
As shown in Figure 2, from delay phase-locked loop 10 to the longest path of the clock signal line of high position data port section 30
Electrical path length is B, and the longest path length from delay phase-locked loop 10 to the clock signal line of low data port section 20 is A,
As can be seen that A is different from B length, and A is almost B half.That is, in the present invention, X4/X8 clock letter
Number longest path length be almost X16 clock signal longest path length half, so as to greatly reduce X4/X8's
Circuit power consumption (reduces by 50%), and improves the performance of delay phase-locked loop.
The course of work of delay phase-locked loop clock line shown in accompanying drawing described in detail below.
First, delay phase-locked loop 10 receives the clock signal from external system, and to clock line control system 40
Export clock signal 44.
The clock signal path selecting module 41 of clock line control system 40 receives the clock signal 44.
When external system needs to transmit high data bit width signal, such as X16, the of clock signal path selecting module 41
One selector 411, second selector 412 and third selector 413 are turned on.By second selector 412 by clock signal
44 are transferred to high bit clock signal control unit 42, and are further transferred to seniority top digit by high bit clock signal control unit 42
According to port section 30, and DQ 8~15 data syn-chronization is discharged.Clock signal 44 is transmitted by third selector 413
Low data port is further transferred to low level clock signal control unit 43, and by low level clock signal control unit 43
Part 20, and DQDQ 0~7 data syn-chronization is discharged.In the process, the 4th selector 414 is closed.
When external system needs to transmit low bit bandwidth signals, for example, X4 or X8, clock signal path selecting module 41
The 4th selector 414 connect, and clock signal 44 is transferred to low level clock line control unit 43, and then during by the low level
Clock line control unit 43 is transferred to low data port section 20, and the data syn-chronization of DQ0~7 is discharged.Cross herein
Cheng Zhong, first selector 411, second selector 412 and third selector 413 are turned off.
According to an embodiment of the invention, the flow direction of clock line is controlled by data bit width signal, i.e. select optimal
Clock line, so as to remove unnecessary circuit, and cause X4/X8 that there is the path length of different clock lines from X16.
The foregoing is only a specific embodiment of the invention, but protection scope of the present invention is not limited thereto, any
Those familiar with the art the invention discloses technical scope in, its various change or replacement can be readily occurred in,
These should all be included within the scope of the present invention.Therefore, protection scope of the present invention should be with the guarantor of the claim
Shield scope is defined.
Claims (9)
1. a kind of delay phase-locked loop clock line, it is characterised in that the delay phase-locked loop clock line includes：
Delay phase-locked loop, for producing clock signal；
Clock line control system, receive the clock signal from delay phase-locked loop transmission；
High position data port section, the clock signal from clock line control system transmission is received, and be used for and outside
Systems exchange is in high-order data bit width signal；And
Low data port section, the clock signal from clock line control system transmission is received, and be used for and outside
Systems exchange is in the data bit width signal of low level；
Wherein, from the delay phase-locked loop to the clock signal line of the high position data port section longest path length with
Longest path length from the delay phase-locked loop to the clock signal line of the low data port section is different.
2. delay phase-locked loop clock line as claimed in claim 1, it is characterised in that from the delay phase-locked loop to described low
The longest path length ratio of the clock line of bit data end oral area point is from the delay phase-locked loop to the high position data port part
The longest path length of the clock line divided is short.
3. delay phase-locked loop clock line as claimed in claim 1, it is characterised in that the clock line control system includes
Clock signal path selecting module, when external system needs to transmit high data bit width signal, the clock signal path selection
Module is by clock signal transmission to the high position data port section and the low data port section, when external system needs
When transmitting low bit bandwidth signals, the clock signal path selecting module is by clock signal transmission to the low data port
Part.
4. delay phase-locked loop clock line as claimed in claim 3, it is characterised in that the clock signal path selecting module
Including first selector, when external system needs to transmit high data bit width signal, the first selector is connected, clock signal
It is transferred to the first selector.
5. delay phase-locked loop clock line as claimed in claim 4, it is characterised in that the clock signal path selecting module
Also include second selector and third selector, the signal input part of the second selector and third selector connects institute respectively
The signal output part of first selector is stated, when the first selector is connected, the second selector and the 3rd selection
Device is also switched on, and is respectively used to clock signal transmission to the high position data port section and the low data port
Part.
6. delay phase-locked loop clock line as claimed in claim 5, it is characterised in that the clock line control system is also wrapped
High bit clock signal control unit is included, the signal input part of the high bit clock signal control unit connects the second selector
Signal output part, when the second selector is connected, the high bit clock signal control unit be used for clock signal is passed
It is defeated to arrive the high position data port section.
7. delay phase-locked loop clock line as claimed in claim 5, it is characterised in that the clock signal path selecting module
Also include the 4th selector, when external system needs to transmit low bit bandwidth signals, the 4th selector is connected, clock letter
Number it is transferred to the 4th selector.
8. delay phase-locked loop clock line as claimed in claim 7, it is characterised in that the clock line control system is also wrapped
Low level clock signal control unit is included, the signal input part of the low level clock signal control unit connects the 3rd choosing respectively
The signal output part of device and the 4th selector is selected, when the third selector or the 4th selector connection, the low level
Clock signal control unit is used for clock signal transmission to the low data port section.
9. a kind of semiconductor memory, it is characterised in that including the delay phase-locked loop as any one of claim 1 to 8
Clock line.
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| CN201711027331.4A CN107592110B (en) | 2017-10-27 | 2017-10-27 | Delay phase-locked loop clock line and semiconductor memory |
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| CN201711027331.4A CN107592110B (en) | 2017-10-27 | 2017-10-27 | Delay phase-locked loop clock line and semiconductor memory |
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| CN107592110B CN107592110B (en) | 2023-10-20 |
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| Publication number | Publication date |
|---|---|
| CN107592110B (en) | 2023-10-20 |
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