CN107590100B - Inter-core data interaction method of multi-core processor - Google Patents
Inter-core data interaction method of multi-core processor Download PDFInfo
- Publication number
- CN107590100B CN107590100B CN201710793934.9A CN201710793934A CN107590100B CN 107590100 B CN107590100 B CN 107590100B CN 201710793934 A CN201710793934 A CN 201710793934A CN 107590100 B CN107590100 B CN 107590100B
- Authority
- CN
- China
- Prior art keywords
- core
- data
- class
- buffer
- inter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Multi Processors (AREA)
- Error Detection And Correction (AREA)
Abstract
The invention discloses an inter-core data interaction method of a multi-core processor, which comprises the following steps: the multiple cores are connected in sequence to form a ring communication structure, wherein each core is connected with the shared data area; one core starts inter-core communication interruption and sends the inter-core communication interruption to the next core, the next core responds to the inter-core communication interruption, reading and/or writing operation is carried out on the shared data area during the interruption response period, and the inter-core communication interruption is sent to the next core along the annular communication structure after the interruption response period is finished; the above processes are circularly carried out along the annular communication structure, and in the circulating process, the data interaction among the cores is completed through the shared data area. The invention provides an internuclear data interaction method with high-speed and high-reliability data transmission function, which can ensure that the read-write operation of a shared data area is only one core at any time, thereby effectively breaking through the bottleneck that the internuclear data is easy to transmit errors, and being applicable to both the presence and absence of an operating system.
Description
Technical Field
The invention relates to the technical field of multi-core processors, in particular to an inter-core data interaction method of a multi-core processor.
Background
At present, the use of multi-core processors is very common in various electrical appliances and various control systems. However, when the inter-core data interaction method is not appropriate, problems such as data transmission errors and a reduction in data processing speed may be caused. The existing solution is as follows: and developing mature operating systems such as Android, iOS, Windows phone and the like. However, the mature os occupies a large amount of system resources, and a high research and development cost is incurred in developing and optimizing the os.
Therefore, on the premise of not depending on a mature operating system, providing a method for data interaction between cores with high reliability and high transmission rate becomes an important point for technical problems to be solved and for research all the time by those skilled in the art.
Disclosure of Invention
In order to solve the problems that the internuclear data of the multi-core processor is easy to be transmitted wrongly, the data processing speed is low, and the operating system depending on maturity is restricted by system resources and cost, the invention innovatively provides an internuclear data interaction method with a high-speed and high-reliability data transmission function, so that the bottleneck that the internuclear data is easy to be transmitted wrongly is effectively broken through, and the method is applicable to both the presence and absence of the operating system and is easy to realize.
In order to achieve the technical purpose, the invention discloses an inter-core data interaction method of a multi-core processor, which comprises the following steps:
the annular communication structure is arranged: the multiple cores are connected in sequence, the tail core is connected with the head core to form a ring-shaped communication structure, and each core in the ring-shaped communication structure is connected with the shared data area respectively;
and (3) starting inter-core communication interruption: starting inter-core communication interruption by one core in the annular communication structure, and sending the inter-core communication interruption to the next core in the annular communication structure;
responding to inter-core communication interruption: the next core responds to the inter-core communication interruption, and reads and/or writes the shared data area through a buffer in the core during the interruption response period;
and (3) interrupting communication among the circulating cores: after the reading and/or writing operation is finished, sending inter-core communication interruption to the next core along the annular communication structure; and then, the processes of responding to interruption, data reading and/or writing and sending interruption are carried out circularly along the annular communication structure, and in the circulating process, the data interaction among the cores is completed through the shared data area.
The invention innovatively designs an internuclear data interaction method based on a ring communication structure, which effectively completes the internuclear data interaction of a multi-core processor through the processes of interrupt sending, interrupt response and data reading and writing which are circularly performed in sequence, thereby effectively avoiding the dependence of the prior art on a mature operating system, breaking through the bottleneck that internuclear data is easy to transmit errors and achieving the technical purpose of internuclear data high-speed and high-reliability transmission.
Furthermore, each core is respectively provided with at least one of a class I buffer, a class II buffer and a class III buffer;
the class I buffer is used for periodically writing data which is interrupted by low priority or needs to be sent to other cores in a main flow into the shared data area through the class I buffer; when receiving a data instruction sent by a low-priority interrupt or a main flow, a core with the class I buffer carries out periodic cycle write operation on the class I buffer, wherein data used for the write operation is sourced from the low-priority interrupt or the main flow; when a core with the class I buffer receives a timing interrupt for starting inter-core communication interrupt or responds to a high-priority interrupt of the inter-core communication interrupt, performing periodic cycle reading operation on the class I buffer, and writing read data into a shared data area;
the class II buffer is used for randomly and aperiodically writing the data which is interrupted by low priority or needs to be sent to other cores in the main flow into the shared data area through the class II buffer; when receiving a data instruction sent by a low-priority interrupt or a main flow, a core with the class II buffer carries out random write operation on the class II buffer, wherein the data used for the write operation comes from the low-priority interrupt or the main flow; when the core with the class II buffer receives the timing interruption for starting the inter-core communication interruption or the high-priority interruption for responding the inter-core communication interruption, the core carries out periodic cycle reading operation on the class II buffer and writes the read data into a shared data area;
the class III buffer is used for receiving data transmitted by other cores through a low-priority interrupt or main flow; when the core with the class-III buffer receives the timing interrupt for starting the inter-core communication interrupt or responds to the high-priority interrupt of the inter-core communication interrupt, writing data transmitted by other cores in the shared data area into the buffer, wherein the data used for writing operation is sourced from the shared data area; and when the core with the class III buffer responds to the low-priority interrupt or the main flow, the core carries out random or periodic cycle reading operation on the buffer and reads the data transmitted by other cores.
Based on the improved technical scheme, the invention creatively designs various buffers for each core, thereby effectively improving the reliability and stability of the data reading and writing process and avoiding the occurrence of the possible read-write disorder.
Furthermore, a class I write data identifier, a class I data register unit and a class I data register backup unit are arranged in the class I buffer;
when the periodic cycle write operation is carried out on the class I buffer, the class I write data identifier is set, the data to be written is written into the class I data register unit, the class I write data identifier is cleared, and the data to be written is written into the class I data register backup unit;
when the I-type buffer is subjected to periodic cycle reading operation, judging the I-type write data identification state: if the type I write data identifier is cleared, reading data in the type I data register unit; and if the type I write data identification state is set, reading the data in the type I data register backup unit.
Further, a class II write data identifier, a class II data register unit and a new data identifier are set in the class II buffer;
when random write operation is carried out on the class II buffer, a class II write data identifier is set, a new data identifier is set, data needing to be written are written into a class II data register unit, and the class II write data identifier is cleared;
and when the periodic cycle reading operation is carried out on the class II buffer, judging the class II write data identification state and the new data identification state, if the conditions of zero clearing of the class II write data identification and setting of the new data identification are met, reading the data in the class II data register unit, and zero clearing of the new data identification.
Further, a rewrite identifier and a class III data register unit are set in the class III buffer;
when periodic cycle write operation is carried out on the class III buffer, an identification set is rewritten, and data needing to be written is written into a class III data register unit;
and when random or periodic cycle reading operation is carried out on the III type buffer, the rewriting identification is cleared, and data is read from the III type data register unit.
Based on the improved technical scheme, the invention realizes the fast and efficient data interaction of various priority workflows among a plurality of processors. Through setting up special buffer, can guarantee going on smoothly, avoiding appearing the chaotic problem of reading and writing operation.
Further, in the step of starting inter-core communication interruption, one core in the ring communication structure starts inter-core communication interruption at regular time; the timed interrupt that initiates inter-core communication interrupts and the interrupt that responds to inter-core communication interrupts in each core are all the highest priority interrupts outside the reset interrupts in each core.
Further, the time length of the inter-core communication interruption timing is 1 ms.
Further, the core number of the multi-core processor is four cores.
Further, the processor is a DSP processor.
Further, the inter-core communication interrupt is an IPC interrupt.
The invention has the beneficial effects that: the invention provides an internuclear data interaction method with high-speed and high-reliability data transmission function, which can ensure that the read-write operation of a shared data area is only one core at any time, thereby effectively breaking through the bottleneck that the internuclear data is easy to transmit errors, and the method is applicable to both the presence and absence of an operating system and is easy to realize.
Drawings
FIG. 1 is a flow diagram illustrating a method for inter-core data interaction in a multi-core processor.
FIG. 2 is a diagram illustrating a data interaction state between cores of a quad-core processor.
Detailed Description
The following explains and explains the inter-core data interaction method of the multi-core processor in detail with reference to the drawings of the specification.
As shown in fig. 1 and 2, the present invention specifically discloses an inter-core data interaction method for a multi-core processor, which can effectively improve the rate and reliability of data transmission, and is suitable for data interaction among the multi-core processors.
The annular communication structure is arranged: the cores are connected in sequence, the tail core is connected with the head core to form a ring-shaped communication structure, and each core in the ring-shaped communication structure is connected with the shared data area. It should be understood that "end core" and "head core" are used to distinguish different cores for describing the construction process of the clear ring communication structure, and are not limited to a certain core in the multi-core processor, and in the construction process of a specific implementation, the "head core" may be regarded as the first core to be noticed, and the "end core" is the last core to be noticed, and the "end core" and the "head core" need to be connected in the last construction step, so as to meet the requirement that the two cores can perform interrupt communication.
And (3) starting inter-core communication interruption: in the embodiment, the timing interruption for starting the inter-core communication interruption in each core and the interruption for responding the inter-core communication are the interruptions with the highest priority except the reset interruption in each core, and in the embodiment, the timing duration for the inter-core communication interruption can be 1 ms. It should be understood that "one core in a ring communication structure" refers to any one of a plurality of cores, and in a specific implementation, one core in a ring communication structure may be specified according to actual needs; "Next core" refers to the core that is next to the current core in a ring communication structure, as shown in FIG. 2.
Responding to inter-core communication interruption: the next core responds to the inter-core communication interrupt and reads and/or writes to the shared data area through the buffer in the core during the interrupt response. If the core has multiple types of buffers, the shared data area can be read and written through the various types of buffers in a polling mode. In this embodiment, three types of buffers are given, and the following description is given.
Specifically, during the read operation and/or the write operation on the shared data area, the core is subjected to the write operation and/or the read operation. In the invention, each core is respectively provided with at least one of a class I buffer, a class II buffer and a class III buffer; in this embodiment, the read/write operation is explained in detail in terms of cores, and various buffers are defined in a constrained manner.
The class I buffer is used for periodically writing data which is interrupted by low priority or needs to be sent to other cores in a main flow into the shared data area through the class I buffer; when receiving a data instruction sent by a low-priority interrupt or a main flow, a core with the class I buffer carries out periodic cycle write operation on the class I buffer, wherein data used for the write operation is sourced from the low-priority interrupt or the main flow; and when the core with the class I buffer receives the timing interrupt for starting the inter-core communication interrupt or responds to the high-priority interrupt of the inter-core communication interrupt, performing periodic cycle reading operation on the class I buffer, and writing the read data into the shared data area.
More specifically, a class I write data identifier, a class I data register unit and a class I data register backup unit are arranged in the class I buffer.
When periodic cycle write operation is carried out on the class I buffer, the class I write data identifier is set, the data needing to be written is written into the class I data register unit, the class I write data identifier is cleared, and the data needing to be written is written into the class I data register backup unit.
When the periodic cycle reading operation is carried out on the class I buffer, the I class writing data identification state is judged: if the type I write data identifier is cleared, reading data in the type I data register unit; and if the type I write data identification state is set, reading the data in the type I data register backup unit.
The class II buffer is used for randomly and aperiodically writing the data which is interrupted by low priority or needs to be sent to other cores in the main flow into the shared data area through the class II buffer; when receiving a data instruction sent by a low-priority interrupt or a main flow, a core with the class II buffer carries out random write operation on the class II buffer, wherein the data used for the write operation comes from the low-priority interrupt or the main flow; and when the core with the class II buffer receives the timing interrupt for starting the inter-core communication interrupt or responds to the high-priority interrupt of the inter-core communication interrupt, performing periodic cycle reading operation on the class II buffer, and writing the read data into the shared data area.
More specifically, a class ii write data flag, a class ii data register unit, and a new data flag are set in the class ii buffer.
When random write operation is carried out on the class II buffer, the class II write data identifier is set, the new data identifier is set, the data needing to be written is written into the class II data register unit, and the class II write data identifier is cleared.
When periodic cycle reading operation is carried out on the class II buffer, judging the class II write data identification state and the new data identification state, if the conditions of zero clearing of the class II write data identification and setting of the new data identification are met, reading data in a class II data register unit, and zero clearing of the new data identification; if the above condition is not satisfied, the read operation is cancelled and the next step is executed.
The class III buffer is used for receiving data transmitted by other cores through a low-priority interrupt or main flow; when the core with the class-III buffer receives the timing interrupt for starting the inter-core communication interrupt or responds to the high-priority interrupt of the inter-core communication interrupt, writing data transmitted by other cores in the shared data area into the buffer, wherein the data used for writing operation is sourced from the shared data area; and when the core with the class III buffer responds to the low-priority interrupt or the main flow, the core carries out random or periodic cycle reading operation on the buffer and reads the data transmitted by other cores.
More specifically, a rewrite flag and a class iii data register unit are set in a class iii buffer;
and when periodic cycle write operation is carried out on the III type buffer, rewriting the identification set, and writing the data to be written into the III type data register unit.
And when random or periodic cycle reading operation is carried out on the III type buffer, the rewriting identification is cleared, and data is read from the III type data register unit.
And (3) interrupting communication among the circulating cores: after the reading and/or writing operation is finished, sending inter-core communication interruption to the next core along the annular communication structure; and then, the processes of responding to interruption, data reading and/or writing and sending interruption are carried out circularly along the annular communication structure, and in the circulating process, the data interaction among the cores is completed through the shared data area. In this embodiment, as shown in fig. 2, the core number of the multi-core processor is four cores, and the processor is a DSP processor.
The invention is verified for the first time in a laser strapdown inertial measurement unit (SINS) device which takes a TI multi-Core DSP chip TMS320C6674 as a controller, as shown in FIG. 2, the TMS320C6674 is provided with four DSP processors (Core 0-Core 3), each processor is provided with an independent bus and a data storage space respectively and can operate independently, and the four DSP processors can access a shared data area and a common peripheral device together. The specific implementation process of the embodiment is as follows:
(1) core1 uses 1ms timer to read and write the shared data area through necessary buffer timing, and simultaneously starts Core1 — > Core2IPC interrupt;
(2) the Core2 responds to the IPC interrupt, reads and writes the IPC shared data area through a necessary buffer, and starts the Core 2- > Core3IPC interrupt;
(3) the Core3 responds to the IPC interrupt, reads and writes the IPC shared data area through a necessary buffer, and starts the Core 3- > Core0IPC interrupt;
(4) the Core0 responds to the IPC interrupt, reads and writes the IPC shared data area through a necessary buffer, and starts the Core 0- > Core1IPC interrupt;
(5) the Core1 makes the necessary event logging flags for inter-Core communications in response to IPC interrupts.
The inter-core communication mode effectively solves a series of problems of inter-core interaction data abnormity, too slow rapid data processing, too large memory resource consumption and the like in the research and development of laser strapdown inertial measurement unit equipment, and experiments verify that the communication mode is reliable and high-speed.
Furthermore, the terms "class i" and "class ii" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "class i" or "class ii" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship, unless expressly stated otherwise. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the description herein, references to the description of the term "the present embodiment," "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and simplifications made in the spirit of the present invention are intended to be included in the scope of the present invention.
Claims (9)
1. A method for data interaction among cores of a multi-core processor is characterized in that: the method comprises the following steps:
the annular communication structure is arranged: the multiple cores are connected in sequence, the tail core is connected with the head core to form a ring-shaped communication structure, and each core in the ring-shaped communication structure is connected with the shared data area respectively;
and (3) starting inter-core communication interruption: starting inter-core communication interruption by one core in the annular communication structure, and sending the inter-core communication interruption to the next core in the annular communication structure;
responding to inter-core communication interruption: the next core responds to the inter-core communication interruption, and reads and/or writes the shared data area through a buffer in the core during the interruption response period;
and (3) interrupting communication among the circulating cores: after the reading and/or writing operation is finished, sending inter-core communication interruption to the next core along the annular communication structure; then, the interruption process of responding to interruption, data reading and/or writing and sending is carried out circularly along the annular communication structure, and in the circulation process, the data interaction between the cores is completed through the shared data area;
wherein each core is respectively provided with at least one of a class I buffer, a class II buffer and a class III buffer;
the class I buffer is used for periodically writing data which is interrupted by low priority or needs to be sent to other cores in a main flow into the shared data area through the class I buffer; when receiving a data instruction sent by a low-priority interrupt or a main flow, a core with the class I buffer carries out periodic cycle write operation on the class I buffer, wherein data used for the write operation is sourced from the low-priority interrupt or the main flow; when a core with the class I buffer receives a timing interrupt for starting inter-core communication interrupt or responds to a high-priority interrupt of the inter-core communication interrupt, performing periodic cycle reading operation on the class I buffer, and writing read data into a shared data area;
the class II buffer is used for randomly and aperiodically writing the data which is interrupted by low priority or needs to be sent to other cores in the main flow into the shared data area through the class II buffer; when receiving a data instruction sent by a low-priority interrupt or a main flow, a core with the class II buffer carries out random write operation on the class II buffer, wherein the data used for the write operation comes from the low-priority interrupt or the main flow; when the core with the class II buffer receives the timing interruption for starting the inter-core communication interruption or the high-priority interruption for responding the inter-core communication interruption, the core carries out periodic cycle reading operation on the class II buffer and writes the read data into a shared data area;
the class III buffer is used for receiving data transmitted by other cores through a low-priority interrupt or main flow; when the core with the class-III buffer receives the timing interrupt for starting the inter-core communication interrupt or responds to the high-priority interrupt of the inter-core communication interrupt, writing data transmitted by other cores in the shared data area into the buffer, wherein the data used for writing operation is sourced from the shared data area; and when the core with the class III buffer responds to the low-priority interrupt or the main flow, the core carries out random or periodic cycle reading operation on the buffer and reads the data transmitted by other cores.
2. The method of claim 1, wherein the method comprises: setting a class I write data identifier, a class I data register unit and a class I data register backup unit in the class I buffer;
when the periodic cycle write operation is carried out on the class I buffer, the class I write data identifier is set, the data to be written is written into the class I data register unit, the class I write data identifier is cleared, and the data to be written is written into the class I data register backup unit;
when the I-type buffer is subjected to periodic cycle reading operation, judging the I-type write data identification state: if the type I write data identifier is cleared, reading data in the type I data register unit; and if the type I write data identification state is set, reading the data in the type I data register backup unit.
3. The method of claim 2, wherein the method comprises: setting a class II write data identifier, a class II data register unit and a new data identifier in the class II buffer;
when random write operation is carried out on the class II buffer, a class II write data identifier is set, a new data identifier is set, data needing to be written are written into a class II data register unit, and the class II write data identifier is cleared;
and when the periodic cycle reading operation is carried out on the class II buffer, judging the class II write data identification state and the new data identification state, if the conditions of zero clearing of the class II write data identification and setting of the new data identification are met, reading the data in the class II data register unit, and zero clearing of the new data identification.
4. The method of claim 3, wherein the method comprises: setting a rewrite identifier and a class III data register unit in the class III buffer;
when periodic cycle write operation is carried out on the class III buffer, an identification set is rewritten, and data needing to be written is written into a class III data register unit;
and when random or periodic cycle reading operation is carried out on the III type buffer, the rewriting identification is cleared, and data is read from the III type data register unit.
5. The method of any one of claims 1 to 4 for data interaction between cores of a multicore processor, wherein:
in the step of starting inter-core communication interruption, one core in the annular communication structure starts inter-core communication interruption at fixed time;
the timed interrupt that initiates inter-core communication interrupts and the interrupt that responds to inter-core communication interrupts in each core are all the highest priority interrupts outside the reset interrupts in each core.
6. The method of claim 5, wherein the method comprises: the time length of the inter-core communication interruption timing is 1 ms.
7. The method of claim 1 or 6, wherein the method comprises: the core number of the multi-core processor is four cores.
8. The method of claim 7, wherein the method comprises: the processor is a DSP processor.
9. The method of claim 1 or 8, wherein the method comprises: the inter-core communication interrupt is an IPC interrupt.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710793934.9A CN107590100B (en) | 2017-09-06 | 2017-09-06 | Inter-core data interaction method of multi-core processor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710793934.9A CN107590100B (en) | 2017-09-06 | 2017-09-06 | Inter-core data interaction method of multi-core processor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107590100A CN107590100A (en) | 2018-01-16 |
| CN107590100B true CN107590100B (en) | 2020-06-19 |
Family
ID=61051077
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710793934.9A Active CN107590100B (en) | 2017-09-06 | 2017-09-06 | Inter-core data interaction method of multi-core processor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107590100B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113192237B (en) * | 2020-01-10 | 2023-04-18 | 阿里巴巴集团控股有限公司 | Internet of things equipment supporting TEE and REE and method for realizing communication between TEE and REE |
| CN113220541B (en) * | 2021-06-10 | 2021-09-07 | 北京全路通信信号研究设计院集团有限公司 | Memory inspection method and system of multi-core processor |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101013383A (en) * | 2007-02-13 | 2007-08-08 | 杭州华为三康技术有限公司 | System and method for implementing packet combined treatment by multi-core CPU |
| CN101132336A (en) * | 2007-10-17 | 2008-02-27 | 中国人民解放军国防科学技术大学 | High-speed asynchronous interlinkage communication network of heterogeneous multi-nucleus processor |
| CN102141974A (en) * | 2011-04-11 | 2011-08-03 | 复旦大学 | Internuclear communication method of multinuclear processor and circuit structure thereof |
| CN102270189A (en) * | 2011-06-17 | 2011-12-07 | 西安电子科技大学 | Inter-core communication method based on FPGA (Field Programmable Gate Array) multi-core system |
| CN102521201A (en) * | 2011-11-16 | 2012-06-27 | 刘大可 | Multi-core DSP (digital signal processor) system-on-chip and data transmission method |
| CN102855214A (en) * | 2011-06-27 | 2013-01-02 | 上海华为技术有限公司 | Method for implementing data consistency and multi-core system |
| CN102929834A (en) * | 2012-11-06 | 2013-02-13 | 无锡江南计算技术研究所 | Many-core processor and inter-core communication method thereof and main core and auxiliary core |
| CN105893320A (en) * | 2016-03-29 | 2016-08-24 | 浙江大学 | Remote task function calling method oriented at multi-core processor |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9519943B2 (en) * | 2010-12-07 | 2016-12-13 | Advanced Micro Devices, Inc. | Priority-based command execution |
-
2017
- 2017-09-06 CN CN201710793934.9A patent/CN107590100B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101013383A (en) * | 2007-02-13 | 2007-08-08 | 杭州华为三康技术有限公司 | System and method for implementing packet combined treatment by multi-core CPU |
| CN101132336A (en) * | 2007-10-17 | 2008-02-27 | 中国人民解放军国防科学技术大学 | High-speed asynchronous interlinkage communication network of heterogeneous multi-nucleus processor |
| CN102141974A (en) * | 2011-04-11 | 2011-08-03 | 复旦大学 | Internuclear communication method of multinuclear processor and circuit structure thereof |
| CN102270189A (en) * | 2011-06-17 | 2011-12-07 | 西安电子科技大学 | Inter-core communication method based on FPGA (Field Programmable Gate Array) multi-core system |
| CN102855214A (en) * | 2011-06-27 | 2013-01-02 | 上海华为技术有限公司 | Method for implementing data consistency and multi-core system |
| CN102521201A (en) * | 2011-11-16 | 2012-06-27 | 刘大可 | Multi-core DSP (digital signal processor) system-on-chip and data transmission method |
| CN102929834A (en) * | 2012-11-06 | 2013-02-13 | 无锡江南计算技术研究所 | Many-core processor and inter-core communication method thereof and main core and auxiliary core |
| CN105893320A (en) * | 2016-03-29 | 2016-08-24 | 浙江大学 | Remote task function calling method oriented at multi-core processor |
Non-Patent Citations (4)
| Title |
|---|
| Cell处理器上软件缓存的设计与实现;孙守航等;《计算机工程》;20110131;第37卷(第2期);全文 * |
| The Cell Processor;David T. Wang;《ISSCC 2005》;20051231;全文 * |
| 基于ARM Cortex-A9 MPCore嵌入式多核操作系统内核研究与实现;蔡人和;《中国优秀硕士学位论文全文数据库 信息科技辑》;20170215;第2017卷(第2期);全文 * |
| 多核处理器核间通信技术研究;杨国芳;《中国优秀硕士学位论文全文数据库信息科技辑》;20120515;第2012年卷(第5期);第3节 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107590100A (en) | 2018-01-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102866971B (en) | Device, the system and method for transmission data | |
| EP3091434B1 (en) | Chip starting method, multi-core processor chip and storage medium | |
| CN109688058B (en) | Message processing method and device and network equipment | |
| US8352710B2 (en) | Off-loading of processing from a processor blade to storage blades | |
| CN104321716B (en) | Use device idle duration information optimizes energy efficiency | |
| EP2187308A1 (en) | Method, device and system for storing data in cache in case of power failure | |
| CN111061587A (en) | Communication control method, device, equipment and storage medium of I2C bus | |
| CN107590100B (en) | Inter-core data interaction method of multi-core processor | |
| US10409744B1 (en) | Low-latency wake-up in a peripheral device | |
| CN106489132A (en) | The method of read-write data, device, storage device and computer system | |
| CN103092798A (en) | On-chip system and method for accessing to equipment under bus | |
| CN109525473A (en) | A kind of MCU extension CAN method, system, MCU and computer media | |
| CN104917696A (en) | Periodic and non-periodic mixed communication method and system used for low-speed serial bus | |
| CN105161132A (en) | NVMe SSD read-only protection method based on FPGA | |
| CN105528314A (en) | Data processing method and control equipment | |
| CN104484260A (en) | Simulation monitoring circuit based on GJB289 bus interface SoC (system on a chip) | |
| CN110362448A (en) | A kind of GPU management-control method and relevant apparatus | |
| US20140359187A1 (en) | Control apparatus and control method | |
| CN102640129B (en) | For direct memory access (DMA) device and the method for operating thereof of multiple nucleus system | |
| CN114567445A (en) | Signature verification data transmission method, device, equipment and medium | |
| CN110659122A (en) | SSD interruption implementation method and device | |
| CN107168227B (en) | The communicating control method and device of more kernel Embedded PLCs | |
| WO2020014836A1 (en) | Method, device and system for acquiring link negotiation information of optical module | |
| CN110661869A (en) | Node online method, system, device, equipment and computer storage medium | |
| CN104932947A (en) | Barrier synchronization method and device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |