CN107566092B - Data processing method and device - Google Patents

Data processing method and device Download PDF

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CN107566092B
CN107566092B CN201610512135.5A CN201610512135A CN107566092B CN 107566092 B CN107566092 B CN 107566092B CN 201610512135 A CN201610512135 A CN 201610512135A CN 107566092 B CN107566092 B CN 107566092B
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data sequence
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CN107566092A (en
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吴涛
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/02—Arrangements for detecting or preventing errors in the information received by diversity reception
    • H04L1/06—Arrangements for detecting or preventing errors in the information received by diversity reception using space diversity
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/26—Systems using multi-frequency codes

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Abstract

The invention provides a data processing method and a data processing device, wherein the method comprises the following steps: determining a first data sequence comprising N first data symbols and a second data sequence comprising N second data symbols; performing conjugate operation and inversion operation on a first second data symbol of the second data sequence, and performing conjugate operation, reverse operation and inversion operation on the last (N-1) second data symbols to obtain a third data sequence; performing conjugate operation on the first data symbol of the first data sequence and performing conjugate operation and reverse operation on the last (N-1) first data symbols to obtain a fourth data sequence; determining a first signal stream to be transmitted according to the first data sequence and the third data sequence; and determining a second signal stream to be transmitted according to the second data sequence and the fourth data sequence. The data processing method and device provided by the invention can obtain the signal stream which is based on Alamouti coding and is suitable for single carrier frequency domain equalization.

Description

Data processing method and device
Technical Field
The invention relates to the field of single-carrier frequency domain equalization (SC-FDE), in particular to a data processing method and device in the field of single-carrier equalization.
Background
In a broadband wireless communication system, frequency selective fading caused by multipath transmission may seriously affect the reliability of communication. The single carrier frequency domain equalization technology is one of effective ways to overcome multipath fading.
The Alamouti coding is widely applied to a multi-antenna input-output (english: multiple-input multiple-output, abbreviated as MIMO) system because of its simple design and convenient decoding. The Alamouti coding includes Space Time Block Coding (STBC).
Space Frequency Block Coding (SFBC) is a technology that combines STBC and Orthogonal Frequency Division Multiplexing (OFDM) technologies, and can obtain higher spectral efficiency, transmission rate, and communication quality.
However, the existing Alamouti coding technique is only suitable for single carrier time domain equalization.
Disclosure of Invention
The invention provides a data processing method and device, which can obtain a signal stream based on Alamouti coding and suitable for single carrier frequency domain equalization.
In a first aspect, the present invention provides a method of data processing, the method comprising:
determining a first data sequence and a second data sequence, wherein the first data sequence comprises N first data symbols, the second data sequence comprises N second data symbols, and N is an integer greater than 1;
performing complex conjugate operation and inversion operation on a first second data symbol of the second data sequence, and performing complex conjugate operation, reverse operation and inversion operation on the last (N-1) second data symbols of the second data sequence to obtain a third data sequence;
performing complex conjugate operation on a first data symbol of the first data sequence, and performing complex conjugate operation and reverse operation on the last (N-1) first data symbols of the first data sequence to obtain a fourth data sequence;
determining a first signal stream to be transmitted according to the first data sequence and the third data sequence, and determining a second signal stream to be transmitted according to the second data sequence and the fourth data sequence.
The data processing method provided by the invention can obtain the signal stream which is based on Alamouti coding and is suitable for single carrier frequency domain equalization.
With reference to the first aspect, in a first possible implementation manner of the first aspect, the determining the first data sequence and the second data sequence includes: acquiring input M first target data symbols, M second target data symbols and G first protection symbols; determining the first data sequence and the second data sequence according to the M first target data symbols, the M second target data symbols and the G first guard symbols.
With reference to the first possible implementation manner of the first aspect, in a second possible implementation manner of the first aspect, the determining the first data sequence according to the M first target data symbols, the M second target data symbols, and the G first guard symbols includes: performing complex conjugate operation and negation operation on the G first protection symbols to obtain G second protection symbols; the G first guard symbols are inserted before the M first target data symbols, and the G second guard symbols are inserted after the M first target data symbols, resulting in the first data sequence.
With reference to the first or the second possible implementation manner of the first aspect, in a third possible implementation manner of the first aspect, the determining the second data sequence according to the M first target data symbols, the M second target data symbols, and the G first guard symbols includes: inserting G protection symbols obtained by performing complex conjugate operation, reverse operation and inversion operation on the G second protection symbols after a first protection symbol in the G first protection symbols to obtain (G +1) third protection symbols; performing complex conjugate operation and reverse order operation on the last (G-1) first protection symbols of the G first protection symbols to obtain (G-1) fourth protection symbols; the (G +1) third guard symbols are inserted before the M second target data symbols, and the (G-1) fourth guard symbols are inserted after the M second target data symbols, resulting in the second data sequence.
With reference to the third possible implementation manner of the first aspect, in a fourth possible implementation manner of the first aspect, the performing complex conjugate operation and inverse operation on the first second data symbol of the second data sequence, and performing complex conjugate operation, inverse operation, and inverse operation on the last (N-1) second data symbols of the second data sequence to obtain a third data sequence includes: inserting (G-1) protection symbols obtained by performing complex conjugate operation, reverse operation and inversion operation on the (G-1) fourth protection symbols after the protection symbols obtained by performing complex conjugate operation and inversion operation on the first third protection symbol in the (G +1) third protection symbols to obtain G fifth protection symbols; performing complex conjugate operation, reverse operation and inversion operation on the M second target data symbols to obtain M third target data symbols; inserting the G fifth guard symbols before the M third target data symbols, and inserting the G second guard symbols after the M third target data symbols to obtain the third data sequence.
With reference to any one of the second to fourth possible implementation manners of the first aspect, in a fifth possible implementation manner of the first aspect, the performing a complex conjugate operation on a first data symbol of the first data sequence, and performing a complex conjugate operation and a reverse order operation on last (N-1) first data symbols of the first data sequence to obtain a fourth data sequence includes: inserting G protection symbols obtained by performing complex conjugate operation and reverse order operation on the G second protection symbols after the protection symbol obtained by performing complex conjugate operation on the first protection symbol in the G first protection symbols to obtain (G +1) sixth protection symbols; performing complex conjugate operation and reverse operation on the M first target data symbols to obtain M fourth target data symbols; the (G +1) sixth guard symbols are inserted before the M fourth target data symbols, and the (G-1) fourth guard symbols are inserted after the M fourth target data symbols, resulting in the fourth data sequence.
According to the data processing method provided by the embodiment of the invention, a new frame structure is constructed based on the Alamouti coding mode through M first target data symbols which need to be actually sent through a first antenna, M second target data symbols which need to be actually sent through a second antenna and known G first protection symbols, so that after receiving two reconstructed signal streams, a receiving device can perform frequency domain equalization processing on the two signal streams.
With reference to the fifth possible implementation manner of the first aspect, in a sixth possible implementation manner of the first aspect, the determining a first signal stream to be transmitted according to the first data sequence and the third data sequence, and determining a second signal stream to be transmitted according to the second data sequence and the fourth data sequence includes: inserting the G second guard symbols before the first data sequence; determining the first signal stream according to the G second guard symbols, the first data sequence and the third data sequence; inserting the (G-1) fourth guard symbols before the second data sequence; determining the second signal stream according to the (G-1) fourth guard symbols, the second data sequence and the fourth data sequence.
The data processing method of the embodiment of the invention can be used as a guard interval by inserting a plurality of guard symbols in front of and behind the target data symbol, and can reduce the multipath interference in the data transmission process.
With reference to the first aspect and any one possible implementation manner of the first to sixth possible implementation manners of the first aspect, in a seventh possible implementation manner of the first aspect, the method further includes: the first signal stream and the second signal stream are transmitted through different antennas.
In a second aspect, the present invention provides a method of data processing, the method comprising:
determining a first signal stream transmitted by a first antenna and a second signal stream transmitted by a second antenna, wherein the first signal stream includes a first data sequence and a third data sequence, the second signal stream includes a second data sequence and a fourth data sequence, the first data sequence includes N first data symbols, the second data sequence includes N second data symbols, the third data sequence is N data symbols obtained by performing complex conjugate operation and inversion operation on the first second data symbol of the second data sequence and performing complex conjugate operation, inversion operation and inversion operation on the latter (N-1) second data symbols of the second data sequence, the fourth data sequence is N data symbols obtained by performing complex conjugate operation on the first data symbol of the first data sequence and performing complex conjugate operation and inversion operation on the latter (N-1) first data symbols of the first data sequence, n is an integer greater than 1;
performing frequency domain equalization on the first signal stream and the second signal stream to obtain a frequency domain response of the first data sequence and a frequency domain response of the second data sequence;
and determining M first target data symbols and M second target data symbols according to the frequency domain response of the first data sequence and the frequency domain response of the second data sequence, wherein M is an integer greater than 1.
The data processing method provided by the invention can obtain the signal stream which is based on Alamouti coding and is suitable for single carrier frequency domain equalization.
With reference to the second aspect, in a first possible implementation manner of the second aspect, the frequency-domain equalizing the first signal stream and the second signal stream to obtain a frequency-domain response of the first data sequence and a frequency-domain response of the second data sequence includes: performing a discrete fourier transform on the first signal stream and the second signal stream to obtain a frequency domain response of the first signal stream and a frequency domain response of the second signal stream; and obtaining the frequency domain response of the first data sequence and the frequency domain response of the second data sequence according to the frequency domain response of the first signal stream, the conjugate of the frequency domain response of the second signal stream, the frequency domain response of the channel from the first transmitting antenna to the receiving antenna and the frequency domain response of the channel from the second transmitting antenna to the receiving antenna.
With reference to the second aspect or the first possible implementation manner of the second aspect, in a second possible implementation manner of the second aspect, the frequency-domain equalizing the first signal stream and the second signal stream to obtain a frequency-domain response of the first data sequence and a frequency-domain response of the second data sequence includes:
determining a frequency domain response of the first data sequence and a frequency domain response of the second data sequence according to the following formula:
Figure GDA0002361940940000051
wherein z is11,f(n) represents the frequency domain response of the first data sequence, z21,f(n) denotes the frequency domain response of the second data sequence, r1,f(n) represents the frequency domain response of the first received signal stream, r2,f(n) denotes the conjugate of the frequency domain response of the received second signal stream, h11,f(n) signals representing a first transmit antenna to a first receive antennaFrequency domain response of the track, h12,f(n) represents the frequency domain response of the channel from the second transmit antenna to the first receive antenna, h12,f(n) denotes the conjugate of the frequency domain response of the channel from the second transmit antenna to the first receive antenna, h11,f(n) represents the conjugate of the frequency domain response of the channel from the first transmit antenna to the first receive antenna.
It should be understood that since
Figure GDA0002361940940000052
Thus can be based on
Figure GDA0002361940940000053
Obtaining z can be obtained from the formula in the second possible implementation of the second aspect11,f(n) and z21,f(n)。
With reference to the second aspect, the first or second possible implementation manner of the second aspect, in a third possible implementation manner of the second aspect, the determining M first target data symbols and M second target data symbols according to the frequency domain response of the first data sequence and the frequency domain response of the second data sequence includes: performing inverse discrete Fourier transform on the frequency domain response of the first data sequence to obtain the first data sequence; deleting the first G first protection symbols inserted in the first data sequence and the last G second protection symbols inserted in the first data sequence to obtain M first target data symbols; performing inverse discrete Fourier transform on the frequency domain response of the second data sequence to obtain the second data sequence; deleting the first (G +1) third protection symbols inserted in the second data sequence and the last (G-1) fourth protection symbols inserted in the second data sequence to obtain the M second target data symbols.
With reference to the second aspect and any one possible implementation manner of the first to third possible implementation manners of the second aspect, in a fourth possible implementation manner of the second aspect, before the determining the first signal stream transmitted by the first antenna and the second signal stream transmitted by the second antenna, the method further includes: receiving a third signal stream transmitted by the first antenna and a fourth signal stream transmitted by the second antenna, wherein the third signal stream includes G second guard symbols, the first data sequence and the third data sequence, and the fourth signal stream includes (G-1) fourth guard symbols, the second data sequence and the fourth data sequence; the determining a first signal stream transmitted by a first antenna and a second signal stream transmitted by a second antenna comprises: deleting the G second guard symbols in the third signal stream to obtain the first signal stream; deleting the (G-1) fourth guard symbols in the fourth signal stream to obtain the second signal stream.
In a third aspect, the present invention provides an apparatus for data processing, configured to perform the method in the first aspect or any possible implementation manner of the first aspect. In particular, the apparatus comprises means for performing the method of the first aspect described above or any possible implementation manner of the first aspect.
In a fourth aspect, the present invention provides a data processing apparatus configured to perform the method of the second aspect or any possible implementation manner of the second aspect. In particular, the apparatus comprises means for performing the method of the second aspect described above or any possible implementation of the second aspect.
In a fifth aspect, the present invention provides an apparatus for data processing, the apparatus comprising: receiver, transmitter, memory, processor and bus system. Wherein the receiver, the transmitter, the memory and the processor are connected via the bus system, the memory is configured to store instructions, the processor is configured to execute the instructions stored by the memory and control the transmitter to transmit the protection symbol, and when the processor executes the instructions stored by the memory, the method of the first aspect or any possible implementation manner of the first aspect can be implemented.
In a sixth aspect, the present invention provides an apparatus for data processing, where the head-end device includes: receiver, transmitter, memory, processor and bus system. Wherein the receiver, the transmitter, the memory and the processor are connected by the bus system, the memory is configured to store instructions, the processor is configured to execute the instructions stored by the memory and control the transmitter to transmit the protection symbol, and the processor, when executing the instructions stored by the memory, is capable of implementing the method of the second aspect or any possible implementation manner of the second aspect.
In a seventh aspect, the present invention provides a computer-readable medium for storing a computer program comprising instructions for performing the method of the first aspect or any possible implementation manner of the first aspect.
In an eighth aspect, the invention provides a computer-readable medium for storing a computer program comprising instructions for carrying out the method of the second aspect or any possible implementation of the second aspect.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required to be used in the embodiments of the present invention will be briefly described below.
Fig. 1 is a schematic diagram of a scenario of transmitting data to which an embodiment of the present invention is applicable.
Fig. 2 is a schematic structural diagram of a Physical Layer Convergence Procedure (PLCP) protocol data unit (PPDU) in an existing 802.11 ad.
Fig. 3 is a schematic structural diagram of data blocks of a PPDU frame in a conventional single carrier frequency domain system.
FIG. 4 is a schematic flow chart diagram of a method of data processing of an embodiment of the present invention.
FIG. 5 is a schematic flow chart diagram of another method of data processing in accordance with an embodiment of the present invention.
Fig. 6 is a schematic structural diagram of a data block based on Alamouti coding according to an embodiment of the present invention.
Fig. 7 is a schematic block diagram of a data processing apparatus of an embodiment of the present invention.
FIG. 8 is a schematic block diagram of another data processing apparatus of an embodiment of the present invention.
FIG. 9 is a schematic block diagram of yet another data processing apparatus of an embodiment of the present invention.
FIG. 10 is a schematic block diagram of yet another data processing apparatus of an embodiment of the present invention.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.
The technical scheme of the invention can be applied to OFDM systems, such as WLAN systems, in particular to wireless fidelity (WiFi) and the like; the technical method of the invention can also be applied to a Single Carrier (SC) system. Of course, the method of the embodiment of the present invention may also be applied to other types of OFDM systems, and the embodiment of the present invention is not limited herein.
Correspondingly, the sending end device and the receiving end device may be user Stations (STA) in the WLAN, and the user stations may also be called systems, subscriber units, access terminals, mobile stations, remote terminals, mobile devices, user terminals, wireless communication devices, user agents, user devices, or User Equipment (UE). The STA may be a cellular phone, a cordless phone, a Session Initiation Protocol (SIP) phone, a Wireless Local Loop (WLL) station, a Personal Digital Assistant (PDA), a handheld device having wireless local area network (e.g., Wi-Fi) communication capability, a computing device, or other processing device connected to a wireless modem.
In addition, the sending end device and the receiving end device may also be Access Points (APs) in the WLAN, and the APs may be configured to communicate with the access terminal through a wireless local area network, and transmit data of the access terminal to the network side, or transmit data from the network side to the access terminal.
The receiving end device may be a correspondent end corresponding to the sending end device.
Fig. 1 is a schematic diagram of a scenario of transmitting data to which an embodiment of the present invention is applicable. The scenario system shown in fig. 1 may be a WLAN system, and the system of fig. 1 includes one or more access points (AP 110 is shown in fig. 1) and one or more stations (STA 121 and STA122 are shown in fig. 1), wherein wireless communication between access point 110 and station 121 or station 122 may be performed through various standards.
It should be understood that, in the embodiment of the present invention, data transmission may be performed between the access point and the station through a physical layer protocol data unit, where the physical layer protocol data unit is a PPDU frame, which may also be referred to as a physical layer protocol data unit frame in 802.11ad, and this is not limited in the embodiment of the present invention.
It should also be understood that the PPDU in the embodiments of the present invention may meet the 802.11ad standard operating in the 60GHz band.
For example, FIG. 2 is a diagram of a PPDU of the 802.11ad standard in accordance with one embodiment of the present invention. The PPDU shown in fig. 3 includes: a Short Training Field (STF), a channel estimation field (CE), an indicator signal field (Header), a Data field (Data), etc., wherein the STF is used for synchronization, frequency offset estimation, and automatic gain control field (AGC) adjustment; the CE is used for channel estimation; the indication signal field is used to indicate an indication signal, and may be used to indicate a modulation scheme of the data frame, for example.
It should also be understood that the signal to be transmitted in the embodiment of the present invention may be a Data block in Data, which is not limited in the embodiment of the present invention.
For example, the Data portion in a PPDU in the 802.11ad standard is made up of several Data blocks. Each data block is composed of a data sequence of 448 symbols and a guard interval of 64 symbols.
Fig. 3 shows a schematic block diagram of data blocks of a PPDU frame in a single carrier frequency domain system. As shown in fig. 3, the data block includes: n symbols constituting transmission data s (k), k being 1, …, N, G (k) before and after s (k), k being 1, …, G, for combating multipath interference.
Specifically, the existing single carrier frequency domain equalization system performs the following process of frequency domain equalization on the signal stream:
the signal stream transmitted by the transmitting device is as shown in equation (1):
Figure GDA0002361940940000081
specifically, after the sending device sends the signal stream described in equation (1) to the receiving device, the receiving device performs Discrete Fourier Transform (DFT) processing on x (k) part in the received signal stream to obtain equation (2):
rf(k)＝hf(k)xf(k)+nf(k) (2)
wherein x isf(k)＝DFT{x(k)}，hf(k) Is the frequency domain response of the channel.
It should be understood that the receiving device pair rf(k) Performing frequency domain equalization to obtain
Figure GDA0002361940940000091
To pair
Figure GDA0002361940940000092
And (3) performing Inverse Discrete Fourier Transform (IDFT) to obtain an estimate of x (k).
Optionally, the frequency domain equalization method includes a Zero Forcing (ZF) method or a linear minimum mean square error (lmmse) method, which is not limited in this embodiment of the present invention.
In addition, the existing process of coding the signal stream based on Alamouti coding at the transmitting device end and the process of performing single carrier time domain equalization at the receiving device end are as follows:
the transmitting equipment carries out space-time coding on the information bits to be transmitted, namely, each information bit is divided into one group, two groups of continuous bits are subjected to constellation mapping to obtain two modulation symbols x and y, and then the two modulation symbols x and y are subjected to constellation mappingThe symbols are fed into a coder to obtain modulation symbols-y*、x*。
The transmitting device passes through two different antennas at a first time t1Transmitting a signal (x, y) at a second time t2Transmitting signal (-y)*,x*) And assuming that the receiving device receives a signal through one antenna, the signal stream received by the receiving device can be represented by equation (3):
Figure GDA0002361940940000093
where h (nm, t) denotes a channel from the mth transmitting antenna to the nth receiving antenna at the tth time.
If the channels of two adjacent time instants can be considered to be nearly equal, i.e.
Figure GDA0002361940940000094
The signal stream received by the receiving device can be represented by equation (4):
Figure GDA0002361940940000095
optionally, the sending device may include two antennas and send the two signal streams through the two antennas, and the sending device may further include multiple antennas and send the two signal streams through two antennas of the multiple antennas, which is not limited in this embodiment of the present invention.
Specifically, the receiving device multiplies the r matrix by the transposed conjugate matrix of the H channel matrix to obtain the time domain equalization result of the transmitted signal (x, y).
If the receiving device is to perform frequency domain equalization on the received signal stream, x, y, x in equation (3) are required*And y*Performing DFT to obtain xf、yf、x* fAnd y* f。
However, due to xfIs not equal to x* f，yfIs also not equal to y* fTherefore, the above Alamouti coding is not suitable for single carrier frequency domain equalization.
The invention provides a data processing method, which can obtain a signal stream based on Alamouti coding and suitable for single carrier frequency domain equalization.
Let us assume, a time-domain signal s1(k) K is 0, …, M-1, which is subjected to DFT to obtain frequency domain response s1f(n)。
We can establish s by equation (5)2(k) Frequency domain response of and s1Relation between frequency domain responses of (k):
Figure GDA0002361940940000101
from equation (5) we can get: satisfy the requirement of
Figure GDA0002361940940000102
Of the time domain signal s2(k) And the frequency domain response of (c) and (d) above1(k) Is a conjugate relationship.
Therefore, the processing principle of the signal stream which can be based on the Alamouti coding and is suitable for single carrier frequency domain equalization is provided by the invention as follows: by Alamouti coding the signal stream to be transmitted by the transmitting device, s is made to1The result of the DFT transform of (k) equals s2(k) The conjugate of the DFT transform result, thereby enabling the receiving device to perform frequency domain equalization processing on the received signal stream through equation (4).
Specifically, the data processing apparatus reconstructs a frame structure from a first data sequence including N first data symbols, performs a conjugate process on a first data symbol in the first data sequence, and performs a complex conjugate process and a reverse order process on the last (N-1) first data symbols in the first data sequence, resulting in a second data sequence composed of N second data symbols, and the frequency domain response of the second data sequence is equal to the conjugate of the frequency domain response of the first data sequence, and reconstructs the frame structure from such first and second data sequences.
Fig. 4 shows a schematic flowchart of a method 100 for data processing according to an embodiment of the present invention, where the method 100 is applied to the scenario shown in fig. 1, and may be executed by a data processing apparatus at the sending device side, and optionally, the data processing apparatus may be a separate device disposed at the signal input end of the transmitting antenna, or may be integrated in the sending device as a data processing unit in the sending device, which is not limited in this embodiment of the present invention.
S410, determining a first data sequence and a second data sequence, where the first data sequence includes N first data symbols, the second data sequence includes N second data symbols, and N is an integer greater than 1.
Specifically, the data processing apparatus may determine M first target data symbols, M second target data symbols, and G first guard symbols input to a transmitting device; determining the first data sequence and the second data sequence according to the M first target data symbols, the M second target data symbols and the G first guard symbols.
Optionally, the M first target data symbols are actually to-be-transmitted data in the first signal stream, and the M second target data symbols are actually to-be-transmitted data in the second signal stream, for example, may be a sequence of M data symbols, which is not limited in this embodiment of the present invention.
It should be understood that the G protection symbols may be a protection interval, and the protection interval may be composed of G pieces of 1 or-1 obtained through training in advance, for example, but the embodiment of the present invention does not limit this.
Optionally, the G known first guard symbols may be pre-trained, or pre-defined guard symbols as guard intervals, which is not limited in this embodiment of the present invention.
Optionally, the data processing apparatus may perform complex conjugate operation and negation operation on the G first guard symbols to obtain G second guard symbols; the G first guard symbols are inserted before the M first target data symbols, and the G second guard symbols are inserted after the M first target data symbols, resulting in the first data sequence.
Optionally, the data processing apparatus may insert, after a first guard symbol of the G first guard symbols, G guard symbols obtained by performing complex conjugate operation, reverse order operation, and negation operation on the G second guard symbols, to obtain (G +1) third guard symbols; performing complex conjugate operation and reverse order operation on the last (G-1) first protection symbols of the G first protection symbols to obtain (G-1) fourth protection symbols; the (G +1) third guard symbols are inserted before the M second target data symbols, and the (G-1) fourth guard symbols are inserted after the M second target data symbols, resulting in the second data sequence.
S420, performing complex conjugate operation and negation operation on the first second data symbol of the second data sequence, and performing complex conjugate operation, inverse operation and negation operation on the last (N-1) second data symbols of the second data sequence to obtain a third data sequence.
Optionally, the data processing apparatus may insert (G-1) protection symbols obtained by performing a complex conjugate operation, a reverse order operation, and an inversion operation on the (G-1) fourth protection symbols after performing a complex conjugate operation and an inversion operation on a first third protection symbol of the (G +1) third protection symbols to obtain G fifth protection symbols; performing complex conjugate operation, reverse operation and inversion operation on the M second target data symbols to obtain M third target data symbols; inserting the G fifth guard symbols before the M third target data symbols, and inserting the G second guard symbols after the M third target data symbols to obtain the third data sequence.
It can be seen that G fifth protection symbols are inserted before the M third data, G second protection symbols are inserted after the M third data, and the obtained third data sequence is obtained by performing complex conjugate operation and inversion operation on the first second data symbol of the second data sequence, and performing complex conjugate operation, inversion operation and inversion operation on the last (N-1) second data symbols of the second data sequence.
S430, performing complex conjugate operation on the first data symbol of the first data sequence, and performing complex conjugate operation and reverse order operation on the last (N-1) first data symbols of the first data sequence to obtain a fourth data sequence.
It should be understood that S420 and S430 are not performed in a sequential order.
Optionally, the data processing apparatus may insert, after the guard symbol obtained by performing the complex conjugate operation on the first guard symbol of the G first guard symbols, G guard symbols obtained by performing the complex conjugate operation and the reverse order operation on the G second guard symbols, to obtain (G +1) sixth guard symbols; performing complex conjugate operation and reverse operation on the M first target data symbols to obtain M fourth target data symbols; the (G +1) sixth guard symbols are inserted before the M fourth target data symbols, and the (G-1) fourth guard symbols are inserted after the M fourth target data symbols, resulting in the fourth data sequence.
It can be seen that (G +1) sixth protection symbols are inserted before the M fourth target data symbols, and (G-1) fourth protection symbols are inserted after the M fourth target data symbols, so that the obtained fourth data sequence is a fourth data sequence obtained by performing complex conjugate operation on the first data symbol of the first data sequence, and performing complex conjugate operation and reverse order operation on the (N-1) last first data symbols of the first data sequence.
It should be understood that the data processing apparatus may perform encoding processing on data sequences transmitted through two different antennas at two adjacent time instants such that a first data sequence transmitted through the antenna 1 at the first time instant and a fourth data sequence transmitted through the antenna 2 at the second time instant satisfy equations (6) and (7), and a third data sequence transmitted through the antenna 1 at the second time instant and a fourth data sequence transmitted through the antenna 2 at the second time instant satisfy equations (8) and (9), such that a frequency domain response of a conjugate of the first data sequence is equal to a frequency domain response of the fourth data sequence, and a frequency domain response of a conjugate of the second data sequence is equal to a frequency domain response of the third data sequence.
x1(k)＝k,k＝0,1,...,M-1 (6)
x4(k)＝x*1(mod(M-k),M) (7)
x2(k)＝k,k＝0,1,...,M-1 (8)
x3(k)＝-x*2(mod(M-k),M) (9)
S440, determining a first signal stream to be transmitted according to the first data sequence and the third data sequence, and determining a second signal stream to be transmitted according to the second data sequence and the fourth data sequence.
Specifically, the data processing apparatus may insert the G second protection symbols before the first data sequence, and determine a signal stream composed of the G second protection symbols, the first data sequence, and the third data sequence as a first signal stream; the data processing apparatus may further insert the (G-1) fourth guard symbols before the second data sequence, and determine a signal stream composed of the (G-1) fourth guard symbols, the second data sequence, and the fourth data sequence as a second signal stream.
It should be understood that G second guard symbols inserted in the first signal stream may serve as guard intervals of the first signal stream, and (G-1) fourth guard symbols inserted in the second signal stream may serve as guard intervals of the second signal stream, which is not limited in this embodiment of the present invention.
Optionally, since the number of the fourth protection symbols inserted in the second signal stream is smaller than the number of the second protection symbols inserted in the first signal stream, in a specific implementation process, a complementary bit protection symbol may be inserted at the head end of the data sequence of the second signal stream, where the complementary bit may be, for example, 0 or 1, but the embodiment of the present invention does not limit this.
Optionally, if the data processing apparatus is a transmitting device, the data processing apparatus may transmit the first signal stream through a first antenna and transmit the second signal stream through a second antenna, which is not limited in this embodiment of the present invention.
According to the data processing method provided by the embodiment of the invention, a new frame structure is constructed based on the Alamouti coding mode through M first target data symbols which need to be actually sent through a first antenna, M second target data symbols which need to be actually sent through a second antenna and known G first protection symbols, so that after receiving two reconstructed signal streams, a receiving device can perform frequency domain equalization processing on the two signal streams.
The data processing method of the embodiment of the invention can be used as a guard interval by inserting a plurality of guard symbols in front of and behind the target data symbol, and can reduce the multipath interference in the data transmission process.
Fig. 5 shows a schematic flow chart of a method 200 for data processing according to an embodiment of the present invention, where the method 200 is applied in the scenario shown in fig. 1, and may be executed by a data processing apparatus at the receiving device side, and optionally, the data processing apparatus may be a separate device disposed at the signal input end of the receiving antenna, or may be integrated in the sending device as a data processing unit in the sending device, which is not limited in this embodiment of the present invention.
S510, determining a first signal stream transmitted by a first antenna and a second signal stream transmitted by a second antenna, wherein the first signal stream comprises a first data sequence and a third data sequence, the second signal stream comprises a second data sequence and a fourth data sequence,
the first data sequence comprises N first data symbols, the second data sequence comprises N second data symbols, the third data sequence is N data symbols obtained by performing complex conjugate operation and inversion operation on a first second data symbol of the second data sequence and performing complex conjugate operation, inversion operation and inversion operation on the last (N-1) second data symbols of the second data sequence, the fourth data sequence is N data symbols obtained by performing complex conjugate operation and inversion operation on the first data symbol of the first data sequence and performing complex conjugate operation and inversion operation on the last (N-1) first data symbols of the first data sequence, and N is an integer greater than 1.
It should be understood that the first data sequence, the second data sequence, the third data sequence, and the fourth data sequence are obtained by Alamouti encoding, by a transmitting device, M first target data symbols and M second target data symbols, where the first data sequence and the second data sequence may be signal streams transmitted by the transmitting device through two different antennas at a first time, and the third data sequence and the fourth data sequence may be signal streams transmitted by the transmitting device through the two different antennas at a second time.
Specifically, the data processing apparatus receives a third signal stream transmitted by a first antenna and a fourth signal stream transmitted by a second antenna, where the third signal stream and the fourth signal stream may be PPDU frames, the third signal stream includes G second protection symbols, the first data sequence, and the third data sequence, and the fourth signal stream includes (G-1) fourth protection symbols, the second data sequence, and the fourth data sequence. The data processing device obtains the first signal stream by deleting the G second protection symbols in the third signal stream; and deleting the (G-1) fourth protection symbols and the complementary protection symbols in the fourth signal stream to obtain the second signal stream, which is not limited in the embodiment of the present invention.
S520, performing frequency domain equalization on the first signal stream and the second signal stream to obtain a frequency domain response of the first data sequence and a frequency domain response of the second data sequence.
In particular, the data processing apparatus may perform a discrete fourier transform on the first signal stream and the second signal stream to obtain a frequency domain response of the first signal stream and a frequency domain response of the second signal stream; and obtaining the frequency domain response of the first data sequence and the frequency domain response of the second data sequence according to the frequency domain response of the first signal stream, the conjugate of the frequency domain response of the second signal stream, the frequency domain response of the channel from the first transmitting antenna to the receiving antenna and the frequency domain response of the channel from the second transmitting antenna to the receiving antenna.
Optionally, due to
Figure GDA0002361940940000151
The data processing apparatus may be according to equation (10):
Figure GDA0002361940940000152
equation (11) is derived such that the frequency domain response of the first data sequence and the frequency domain response of the second data sequence can be determined according to equation (11):
Figure GDA0002361940940000153
wherein z is11,f(n) represents the frequency domain response of the first data sequence, z21,f(n) denotes the frequency domain response of the second data sequence, r1,f(n) represents the frequency domain response of the first received signal stream, r2,f(n) denotes the conjugate of the frequency domain response of the received second signal stream, h11,f(n) represents the frequency domain response of the channel from the first transmit antenna to the first receive antenna, h12,f(n) frequency domain response of the channel from the second transmit antenna to the first receive antenna [ ·]HRepresents the transposed conjugate of the matrix, h12,f(n) denotes the conjugate of the frequency domain response of the channel from the second transmit antenna to the first receive antenna, h11,f(n) represents the conjugate of the frequency domain response of the channel from the first transmit antenna to the first receive antenna.
S530, determining M first target data symbols and M second target data symbols according to the frequency domain response of the first data sequence and the frequency domain response of the second data sequence, where M is an integer greater than 1.
Specifically, the data processing apparatus may perform inverse discrete fourier transform on the frequency domain response of the first data sequence, resulting in the first data sequence; deleting the first G first protection symbols inserted in the first data sequence and the last G second protection symbols inserted in the first data sequence to obtain M first target data symbols; performing inverse discrete Fourier transform on the frequency domain response of the second data sequence to obtain the second data sequence; deleting the first (G +1) third protection symbols inserted in the second data sequence and the last (G-1) fourth protection symbols inserted in the second data sequence to obtain the M second target data symbols.
Optionally, before S510, the data processing apparatus may receive a third signal stream transmitted by the first antenna and a fourth signal stream transmitted by the second antenna, where the third signal stream includes the G second guard symbols, the first data sequence and the third data sequence, and the fourth signal stream includes the (G-1) fourth guard symbols, the second data sequence and the fourth data sequence; the determining a first signal stream transmitted by a first antenna and a second signal stream transmitted by a second antenna comprises: deleting the G guard symbols in the third signal stream to obtain the first signal stream; deleting the (G-1) guard symbols in the fourth signal stream to obtain the second signal stream.
Fig. 6 shows a schematic block diagram of a data block based on Alamouti coding according to an embodiment of the present invention. As shown in fig. 6, the data block may be a data block in a data field of a PPDU frame, the signal stream 1 and the signal stream 2 may be, for example, signal streams transmitted by a transmitting device (for example, may be an AP110) through an antenna 1 and an antenna 2 as shown in fig. 1, and the signal stream 1 and the signal stream 2 may also be signal streams received by a receiving device (for example, may be an STA121 or an STA122) through the antenna 1 as shown in fig. 2, which is not limited in this embodiment of the present invention.
As an alternative embodiment, the encoding process of the data block at the transmitting device as shown in fig. 6 is as follows:
step a), determining at a first time t1Data to be transmitted x (n) and y (n).
It is to be understood that x (N) is a sequence of N data symbols to be transmitted, having a value of (x)1，x2，…，xN-1，xN) Y (N) is a sequence of N data symbols to be transmitted, having a value of (y)1，y2，…，yN-1，yN)。
Step b), inserting G protection symbols (G) in front of x (n)1，g2，…，gG) G protection symbols are inserted at the back
Figure GDA0002361940940000161
The data sequence z is obtained by the constructed guard interval (GI 1 for short)11(n)。
It should be understood that the G protection symbols may be a protection interval, and the protection interval may be composed of G pieces of 1 or-1 obtained through training in advance, for example, but the embodiment of the present invention does not limit this.
Step c), inserting G +1 protection symbols (G) in front of y (n)1，gG，gG-1，…，g2，g1) Behind which G-1 guard symbols are inserted
Figure GDA0002361940940000162
The constructed guard interval GI 2, the data sequence z21(n)。
Step d), determining at a second time t2Data x to be transmitted*(-n) and-y*(-n)。
Step e) at-y*G guard symbols inserted in front of (-n)
Figure GDA0002361940940000163
G protective symbols inserted at the back
Figure GDA0002361940940000164
The constructed guard interval GI 1 is used to obtain the data sequence z12(n)。
Step f) at x*G +1 guard symbols inserted in front of (-n)
Figure GDA0002361940940000165
G-1 protection symbols inserted at the back
Figure GDA0002361940940000166
The constructed guard interval GI 2, the data sequence z22(n)。
It is understood that x (-n) is the reverse order of x (n) ((x))N，xN-1，…，x2，x1) (ii) a y (-n) is the reverse of y (n)N，yN-1，…，y2，y1) (ii) a G guard intervals consisting of known guard symbols, G each1，g2，…，gG。
Step g) in z11(n) and z12G protection symbols are inserted in front of the data sequence composed of (n)
Figure GDA0002361940940000171
The guard interval GI 1 thus formed results in a signal stream 1.
Step h) at z21(n) and z22(n) inserting G-1 protection symbols in front of the data sequence
Figure GDA0002361940940000172
The guard interval GI 2 thus formed results in a signal stream 2.
It should be understood that the steps of the embodiment of the present invention do not have the encoding process for signal stream 1 and signal stream 2 in a sequential order.
Step i) at a first time t1Transmitting the data sequence z in the signal stream 1 via the first antenna11(n) simultaneously transmitting the data sequence z in the signal stream 2 via the second antenna21(n)。
Step j) at a second time t2Transmitting the data sequence z in the signal stream 1 via the first antenna12(n) simultaneously transmitting the data sequence z in the signal stream 2 via the second antenna22(n)。
Alternatively, since the number of guard symbols of the guard interval GI 1 inserted before the signal stream 1 is one more than the number of guard symbols of the guard interval GI 2 inserted before the signal stream 2, the guard interval GI 2 may be supplemented by inserting a complementary guard symbol before the guard interval GI 2, where the complementary guard symbol may be, for example, 0 or 1, which is not limited in this embodiment of the present invention.
As shown in FIG. 6, z22The data sequence of (n) is z11(n) the conjugate of the first data symbol plus the pair z11(n) a data sequence in which the remaining data symbols have been subjected to conjugation, reverse order and inversion operations, z12The data sequence of (n) is pairz21(n) adding z to the data resulting from the conjugation and negation of the first data symbol21And (n) performing conjugation, reverse order and inversion operations on the residual data symbols in the step (n), wherein the data symbols conform to the relationship from the formula (6) to the formula (9).
The data block 1 of the first signal stream includes a guard interval GI 1, the data block 2 also includes a guard interval GI 1, and the guard interval GI 1 is inserted before the first data block and the second data block.
The data block 2 of the second signal stream includes an interval GI 2, the data block 2 also includes a guard interval GI 2, and the guard interval GI 2 is inserted before the first data block and the second data block.
As another alternative embodiment, the process of frequency domain equalization of the data block at the receiving device as shown in fig. 6 is as follows:
step A), after receiving data in signal stream 1 and signal stream 2, deleting G guard intervals GI 1 located in front of signal stream 1, and complementary guard symbols and (G-1) guard intervals GI 2 located in front of signal stream 2 to obtain data sequence r sent by signal stream 11(n) and the data sequence r transmitted by stream 22(n)。
Step B), respectively aligning r1(n) and r2The conjugate of (n) is subjected to DFT conversion to obtain r1f(n) and r2f(n)。
Wherein
Figure GDA0002361940940000181
Step C), the received r is processed by the formula (11)1(n) and r2(n) frequency domain equalization to obtain z11,f(n) and z21,f(n)。
Step D), for z11,f(n) and z21,f(n) performing inverse discrete Fourier transform to obtain a time-domain guard symbol z11(n) and z21(n)。
It should be understood that the steps of the embodiment of the present invention do not have to process signal stream 1 and signal stream 2 in a sequential order.
The method for video quality assessment according to the embodiment of the present invention is described in detail above with reference to fig. 1 to 6, and the apparatus for video quality assessment and the headend device according to the embodiment of the present invention are described in detail below with reference to fig. 7 to 10.
Fig. 7 shows a data processing apparatus 700 provided in an embodiment of the present invention, where the apparatus 700 includes:
a determining unit 710, configured to determine a first data sequence and a second data sequence, where the first data sequence includes N first data symbols, the second data sequence includes N second data symbols, and N is an integer greater than 1;
a processing unit 720, configured to perform complex conjugate operation and negation operation on the first second data symbol of the second data sequence determined by the determining unit, and perform complex conjugate operation, inverse operation, and negation operation on the last (N-1) second data symbols of the second data sequence, so as to obtain a third data sequence; performing complex conjugate operation on a first data symbol of the first data sequence, and performing complex conjugate operation and reverse operation on the last (N-1) first data symbols of the first data sequence to obtain a fourth data sequence;
the processing unit 720 is further configured to determine a first signal stream to be transmitted according to the first data sequence and the third data sequence, and determine a second signal stream to be transmitted according to the second data sequence and the fourth data sequence.
Optionally, the determining unit is specifically configured to: acquiring input M first target data symbols, M second target data symbols and G first protection symbols; determining the first data sequence and the second data sequence according to the M first target data symbols, the M second target data symbols and the G first guard symbols.
Optionally, the determining unit is specifically configured to: performing complex conjugate operation and negation operation on the G first protection symbols to obtain G second protection symbols; the G first guard symbols are inserted before the M first target data symbols, and the G second guard symbols are inserted after the M first target data symbols, resulting in the first data sequence.
Optionally, the determining unit is specifically configured to: inserting G protection symbols obtained by performing complex conjugate operation, reverse operation and inversion operation on the G second protection symbols after a first protection symbol in the G first protection symbols to obtain (G +1) third protection symbols; performing complex conjugate operation and reverse order operation on the last (G-1) first protection symbols of the G first protection symbols to obtain (G-1) fourth protection symbols; the (G +1) third guard symbols are inserted before the M second target data symbols, and the (G-1) fourth guard symbols are inserted after the M second target data symbols, resulting in the second data sequence.
Optionally, the processing unit is specifically configured to: inserting (G-1) protection symbols obtained by performing complex conjugate operation, reverse operation and inversion operation on the (G-1) fourth protection symbols after the protection symbols obtained by performing complex conjugate operation and inversion operation on the first third protection symbol in the (G +1) third protection symbols to obtain G fifth protection symbols; performing complex conjugate operation, reverse operation and inversion operation on the M second target data symbols to obtain M third target data symbols; inserting the G fifth guard symbols before the M third target data symbols, and inserting the G second guard symbols after the M third target data symbols to obtain the third data sequence.
Optionally, the processing unit is specifically configured to: inserting G protection symbols obtained by performing complex conjugate operation and reverse order operation on the G second protection symbols after the protection symbol obtained by performing complex conjugate operation on the first protection symbol in the G first protection symbols to obtain (G +1) sixth protection symbols; performing complex conjugate operation and reverse operation on the M first target data symbols to obtain M fourth target data symbols; the (G +1) sixth guard symbols are inserted before the M fourth target data symbols, and the (G-1) fourth guard symbols are inserted after the M fourth target data symbols, resulting in the fourth data sequence.
Optionally, the processing unit is specifically configured to: inserting the G second guard symbols before the first data sequence; determining the first signal stream according to the G second guard symbols, the first data sequence and the third data sequence; inserting the (G-1) fourth guard symbols before the second data sequence; determining the second signal stream according to the (G-1) fourth guard symbols, the second data sequence and the fourth data sequence.
Optionally, the apparatus further comprises: a transmitting unit for transmitting the first signal stream and the second signal stream through different antennas.
It should be appreciated that the apparatus 700 herein is embodied in the form of a functional unit. The term unit herein may refer to an application-specific integrated circuit (ASIC), an electronic circuit, a processor (e.g., a shared, dedicated, or group processor) and memory that execute one or more software or firmware programs, a combinational logic circuit, and/or other suitable components that support the described functionality. In an optional example, it may be understood by those skilled in the art that the apparatus 700 may be embodied as a data processing apparatus on the sending device side in the foregoing embodiment, and the apparatus 700 may be configured to execute each procedure and/or step corresponding to the data processing apparatus on the sending device side in the foregoing method embodiment, and is not described herein again to avoid repetition.
Fig. 8 shows a data processing apparatus 800 according to an embodiment of the present invention, where the apparatus 800 includes:
a determining unit 810, configured to determine a first signal stream transmitted by a first antenna and a second signal stream transmitted by a second antenna, where the first signal stream includes a first data sequence and a third data sequence, the second signal stream includes a second data sequence and a fourth data sequence, where the first data sequence includes N first data symbols, the second data sequence includes N second data symbols, the third data sequence is N data symbols obtained by performing a complex conjugate operation and an inversion operation on a first second data symbol of the second data sequence, and performing a complex conjugate operation, an inversion operation and an inversion operation on a last (N-1) second data symbols of the second data sequence, and the fourth data sequence is N data symbols obtained by performing a complex conjugate operation on a first data symbol of the first data sequence, and performing a complex conjugate operation and an inversion operation on a last (N-1) first data symbols of the first data sequence N data symbols of (a), N being an integer greater than 1;
a processing unit 820, configured to perform frequency domain equalization on the first signal stream and the second signal stream determined by the determining unit to obtain a frequency domain response of the first data sequence and a frequency domain response of the second data sequence;
the processing unit 820 is further configured to determine M first target data symbols and M second target data symbols according to the frequency domain response of the first data sequence and the frequency domain response of the second data sequence obtained by the processing unit, where M is an integer greater than 1.
Optionally, the processing unit is specifically configured to: performing a discrete fourier transform on the first signal stream and the second signal stream to obtain a frequency domain response of the first signal stream and a frequency domain response of the second signal stream; and obtaining the frequency domain response of the first data sequence and the frequency domain response of the second data sequence according to the frequency domain response of the first signal stream, the conjugate of the frequency domain response of the second signal stream, the frequency domain response of the channel from the first transmitting antenna to the receiving antenna and the frequency domain response of the channel from the second transmitting antenna to the receiving antenna.
Optionally, the processing unit is specifically configured to: the frequency domain response of the first data sequence and the frequency domain response of the second data sequence are determined according to equation (11) above.
Optionally, the processing unit is specifically configured to: performing inverse discrete Fourier transform on the frequency domain response of the first data sequence to obtain the first data sequence; deleting the first G first protection symbols inserted in the first data sequence and the last G second protection symbols inserted in the first data sequence to obtain M first target data symbols; performing inverse discrete Fourier transform on the frequency domain response of the second data sequence to obtain the second data sequence; deleting the first (G +1) third protection symbols inserted in the second data sequence and the last (G-1) fourth protection symbols inserted in the second data sequence to obtain the M second target data symbols.
Optionally, the apparatus further includes a receiving unit, configured to receive a third signal stream transmitted by the first antenna and a fourth signal stream transmitted by the second antenna before the determining of the first signal stream transmitted by the first antenna and the second signal stream transmitted by the second antenna, where the third signal stream includes the G second guard symbols, the first data sequence, and the third data sequence, and the fourth signal stream includes the (G-1) fourth guard symbols, the second data sequence, and the fourth data sequence; the determining unit is specifically configured to: deleting the G second guard symbols in the third signal stream to obtain the first signal stream; deleting the (G-1) fourth guard symbols in the fourth signal stream to obtain the second signal stream.
It should be appreciated that the apparatus 800 herein is embodied in the form of a functional unit. The term unit herein may refer to an application-specific integrated circuit (ASIC), an electronic circuit, a processor (e.g., a shared, dedicated, or group processor) and memory that execute one or more software or firmware programs, a combinational logic circuit, and/or other suitable components that support the described functionality. In an optional example, it may be understood by those skilled in the art that the apparatus 800 may be specifically a data processing apparatus on the receiving device side in the foregoing embodiment, and the apparatus 800 may be configured to execute each procedure and/or step corresponding to the data processing apparatus on the receiving device side in the foregoing method embodiment, and details are not described here again to avoid repetition.
Fig. 9 shows an apparatus 900 for data processing according to an embodiment of the present invention, where the apparatus 900 includes: a processor 910, a transmitter 920, a receiver 930, a memory 940, and a bus system 950. Wherein, the processor 910, the transmitter 920, the receiver 930 and the memory 940 are connected by a bus system 950, the memory 940 is used for storing instructions, and the processor 910 is used for executing the instructions stored in the memory 940 to control the transmitter 920 to transmit signals. The transmitter 920 and the receiver 930 may be communication interfaces, and particularly, the transmitter 920 may be an interface for receiving data and/or instructions, and the receiver 930 may be an interface for transmitting data and/or instructions, and specific forms of the transmitter 920 and the receiver 930 will not be illustrated herein.
It should be understood that the apparatus 900 may be embodied as the data processing apparatus on the transmitting device side in the foregoing embodiments, and may be configured to execute each step and/or flow corresponding to the data processing apparatus on the transmitting device side in the foregoing method embodiments. Alternatively, the memory 940 may include a read-only memory and a random access memory, and provide instructions and data to the processor. The portion of memory may also include non-volatile random access memory. For example, the memory may also store device type information. The processor 910 may be configured to execute the instructions stored in the memory, and when the processor executes the instructions, the processor may perform the steps corresponding to the video quality assessment apparatus in the above method embodiments.
It should be understood that, in the embodiment of the present invention, the processor may be a Central Processing Unit (CPU), and the processor may also be other general-purpose processors, Digital Signal Processors (DSP), Application Specific Integrated Circuits (ASIC), Field Programmable Gate Arrays (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, and the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
Fig. 10 shows an apparatus 1000 for data processing according to an embodiment of the present invention, the apparatus 1000 comprising: a processor 1010, a transmitter 1020, a receiver 1030, a memory 1040, and a bus system 1050. The processor 1010, the transmitter 1020, the receiver 1030, and the memory 1040 are coupled by a bus system 1050, the memory 1040 is used for storing instructions, and the processor 1010 is used for executing the instructions stored in the memory 1040 to control the transmitter 1020 to transmit signals. The transmitter 1020 and the receiver 1030 may be communication interfaces, and particularly, the transmitter 1020 may be an interface for receiving data and/or instructions, and the receiver 1030 may be an interface for transmitting data and/or instructions, and specific forms of the transmitter 1020 and the receiver 1030 will not be illustrated.
It should be understood that the apparatus 1000 may be used for executing various steps and/or flows corresponding to the data processing apparatus on the receiving device side in the above method embodiments. Alternatively, the memory 1040 may include both read-only memory and random access memory, and provides instructions and data to the processor. The portion of memory may also include non-volatile random access memory. For example, the memory may also store device type information. The processor 1010 may be configured to execute instructions stored in the memory, and when the processor executes the instructions, the processor may perform the steps corresponding to the head-end device in the above-described method embodiments.
It is to be understood that in embodiments of the present invention, the processor may be a central processing unit CPU, but may also be other general purpose processors, digital signal processors DSP, application specific integrated circuits ASIC, off-the-shelf programmable gate arrays FPGA or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
In implementation, the steps of the above method may be performed by integrated logic circuits of hardware in a processor or instructions in the form of software. The steps of a method disclosed in connection with the embodiments of the present invention may be directly implemented by a hardware processor, or may be implemented by a combination of hardware and software modules in the processor. The software module may be located in ram, flash memory, rom, prom, or eprom, registers, etc. storage media as is well known in the art. The storage medium is located in a memory, and a processor executes instructions in the memory, in combination with hardware thereof, to perform the steps of the above-described method. To avoid repetition, it is not described in detail here.
Those of ordinary skill in the art will appreciate that the various method steps and elements described in connection with the embodiments disclosed herein can be implemented as electronic hardware, computer software, or combinations of both, and that the steps and elements of the various embodiments have been described above generally in terms of their functionality in order to clearly illustrate the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may also be an electric, mechanical or other form of connection.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment of the present invention.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention essentially or partially contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a read-only memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.
While the invention has been described with reference to specific embodiments, the invention is not limited thereto, and various equivalent modifications and substitutions can be easily made by those skilled in the art within the technical scope of the invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims (20)

1. A method of data processing, comprising:
determining a first data sequence and a second data sequence, wherein the first data sequence comprises N first data symbols, the second data sequence comprises N second data symbols, and N is an integer greater than 1;
performing complex conjugate operation and negation operation on a first second data symbol of the second data sequence, and performing complex conjugate operation, reverse order operation and negation operation on the last (N-1) second data symbols of the second data sequence to obtain a third data sequence;
performing complex conjugate operation on a first data symbol of the first data sequence, and performing complex conjugate operation and reverse operation on the last (N-1) first data symbols of the first data sequence to obtain a fourth data sequence;
determining a first signal stream to be transmitted according to the first data sequence and the third data sequence, and determining a second signal stream to be transmitted according to the second data sequence and the fourth data sequence;
the determining the first data sequence and the second data sequence includes:
acquiring input M first target data symbols, M second target data symbols and G first protection symbols;
determining the first data sequence and the second data sequence according to the M first target data symbols, the M second target data symbols and the G first guard symbols;
determining the first data sequence according to the M first target data symbols, the M second target data symbols, and the G first guard symbols includes:
performing complex conjugate operation and negation operation on the G first protection symbols to obtain G second protection symbols;
inserting the G first guard symbols before the M first target data symbols, and inserting the G second guard symbols after the M first target data symbols, to obtain the first data sequence.
2. The method of claim 1, wherein determining the second data sequence based on the M first target data symbols, the M second target data symbols, and the G first guard symbols comprises:
inserting G protection symbols obtained by performing complex conjugate operation, reverse operation and inversion operation on the G second protection symbols after a first protection symbol in the G first protection symbols to obtain (G +1) third protection symbols;
performing complex conjugate operation and reverse order operation on the last (G-1) first protection symbols of the G first protection symbols to obtain (G-1) fourth protection symbols;
inserting the (G +1) third guard symbols before the M second target data symbols and inserting the (G-1) fourth guard symbols after the M second target data symbols, resulting in the second data sequence.
3. The method of claim 2, wherein performing the complex conjugate operation and the inverse operation on the first second data symbol of the second data sequence and performing the complex conjugate operation, the inverse operation and the inverse operation on the last (N-1) second data symbols of the second data sequence to obtain a third data sequence comprises:
inserting (G-1) protection symbols obtained by performing complex conjugate operation, reverse operation and inversion operation on the (G-1) fourth protection symbols after a protection symbol obtained by performing complex conjugate operation and inversion operation on a first third protection symbol in the (G +1) third protection symbols to obtain G fifth protection symbols;
performing complex conjugate operation, reverse operation and inversion operation on the M second target data symbols to obtain M third target data symbols;
and inserting the G fifth protection symbols before the M third target data symbols, and inserting the G second protection symbols after the M third target data symbols to obtain the third data sequence.
4. The method according to any one of claims 1 to 3, wherein the performing a complex conjugate operation on a first data symbol of the first data sequence and performing a complex conjugate operation and a reverse order operation on a last (N-1) first data symbols of the first data sequence to obtain a fourth data sequence comprises:
inserting G protection symbols obtained by performing complex conjugate operation and reverse order operation on the G second protection symbols after a protection symbol obtained by performing complex conjugate operation on a first protection symbol in the G first protection symbols to obtain (G +1) sixth protection symbols;
performing complex conjugate operation and reverse operation on the M first target data symbols to obtain M fourth target data symbols;
inserting the (G +1) sixth guard symbols before the M fourth target data symbols and inserting the (G-1) fourth guard symbols after the M fourth target data symbols, resulting in the fourth data sequence.
5. The method of claim 4, wherein determining a first signal stream to be transmitted according to the first data sequence and the third data sequence, and determining a second signal stream to be transmitted according to the second data sequence and the fourth data sequence comprises:
inserting the G second guard symbols before the first data sequence;
determining the first signal stream according to the G second protection symbols, the first data sequence and the third data sequence;
inserting the (G-1) fourth guard symbols before the second data sequence;
determining the second signal stream according to the (G-1) fourth guard symbols, the second data sequence and the fourth data sequence.
6. The method according to any one of claims 1 to 3, further comprising:
transmitting the first signal stream and the second signal stream through different antennas.
7. A method of data processing, comprising:
determining a first signal stream transmitted by a first antenna and a second signal stream transmitted by a second antenna, the first signal stream comprising a first data sequence and a third data sequence, the second signal stream comprising a second data sequence and a fourth data sequence,
the first data sequence comprises N first data symbols, the second data sequence comprises N second data symbols, the third data sequence is N data symbols obtained by performing complex conjugate operation and inversion operation on a first second data symbol of the second data sequence and performing complex conjugate operation, inversion operation and inversion operation on last (N-1) second data symbols of the second data sequence, the fourth data sequence is N data symbols obtained by performing complex conjugate operation and inversion operation on last (N-1) first data symbols of the first data sequence, and N is an integer greater than 1;
performing frequency domain equalization on the first signal stream and the second signal stream to obtain a frequency domain response of the first data sequence and a frequency domain response of the second data sequence;
determining M first target data symbols and M second target data symbols according to the frequency domain response of the first data sequence and the frequency domain response of the second data sequence, wherein M is an integer greater than 1;
determining M first target data symbols and M second target data symbols according to the frequency domain response of the first data sequence and the frequency domain response of the second data sequence, including:
performing inverse discrete Fourier transform on the frequency domain response of the first data sequence to obtain the first data sequence;
deleting the first G first protection symbols inserted in the first data sequence and the last G second protection symbols inserted in the first data sequence to obtain the M first target data symbols;
performing inverse discrete Fourier transform on the frequency domain response of the second data sequence to obtain the second data sequence;
deleting the first (G +1) third protection symbols inserted in the second data sequence and the last (G-1) fourth protection symbols inserted in the second data sequence to obtain the M second target data symbols.
8. The method of claim 7, wherein the frequency-domain equalizing the first signal stream and the second signal stream to obtain a frequency-domain response of the first data sequence and a frequency-domain response of the second data sequence, comprises:
performing a discrete fourier transform on the first signal stream and the second signal stream to obtain a frequency domain response of the first signal stream and a frequency domain response of the second signal stream;
and obtaining the frequency domain response of the first data sequence and the frequency domain response of the second data sequence according to the frequency domain response of the first signal stream, the conjugate of the frequency domain response of the second signal stream, the frequency domain response of the channel from the first antenna to the receiving antenna and the frequency domain response of the channel from the second antenna to the receiving antenna.
9. The method of claim 7, wherein the frequency-domain equalizing the first signal stream and the second signal stream to obtain a frequency-domain response of the first data sequence and a frequency-domain response of the second data sequence, comprises:
determining a frequency domain response of the first data sequence and a frequency domain response of the second data sequence according to the following formula:
Figure FDA0002361940930000041
wherein z is11,f(n) represents the frequency domain response of the first data sequence, z21,f(n) represents the frequency domain response of the second data sequence, r1,f(n) represents the frequency domain response of the received first signal stream, r2,f(n) represents the conjugate of the frequency domain response of the received second signal stream, h11,f(n) represents the frequency domain response of the channel from the first antenna to the first receive antenna, h12,f(n) frequency domain representing the channel from the second antenna to the first receive antennaIn response, h12,f(n) denotes the conjugate of the frequency domain response of the channel from the second antenna to the first receive antenna, h11,f(n) represents the conjugate of the frequency domain response of the channel from the first antenna to the first receive antenna.
10. The method of any of claims 7-9, wherein prior to said determining the first signal stream transmitted by the first antenna and the second signal stream transmitted by the second antenna, the method further comprises:
receiving a third signal stream transmitted by the first antenna and a fourth signal stream transmitted by the second antenna, wherein the third signal stream includes G second guard symbols, the first data sequence and the third data sequence, and the fourth signal stream includes (G-1) fourth guard symbols, the second data sequence and the fourth data sequence;
the determining a first signal stream transmitted by a first antenna and a second signal stream transmitted by a second antenna comprises:
deleting the G second protection symbols in the third signal stream to obtain the first signal stream;
deleting the (G-1) fourth protection symbols in the fourth signal stream to obtain the second signal stream.
11. An apparatus for data processing, comprising:
a determining unit, configured to determine a first data sequence and a second data sequence, where the first data sequence includes N first data symbols, the second data sequence includes N second data symbols, and N is an integer greater than 1;
a processing unit, configured to perform complex conjugate operation and negation operation on a first second data symbol of the second data sequence determined by the determining unit, and perform complex conjugate operation, inverse operation, and negation operation on last (N-1) second data symbols of the second data sequence, so as to obtain a third data sequence; performing complex conjugate operation on a first data symbol of the first data sequence, and performing complex conjugate operation and reverse operation on the last (N-1) first data symbols of the first data sequence to obtain a fourth data sequence;
the processing unit is further configured to determine a first signal stream to be transmitted according to the first data sequence and the third data sequence, and determine a second signal stream to be transmitted according to the second data sequence and the fourth data sequence;
the determining unit is specifically configured to:
acquiring input M first target data symbols, M second target data symbols and G first protection symbols;
determining the first data sequence and the second data sequence according to the M first target data symbols, the M second target data symbols and the G first guard symbols;
the determining unit is specifically configured to:
performing complex conjugate operation and negation operation on the G first protection symbols to obtain G second protection symbols;
inserting the G first guard symbols before the M first target data symbols, and inserting the G second guard symbols after the M first target data symbols, to obtain the first data sequence.
12. The apparatus according to claim 11, wherein the determining unit is specifically configured to:
inserting G protection symbols obtained by performing complex conjugate operation, reverse operation and inversion operation on the G second protection symbols after a first protection symbol in the G first protection symbols to obtain (G +1) third protection symbols;
performing complex conjugate operation and reverse order operation on the last (G-1) first protection symbols of the G first protection symbols to obtain (G-1) fourth protection symbols;
inserting the (G +1) third guard symbols before the M second target data symbols and inserting the (G-1) fourth guard symbols after the M second target data symbols, resulting in the second data sequence.
13. The apparatus according to claim 12, wherein the processing unit is specifically configured to:
inserting (G-1) protection symbols obtained by performing complex conjugate operation, reverse operation and inversion operation on the (G-1) fourth protection symbols after a protection symbol obtained by performing complex conjugate operation and inversion operation on a first third protection symbol in the (G +1) third protection symbols to obtain G fifth protection symbols;
performing complex conjugate operation, reverse operation and inversion operation on the M second target data symbols to obtain M third target data symbols;
and inserting the G fifth protection symbols before the M third target data symbols, and inserting the G second protection symbols after the M third target data symbols to obtain the third data sequence.
14. The apparatus according to any one of claims 11 to 13, wherein the processing unit is specifically configured to:
inserting G protection symbols obtained by performing complex conjugate operation and reverse order operation on the G second protection symbols after a protection symbol obtained by performing complex conjugate operation on a first protection symbol in the G first protection symbols to obtain (G +1) sixth protection symbols;
performing complex conjugate operation and reverse operation on the M first target data symbols to obtain M fourth target data symbols;
inserting the (G +1) sixth guard symbols before the M fourth target data symbols and inserting the (G-1) fourth guard symbols after the M fourth target data symbols, resulting in the fourth data sequence.
15. The apparatus according to claim 14, wherein the processing unit is specifically configured to:
inserting the G second guard symbols before the first data sequence;
determining the first signal stream according to the G second protection symbols, the first data sequence and the third data sequence;
inserting the (G-1) fourth guard symbols before the second data sequence;
determining the second signal stream according to the (G-1) fourth guard symbols, the second data sequence and the fourth data sequence.
16. The apparatus of any one of claims 11 to 13, further comprising: a sending unit for sending the data to the receiving unit,
the transmitting unit is configured to transmit the first signal stream and the second signal stream through different antennas.
17. An apparatus for data processing, comprising:
a determining unit, configured to determine a first signal stream transmitted by a first antenna and a second signal stream transmitted by a second antenna, where the first signal stream includes a first data sequence and a third data sequence, and the second signal stream includes a second data sequence and a fourth data sequence,
the first data sequence comprises N first data symbols, the second data sequence comprises N second data symbols, the third data sequence is N data symbols obtained by performing complex conjugate operation and inversion operation on a first second data symbol of the second data sequence and performing complex conjugate operation, inversion operation and inversion operation on last (N-1) second data symbols of the second data sequence, the fourth data sequence is N data symbols obtained by performing complex conjugate operation and inversion operation on last (N-1) first data symbols of the first data sequence, and N is an integer greater than 1;
a processing unit, configured to perform frequency domain equalization on the first signal stream and the second signal stream determined by the determining unit to obtain a frequency domain response of the first data sequence and a frequency domain response of the second data sequence;
the processing unit is further configured to determine M first target data symbols and M second target data symbols according to the frequency domain response of the first data sequence and the frequency domain response of the second data sequence obtained by the processing unit, where M is an integer greater than 1;
the processing unit is specifically configured to:
performing inverse discrete Fourier transform on the frequency domain response of the first data sequence to obtain the first data sequence;
deleting the first G first protection symbols inserted in the first data sequence and the last G second protection symbols inserted in the first data sequence to obtain the M first target data symbols;
performing inverse discrete Fourier transform on the frequency domain response of the second data sequence to obtain the second data sequence;
deleting the first (G +1) third protection symbols inserted in the second data sequence and the last (G-1) fourth protection symbols inserted in the second data sequence to obtain the M second target data symbols.
18. The apparatus according to claim 17, wherein the processing unit is specifically configured to:
performing a discrete fourier transform on the first signal stream and the second signal stream to obtain a frequency domain response of the first signal stream and a frequency domain response of the second signal stream;
and obtaining the frequency domain response of the first data sequence and the frequency domain response of the second data sequence according to the frequency domain response of the first signal stream, the conjugate of the frequency domain response of the second signal stream, the frequency domain response of the channel from the first antenna to the receiving antenna and the frequency domain response of the channel from the second antenna to the receiving antenna.
19. The apparatus according to claim 17, wherein the processing unit is specifically configured to:
determining a frequency domain response of the first data sequence and a frequency domain response of the second data sequence according to the following formula:
Figure FDA0002361940930000091
wherein z is11,f(n) represents the frequency domain response of the first data sequence, z21,f(n) represents the frequency domain response of the second data sequence, r1,f(n) represents the frequency domain response of the received first signal stream, r2,f(n) represents the conjugate of the frequency domain response of the received second signal stream, h11,f(n) represents the frequency domain response of the channel from the first antenna to the first receive antenna, h12,f(n) represents the frequency domain response of the channel from the second antenna to the first receive antenna, h12,f(n) denotes the conjugate of the frequency domain response of the channel from the second antenna to the first receive antenna, h11,f(n) represents the conjugate of the frequency domain response of the channel from the first antenna to the first receive antenna.
20. The apparatus according to any one of claims 17 to 19, characterized in that the apparatus further comprises a receiving unit,
the receiving unit is configured to receive, before the determining of the first signal stream transmitted by the first antenna and the second signal stream transmitted by the second antenna, a third signal stream transmitted by the first antenna and a fourth signal stream transmitted by the second antenna, where the third signal stream includes G second guard symbols, the first data sequence and the third data sequence, and the fourth signal stream includes (G-1) fourth guard symbols, the second data sequence and the fourth data sequence;
the determining unit is specifically configured to:
deleting the G second protection symbols in the third signal stream to obtain the first signal stream;
deleting the (G-1) fourth protection symbols in the fourth signal stream to obtain the second signal stream.
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1893307A (en) * 2005-06-28 2007-01-10 东南大学 Signal transmitting/receiving apparatus and method of multi-input-output wireless communication system
CN101335551A (en) * 2007-06-28 2008-12-31 上海无线通信研究中心 SINR estimation method based on multi-antenna diversity scheme of DFT-S-GMC system
CN101783722A (en) * 2009-01-21 2010-07-21 普天信息技术研究院有限公司 Transmission method and device for virtual MIMO

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010015127A1 (en) * 2008-08-07 2010-02-11 Huawei Technologies Co., Ltd. Method for transmit diversity encoding
GB2463508B (en) * 2008-09-16 2011-04-13 Toshiba Res Europ Ltd Wireless communications apparatus

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1893307A (en) * 2005-06-28 2007-01-10 东南大学 Signal transmitting/receiving apparatus and method of multi-input-output wireless communication system
CN101335551A (en) * 2007-06-28 2008-12-31 上海无线通信研究中心 SINR estimation method based on multi-antenna diversity scheme of DFT-S-GMC system
CN101783722A (en) * 2009-01-21 2010-07-21 普天信息技术研究院有限公司 Transmission method and device for virtual MIMO

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
《多发射天线STBC-SCFDE系统的性能研究》;叶卓映;《电信科学》;20121231(第12期);第61页，第3.2节 *
叶卓映.《多发射天线STBC-SCFDE系统的性能研究》.《电信科学》.2012,(第12期), *

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