CN107566071A - A kind of decoding method of IRIG B direct currents code coding and decoding device - Google Patents

A kind of decoding method of IRIG B direct currents code coding and decoding device Download PDF

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Publication number
CN107566071A
CN107566071A CN201710908578.0A CN201710908578A CN107566071A CN 107566071 A CN107566071 A CN 107566071A CN 201710908578 A CN201710908578 A CN 201710908578A CN 107566071 A CN107566071 A CN 107566071A
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module
irig
writing
tpsram
reading
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CN107566071B (en
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陈伟
王宇
王世臣
范兴民
陈仿杰
孟宪伟
范晓东
廖芹
赵娟
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Anhui Sun Create Electronic Co Ltd
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Anhui Sun Create Electronic Co Ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0602—Systems characterised by the synchronising information used
    • H04J3/0605—Special codes used as synchronising signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0602—Systems characterised by the synchronising information used
    • H04J3/0614—Systems characterised by the synchronising information used the synchronising signal being characterised by the amplitude, duration or polarity
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0602—Systems characterised by the synchronising information used
    • H04J3/0617—Systems characterised by the synchronising information used the synchronising signal being characterised by the frequency or phase
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
    • H04L7/0012—Synchronisation information channels, e.g. clock distribution lines by comparing receiver clock with transmitter clock

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Logic Circuits (AREA)
  • Electric Clocks (AREA)

Abstract

The invention belongs to the B code time services field of sync identification, more particularly to a kind of decoding method of IRIG B direct currents code coding and decoding device.The present invention includes time receiving module, IRIG B codes output module, IRIG B codes receiving module, time output module, coding/decoding module and constant-temperature crystal oscillator, the signal input part of the coding/decoding module is received respectively from time receiving module, constant-temperature crystal oscillator, the TOD times of IRIG B code receiving modules and pulse per second (PPS), synchronizing frequency, IRIG B direct current codes, and signal output part output IRIG B direct currents code, TOD times and the pulse per second (PPS) of coding/decoding module are respectively to IRIG B codes output module, the signal input part of time output module.The present invention not only realizes the coding of IRIG B direct current codes, modulation is carried out parallel in ARM microprocessor system MSS, FPGA modulating unit respectively, demodulation, decoding are carried out parallel in FPGA demodulating units, ARM microprocessor system MSS respectively, and the present invention is also equipped with the advantages of design is simple, time service precision is high, system is reliable and stable.

Description

A kind of decoding method of IRIG-B direct currents code coding and decoding device
It is " 2016.01.28 " applying date that the application, which is, Application No. " 201610069062.7 ", and invention and created name is The divisional application of " a kind of IRIG-B direct currents code coding and decoding device and its decoding method ".
Technical field
The invention belongs to the B code time services field of sync identification, more particularly to a kind of IRIG-B direct currents code coding and decoding device Decoding method.
Background technology
IRIG-B codes are a kind of serial time format codes, are proposed earliest by instrument group (IRIG) between U.S. target range, and by It is widely used in time synchronized Transmission system.IRIG-B codes have Global Access use, nuclear interface standardizing, suitable for long-distance transmissions etc. Feature, in China, Industry Control, communication, meteorology, space flight, power system measuring and the test equipments in field such as protection use Time synchronizing standard of the IRIG-B international times standard as timing equipment, and formulated corresponding national military standard.
DC codes are IRIG-B direct current codes, and the frame period of DC codes is 1 second, is made up of 100 symbols, each code element 10ms, code First width is divided into tri- kinds of 8ms, 5ms and 2ms, represents symbol " P ", " 1 ", " 0 " respectively.For the ease of transmitting and extracting in B codes Information, have a position identification marking in every 10 symbols, be referred to as P1, P2 ..., P9, P0, frame reference mark is by position Distinguishing mark P0 and adjacent reference symbol Pr compositions, Pr forward position is quasi- moment second of every frame, that is, from the quasi- second From moment, by the second, point, when, the temporal information such as day encoded, ultimately form DC codes.
Mostly using FPGA as core controller, consumed resource is big, synchronous for domestic IRIG-B direct current codes encoding and decoding at present Precision is low, operating efficiency and stability are poor.Therefore, a kind of more efficient coding and decoding device is needed badly to provide effective encoding and decoding hair Method.
The content of the invention
The present invention is in order to overcome the above-mentioned deficiencies of the prior art, there is provided a kind of IRIG-B direct currents code coding and decoding device, this Invention not only realizes the coding of IRIG-B direct current codes, modulated respectively in ARM microprocessor system MSS, FPGA modulating unit Parallel to carry out, demodulation, decoding are carried out parallel in FPGA demodulating units, ARM microprocessor system MSS respectively, and the present invention It is also equipped with the characteristics of time service precision is high, system is reliable and stable.
To achieve the above object, present invention employs following technical measures：
A kind of IRIG-B direct currents code coding and decoding device, including time receiving module, IRIG-B codes output module, IRIG-B codes Receiving module, time output module, coding/decoding module and constant-temperature crystal oscillator, the signal input part of the coding/decoding module receive Respectively from time receiving module, constant-temperature crystal oscillator, the TOD times of IRIG-B code receiving modules and pulse per second (PPS), synchronizing frequency, IRIG-B direct current codes, the signal output part of coding/decoding module export IRIG-B direct currents code, TOD times and pulse per second (PPS) respectively extremely IRIG-B codes output module, the signal input part of time output module.
Preferably, the coding/decoding module includes on-chip system controller, when the on-chip system controller is internally integrated Clock generation module, FPGA modulating units, FPGA demodulating units, ARM microprocessor system MSS；
The clock generation module is received respectively from time receiving module, the pulse per second (PPS) of constant-temperature crystal oscillator, synchronizing frequency, institute State the signal output part connection FPGA modulating units of clock generation module, FPGA demodulating units, ARM microprocessor system MSS Signal input part, the input input pulse per second (PPS) of the FPGA modulating units, the ARM microprocessor system MSS are received and come from The TOD times of time receiving module, ARM microprocessor system MSS are used to encode the TOD times and by the TOD after coding Time, which is sent into FPGA modulating units, to be modulated to obtain synchronous IRIG-B direct current codes, the FPGA modulating units output IRIG-B direct currents code to IRIG-B code output modules signal input part；
The FPGA demodulating units receive the IRIG-B direct current codes from IRIG-B code receiving modules, and FPGA demodulating units are used It is demodulated in IRIG-B direct current codes, and decoded IRIG-B direct currents code is sent into ARM microprocessor system MSS and carried out Decoding, obtains synchronous TOD times and pulse per second (PPS), ARM microprocessor system MSS, the FPGA demodulating unit exports TOD respectively Time, the signal input part of pulse per second (PPS) to time output module.
Preferably, the FPGA modulating units include code stream receiving module, the first RAM module for reading and writing, the 2nd RAM read-write moulds Block and the first Read-write Catrol module；The code stream receiving module receives the TOD after ARM microprocessor system MSS codings Time, the signal output part of the code stream receiving module connect the first Read-write Catrol module, the first RAM module for reading and writing, the 2nd RAM The signal input part of module for reading and writing, the first Read-write Catrol module are used to control the first RAM module for reading and writing and the 2nd RAM read-writes The read-write operation of module, the first RAM module for reading and writing, the output end of the 2nd RAM module for reading and writing are all connected with alternative selector Signal input part, the signal output part of the alternative selector exports IRIG-B direct currents code to IRIG-B code output modules Signal input part；
The FPGA demodulating units include symbol identification module, decoder module, the 3rd RAM module for reading and writing, the 4th RAM read-writes Module, the second Read-write Catrol module and code stream sending module；The symbol identification module receives and comes from IRIG-B code receiving modules IRIG-B direct current codes, signal output part connection decoder module, the signal of the second Read-write Catrol module of symbol identification module be defeated Entering end, the second Read-write Catrol module is used for the read-write operation for controlling the 3rd RAM module for reading and writing and the 4th RAM module for reading and writing, The 3rd RAM module for reading and writing, the output end of the 4th RAM module for reading and writing are all connected with the signal input part of code stream sending module, institute Code stream sending module is stated to be used to be decoded in decoded IRIG-B direct currents code feeding ARM microprocessor system MSS.
Further, Microsemi companies of the on-chip system controller chip model U.S. produce The M2S025T chips of SmartFusion2 series.
The present invention also provides a kind of decoding method of above-mentioned IRIG-B direct currents code coding and decoding device simultaneously, according to IRIG-B direct current code agreements, 1bit will be considered as per 1ms corresponding to the IRIG-B direct currents code, it is high level 1 to have pulsewidth, otherwise for Low level 0, then in IRIG-B direct currents code three kinds of symbols " P ", " 1 " and " 0 " be expressed as 1111111100 with binary data respectively, 1111100000 and 1100000000, then a frame IRIG-B direct currents code is the binary code stream that 100 symbols are 1000bit.
The coding method specific steps include：
S1, ARM microprocessor system MSS receive the TOD times from time receiving module, and during the TOD to receiving Between resolved, obtain the second, point, when, day, the moon, the temporal information in year, and according to IRIG-B direct current code agreements, ARM microprocessor System MSS by the temporal information be converted into symbol " P ", " 1 ", " 0 " form, and enrich obtain a frame IRIG- of 100 symbols B code data, that is, expand to 1000bit time code stream；The time code stream is stored in whole by the ARM microprocessor system MSS In figurate number group；The pulse per second (PPS) of the ARM microprocessor system MSS responses from the time receiving module is interrupted, the second arteries and veins When punching is interrupted, the time code stream in the shaping array is synchronously sent to FPGA modulating units by ARM microprocessor system MSS；
S2, the code stream receiving module receive the time code stream in the shaping array from ARM microprocessor system MSS, And it is synchronously written in the first RAM module for reading and writing and the 2nd RAM module for reading and writing, the first RAM module for reading and writing and the 2nd the RAM read-write Module uses ping-pong operation, and the first Read-write Catrol module controls the 2nd RAM to read while controlling the first RAM module for reading and writing write operations Writing module read operation, RAM read through model read operations, such circulate operation are controlled while controlling the 2nd RAM module for reading and writing write operations；
S3, the response of the clock generation module pulse per second (PPS) and constant-temperature crystal oscillator from the time receiving module when Clock, when clock generation module produces reading of the homologous clock as the first RAM module for reading and writing and the 2nd RAM module for reading and writing Clock, the first RAM module for reading and writing and the 2nd RAM module for reading and writing export 1000bit, obtained in turn by data in EMS memory with 1bit word lengths To the DC waveform of the IRIG-B direct current code synchronous with the pulse per second (PPS).
The coding/decoding method specific steps include：
S1, the symbol identification module receive the IRIG-B direct current codes from IRIG-B code receiving modules, according to IRIG-B Direct current code agreement, symbol " P ", " 1 " and " 0 " is corresponded in automatic identification IRIG-B direct current codes, and use 10bit binary elements respectively It is expressed as 1111111100,1111100000 and 1100000000；Using the clock homologous with the local of symbol identification module come The rising edge and trailing edge of IRIG-B direct current codes are caught, is produced and the homologous rising edge of local clock and trailing edge clock；
S2, the decoder module are known automatically according to caused rising edge, binary element, decoder module in step S1 The frame reference mark of other IRIG-B direct current codes, the frame head of IRIG-B direct current codes is found by the frame reference mark, then when described When rising edge arrives, binary element is exported, the binary data of complete frame IRIG-B direct current codes is obtained, works as decoding When module identifies the frame reference mark, started counting up with the rising edge of the IRIG-B direct current codes of input, when meter completely 99, under The rising edge of one adjacent IRIG-B direct current codes is defined second moment mark, and decoder module is by blaze when frame reference pulse and quasi- second Will is sent into ARM microprocessor system MSS ports, and pulse per second (PPS) is sent to the signal input part of time output module；
S3, the 3rd RAM module for reading and writing and the 4th RAM module for reading and writing use ping-pong operation, the second Read-write Catrol module The 4th RAM module for reading and writing read operations are controlled while controlling the 3rd RAM module for reading and writing write operations, control the 4th RAM module for reading and writing The 3rd RAM module for reading and writing read operations, such circulate operation, the second Read-write Catrol module control stream hair are controlled while write operation Module is sent to send the binary data in the 3rd RAM module for reading and writing or the 4th RAM module for reading and writing internal memories to ARM microprocessor system Unite in MSS bus；
When S4, the ARM microprocessor system MSS response are from frame reference pulse interruption, ARM microprocessor system MSS synchronously reads the binary data in bus, and is decoded, according to IRIG-B direct current code agreements, ARM microprocessor system MSS extract in the binary data second, point, when, day, the moon, year temporal information and be converted into the TOD times of ASCII fromat； When the pulse per second (PPS) of the MSS responses from FPGA demodulating units is interrupted, the ARM microprocessor system MSS is synchronous by the TOD times Send to the signal input part of output module.
The beneficial effects of the present invention are：
1), the present invention includes time receiving module, IRIG-B codes output module, IRIG-B codes receiving module, time output Module, coding/decoding module and constant-temperature crystal oscillator, the signal input part of the coding/decoding module receives receives mould respectively from the time Block, constant-temperature crystal oscillator, the TOD times of IRIG-B code receiving modules and pulse per second (PPS), synchronizing frequency, IRIG-B direct current codes, encoding and decoding mould Signal output part output IRIG-B direct currents code, TOD times and the pulse per second (PPS) of block export to IRIG-B codes output module, time respectively The signal input part of module.The present invention not only realizes the coding of IRIG-B direct current codes, modulation respectively in ARM microprocessor system Carried out parallel in MSS, FPGA modulating unit, demodulate, decode respectively in FPGA demodulating units, ARM microprocessor system MSS simultaneously Row is carried out, and the present invention is also equipped with the advantages of design is simple, time service precision is high, system is reliable and stable.
2), the SmartFusion2 systems of Microsemi companies of on-chip system controller chip model U.S. production The M2S025T chips of row, the on-chip system controller are internally integrated clock generation module, FPGA modulating units, FPGA demodulation Unit, ARM microprocessor system MSS；Possesses the advantages of fast processing speed, low-power consumption, high safety and reliability.
3), using the coding and decoding device and decoding method in the present invention, the precision height of coding and decoding is realized, and is The advantages of speed of service of uniting is fast.
Brief description of the drawings
Fig. 1 is the structural representation of IRIG-B direct currents code coding and decoding device of the present invention；
Fig. 2 is IRIG-B direct current code symbol diagrams；
Fig. 3 is DC signal bit stream oscillograms；
Fig. 4 is the RTL views of the coding/decoding module of the present invention；
Fig. 5 is the RTL views of the FPGA modulating units of the present invention；
Fig. 6 is the RTL views of the FPGA demodulating units of the present invention.
The implication of label symbol is as follows in figure：
10-time, 20-IRIG-B of receiving module code output module
30-IRIG-B code 40-time of receiving module output modules
50-coding/decoding module, 60-constant-temperature crystal oscillator
Clock-clock generation module Reg_wrp-code stream receiving module
The RAM module for reading and writing RAM module for reading and writing of TPSRAM_0-the 2nd of TPSRAM_1-the first
The Read-write Catrols of Out_TPCtrl-first module EleDetect-symbol identification module
Decode-RAM the module for reading and writing of decoder module TPSRAM_3-the 3rd
The RAM module for reading and writing Read-write Catrol modules of RAMCtrl-second of TPSRAM_4-the 4th
RAMapb-code stream sending module
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete Site preparation describes, it is clear that described embodiment is only part of the embodiment of the present invention, rather than whole embodiments.It is based on Embodiment in the present invention, those of ordinary skill in the art are obtained every other under the premise of creative work is not made Embodiment, belong to the scope of protection of the invention.
As shown in figure 1, a kind of IRIG-B direct currents code coding and decoding device, including the output of time receiving module 10, IRIG-B codes Module 20, IRIG-B codes receiving module 30, time output module 40, coding/decoding module 50 and constant-temperature crystal oscillator 60, it is described to compile solution The signal input part of code module 50 is received respectively from time receiving module 10, constant-temperature crystal oscillator 60, IRIG-B codes receiving module 30 The TOD times and pulse per second (PPS), synchronizing frequency, IRIG-B direct current codes, coding/decoding module 50 signal output part output IRIG-B it is straight Code, TOD times and pulse per second (PPS) are flowed respectively to IRIG-B codes output module 20, the signal input part of time output module 40.This hair The bright coding for not only realizing IRIG-B direct current codes, modulation respectively in ARM microprocessor system MSS, FPGA modulating unit simultaneously Row is carried out, and demodulation, decoding are carried out parallel in FPGA demodulating units, ARM microprocessor system MSS respectively, and the present invention is also Possesses the advantages of design is simple, time service precision is high, system is reliable and stable.
As shown in figure 4, the coding/decoding module 50 includes on-chip system controller, collect inside the on-chip system controller Into clock generation module Clock, FPGA modulating unit, FPGA demodulating units, ARM microprocessor system MSS；
The clock generation module Clock receives the pulse per second (PPS), same respectively from time receiving module 10, constant-temperature crystal oscillator 60 Synchronizing frequency, the signal output part connection FPGA modulating units of the clock generation module Clock, FPGA demodulating units, the micro- places of ARM Manage device system MSS signal input part, the input input pulse per second (PPS) of the FPGA modulating units, the ARM microprocessor system Unite MSS receive the TOD times from time receiving module 10, ARM microprocessor system MSS be used for the TOD times are encoded, And the TOD times after coding are sent into FPGA modulating units and are modulated to obtain synchronous IRIG-B direct current codes, the FPGA Modulating unit exports IRIG-B direct currents code to the signal input part of IRIG-B codes output module 20；
The FPGA demodulating units receive the IRIG-B direct current codes from IRIG-B codes receiving module 30, FPGA demodulating units It is sent into ARM microprocessor system MSS for being demodulated IRIG-B direct current codes, and by decoded IRIG-B direct currents code Row decoding, obtains synchronous TOD times and pulse per second (PPS), ARM microprocessor system MSS, the FPGA demodulating unit exports respectively TOD times, the signal input part of pulse per second (PPS) to time output module 40.
As shown in figure 5, the FPGA modulating units include code stream receiving module Reg_wrp, the first RAM module for reading and writing TPSRAM_1, the 2nd RAM module for reading and writing TPSRAM_0 and the first Read-write Catrol module Out_TPCtrl；The code stream receives Module Reg_wrp receives the TOD times after ARM microprocessor system MSS codings, the code stream receiving module Reg_wrp Signal output part connect the first Read-write Catrol module Out_TPCtrl, the first RAM module for reading and writing TPSRAM_1, the 2nd RAM read Writing module TPSRAM_0 signal input part, the first Read-write Catrol module Out_TPCtrl are used to control the first RAM read-writes Module TPSRAM_1 and the 2nd RAM module for reading and writing TPSRAM_0 read-write operation, the first RAM module for reading and writing TPSRAM_1, 2nd RAM module for reading and writing TPSRAM_0 output end is all connected with alternative selector MX2 signal input part, the letter of the MX2 Number output end exports IRIG-B direct currents code to the signal input part of IRIG-B codes output module 20.
As shown in fig. 6, the FPGA demodulating units include symbol identification module EleDetect, decoder module Decode, the Three RAM module for reading and writing TPSRAM_3, the 4th RAM module for reading and writing TPSRAM_4, the second Read-write Catrol module RAMCtrl and code stream hair Send module RAMapb；The symbol identification module EleDetect receives the IRIG-B direct currents from IRIG-B codes receiving module 30 Code, symbol identification module EleDetect signal output part connection decoder module Decode, the second Read-write Catrol module RAMCtrl signal input part, the second Read-write Catrol module RAMCtrl are used to control the 3rd RAM module for reading and writing TPSRAM_ 3 and the 4th RAM module for reading and writing TPSRAM_4 read-write operation, the 3rd RAM module for reading and writing TPSRAM_3, the 4th RAM read-write Module TPSRAM_4 output end is all connected with code stream sending module RAMapb signal input part, the code stream sending module RAMapb, which is used to decoded IRIG-B direct currents code being sent into ARM microprocessor system MSS, to be decoded.
The SmartFusion2 series of Microsemi companies of on-chip system controller chip model U.S. production M2S025T chips；Possesses the advantages of fast processing speed, low-power consumption, high safety and reliability.
As shown in Fig. 2 the frame period of IRIG-B direct current codes is 1 second, it is made up of 100 symbols, each code element 10ms, symbol Width is divided into tri- kinds of 8ms, 5ms and 2ms, represents symbol " P ", " 1 ", " 0 " respectively.For the ease of transmitting and extracting the letter in B codes Breath, have a position identification marking in every 10 symbols, be referred to as P1, P2 ..., P9, P0, frame reference mark is known by position Not Biao Zhi P0 and adjacent reference symbol Pr composition, Pr forward position is quasi- moment second of every frame, that is, from the quasi- second when Carve, by the second, point, when, the temporal information such as day encoded, ultimately form DC codes.
As shown in figure 3, a kind of decoding method of IRIG-B direct currents code coding and decoding device, its core is straight according to IRIG-B Code agreement is flowed, 1bit will be considered as per 1ms corresponding to the IRIG-B direct currents code, it is high level 1 to have pulsewidth, is otherwise low level 0, Then in IRIG-B direct currents code three kinds of symbols " P ", " 1 " and " 0 " be expressed as 1111111100 with binary data respectively, 1111100000 and 1100000000, then a frame IRIG-B direct currents code is the binary code stream that 100 symbols are 1000bit.
Wherein coding method specific steps include：
S1, the ARM microprocessor system MSS receive the TOD from time receiving module 10 by TOD_Input serial ports Time, and the TOD times to receiving resolve, obtain the second, point, when, day, the moon, the temporal information in year, and according to IRIG-B Direct current code agreement, ARM microprocessor system MSS by the temporal information be converted into symbol " P ", " 1 ", " 0 " form, and enrich A frame IRIG-B code data of 100 symbols are obtained, that is, expand to 1000bit time code stream；The ARM microprocessor system Time code stream deposit length is in the shaping array that 16bit sizes are 64 by MSS；The ARM microprocessor system MSS rings Should the pulse per second (PPS) PPS_in from the time receiving module 10 interrupt, when the pulse per second (PPS) PPS_in is interrupted, ARM microprocessor Time code stream in the shaping array is synchronously sent to FPGA modulating units by system MSS；
S2, the code stream receiving module Reg_wrp receive the shaping array from ARM microprocessor system MSS in when Between code stream, and be synchronously written in the first RAM module for reading and writing TPSRAM_1 and the 2nd RAM module for reading and writing TPSRAM_0, described first RAM module for reading and writing TPSRAM_1 and the 2nd RAM module for reading and writing TPSRAM_0 uses ping-pong operation, the first Read-write Catrol module Out_ TPCtrl controls the 2nd RAM module for reading and writing TPSRAM_0 to read behaviour while controlling the first RAM module for reading and writing TPSRAM_1 write operations Make, control RAM read through model TPSRAM_1 read operations while controlling the 2nd RAM module for reading and writing TPSRAM_0 write operations, so follow Ring operates；
Pulse per second (PPS) PPS_in from the time receiving module 10 of S3, the clock generation module Clock response and The 10MHz clock Clk10M_in of constant-temperature crystal oscillator 60, clock generation module Clock produce homologous 1KHz clocks Clk1KHz_out As the first RAM module for reading and writing TPSRAM_1 and the 2nd RAM module for reading and writing TPSRAM_0 reading clock, the first RAM read-writes Module TPSRAM_1 and the 2nd RAM module for reading and writing TPSRAM_0 exports 1000bit in turn by data in EMS memory with 1bit word lengths, Obtain the DC waveform of the IRIG-B direct current code synchronous with the pulse per second (PPS) PPS_in.
The coding/decoding method specific steps include：
S1, the symbol identification module EleDetect receive the IRIG-B direct current codes from IRIG-B codes receiving module 30, According to IRIG-B direct current code agreements, symbol " P ", " 1 " and " 0 " is corresponded in automatic identification IRIG-B direct current codes, and use 10bit respectively Binary element is expressed as 1111111100,1111100000 and 1100000000, i.e. Element_Out [9:0]；Using with code First identification module EleDetect local clock homologous 10KHz clocks Clk_10K catches the rising edge of IRIG-B direct current codes And trailing edge, produce and local clock homologous rising edge Pos_Out and trailing edge clock Neg_Out；
S2, the decoder module Decode are according to caused rising edge Pos_Out, binary element in step S1 Element_In[9:0], the frame reference mark pp_flag of decoder module Decode automatic identifications IRIG-B direct current codes, by described Frame reference mark pp_flag finds the frame head of IRIG-B direct current codes, defeated then when the rising edge Pos_Out arrives Go out binary element Element_In [9:0], the binary data of complete frame IRIG-B direct current codes is obtained, works as decoder module When Decode identifies the frame reference mark pp_flag, started counting up with the rising edge of the IRIG-B direct current codes of input, work as meter When full 99, the rising edge of next adjacent IRIG-B direct current codes is second moment mark PPS_flag that is defined, by frame reference pulse PP_ Out and mark PPS_Out of quasi- moment second are sent into ARM microprocessor system MSS ports, and pulse per second (PPS) was sent to the time and exports mould The signal input part of block 40；
S3, the 3rd RAM module for reading and writing TPSRAM_3 and the 4th RAM module for reading and writing TPSRAM_4 use ping-pong operation, Second Read-write Catrol module RAMCtrl controls the 4th RAM read-writes while controlling the 3rd RAM module for reading and writing TPSRAM_3 write operations Module TPSRAM_4 read operations, the 3rd RAM module for reading and writing is controlled while controlling the 4th RAM module for reading and writing TPSRAM_4 write operations TPSRAM_3 read operations, such circulate operation, the second Read-write Catrol module RAMCtrl control stream sending module RAMapb are by Binary data in three RAM module for reading and writing TPSRAM_3 or the 4th RAM module for reading and writing TPSRAM_4 internal memories is sent to the micro- places of ARM In the bus for managing device system MSS；
When S4, shown ARM microprocessor system MSS response are from frame reference pulse PP_Out interruptions, ARM microprocessors Device system MSS synchronously reads the binary data in bus, and is decoded, according to IRIG-B direct current code agreements, ARM microprocessors Device system MSS extract in the binary data second, point, when, day, the moon, year temporal information and be converted into ASCII fromat The TOD times；It is described when pulse per second (PPS) PPS_Out of the ARM microprocessor system MSS responses from FPGA demodulating units is interrupted ARM microprocessor system MSS synchronously sends the TOD times to the signal input part of output module 40 through TOD_Output serial ports.

Claims (4)

  1. A kind of 1. decoding method of IRIG-B direct currents code coding and decoding device, it is characterised in that：The IRIG-B direct currents code compiles solution Code device includes time receiving module (10), IRIG-B codes output module (20), IRIG-B codes receiving module (30), time output Module (40), coding/decoding module (50) and constant-temperature crystal oscillator (60), the signal input part of the coding/decoding module (50), which receives, to be divided Lai Zi not time receiving module (10), constant-temperature crystal oscillator (60), the TOD times of IRIG-B codes receiving module (30) and pulse per second (PPS), same Synchronizing frequency, IRIG-B direct current codes, signal output part output IRIG-B direct currents code, TOD times and the second arteries and veins of coding/decoding module (50) Punching is respectively to IRIG-B codes output module (20), the signal input part of time output module (40)；
    The coding/decoding module (50) includes on-chip system controller, and the on-chip system controller is internally integrated clock and produces mould Block Clock, FPGA modulating unit, FPGA demodulating units, ARM microprocessor system MSS；
    The clock generation module Clock receives the pulse per second (PPS), same respectively from time receiving module (10), constant-temperature crystal oscillator (60) Synchronizing frequency, the signal output part connection FPGA modulating units of the clock generation module Clock, FPGA demodulating units, the micro- places of ARM Manage device system MSS signal input part, the input input pulse per second (PPS) of the FPGA modulating units, the ARM microprocessor system The MSS that unites receives the TOD times from time receiving module (10), and ARM microprocessor system MSS is used to compile the TOD times The TOD times after coding are simultaneously sent into FPGA modulating units and are modulated to obtain synchronous IRIG-B direct current codes by code, described FPGA modulating units export IRIG-B direct currents code to the signal input part of IRIG-B codes output module (20)；
    The FPGA demodulating units receive the IRIG-B direct current codes from IRIG-B codes receiving module (30), and FPGA demodulating units are used It is demodulated in IRIG-B direct current codes, and decoded IRIG-B direct currents code is sent into ARM microprocessor system MSS and carried out Decoding, obtains synchronous TOD times and pulse per second (PPS), ARM microprocessor system MSS, the FPGA demodulating unit exports TOD respectively Time, the signal input part of pulse per second (PPS) to time output module (40)；
    The FPGA modulating units include code stream receiving module Reg_wrp, the first RAM module for reading and writing TPSRAM_1, the 2nd RAM and read Writing module TPSRAM_0 and the first Read-write Catrol module Out_TPCtrl；The code stream receiving module Reg_wrp is received and come from TOD times after ARM microprocessor system MSS codings, the signal output part connection first of the code stream receiving module Reg_wrp Read-write Catrol module Out_TPCtrl, the first RAM module for reading and writing TPSRAM_1, the 2nd RAM module for reading and writing TPSRAM_0 signal Input, the first Read-write Catrol module Out_TPCtrl are used to control the first RAM module for reading and writing TPSRAM_1 and the 2nd RAM Module for reading and writing TPSRAM_0 read-write operation, the first RAM module for reading and writing TPSRAM_1, the 2nd RAM module for reading and writing TPSRAM_ 0 output end is all connected with alternative selector MX2 signal input part, and the signal output part of the alternative selector MX2 is defeated Go out IRIG-B direct currents code to the signal input part of IRIG-B codes output module (20)；
    The FPGA demodulating units include symbol identification module EleDetect, decoder module Decode, the 3rd RAM module for reading and writing TPSRAM_3, the 4th RAM module for reading and writing TPSRAM_4, the second Read-write Catrol module RAMCtrl and code stream sending module RAMapb； The symbol identification module EleDetect receives the IRIG-B direct current codes from IRIG-B codes receiving module (30), symbol identification Module EleDetect signal output part connection decoder module Decode, the second Read-write Catrol module RAMCtrl signal input End, the second Read-write Catrol module RAMCtrl are used to control the 3rd RAM module for reading and writing TPSRAM_3 and the 4th RAM read-write moulds Block TPSRAM_4 read-write operation, the 3rd RAM module for reading and writing TPSRAM_3, the 4th RAM module for reading and writing TPSRAM_4 it is defeated Go out the signal input part that end is all connected with code stream sending module RAMapb, the code stream sending module RAMapb is used for will be decoded IRIG-B direct currents code is sent into ARM microprocessor system MSS and decoded；
    The decoding method is included according to IRIG-B direct current code agreements, will be considered as corresponding to the IRIG-B direct currents code per 1ms 1bit, it is high level 1 to have pulsewidth, is otherwise low level 0, then three kinds of symbols " P ", " 1 " and " 0 " are used respectively in IRIG-B direct currents code Binary data is expressed as 1111111100,1111100000 and 1100000000, then a frame IRIG-B direct currents code is 100 symbols As 1000bit binary code stream.
  2. 2. a kind of decoding method of IRIG-B direct currents code coding and decoding device as claimed in claim 1, it is characterised in that described Coding method specific steps include：
    S1, ARM microprocessor system MSS receive the TOD times from time receiving module (10), and during the TOD to receiving Between resolved, obtain the second, point, when, day, the moon, the temporal information in year, and according to IRIG-B direct current code agreements, ARM microprocessor System MSS by the temporal information be converted into symbol " P ", " 1 ", " 0 " form, and enrich obtain a frame IRIG- of 100 symbols B code data, that is, expand to 1000bit time code stream；The time code stream is stored in whole by the ARM microprocessor system MSS In figurate number group；The pulse per second (PPS) of the ARM microprocessor system MSS responses from the time receiving module (10) is interrupted, described When pulse per second (PPS) is interrupted, the time code stream in the shaping array is synchronously sent to FPGA modulation lists by ARM microprocessor system MSS Member；
    S2, the code stream receiving module Reg_wrp receive the timing code in the shaping array from ARM microprocessor system MSS Stream, and be synchronously written in the first RAM module for reading and writing TPSRAM_1 and the 2nd RAM module for reading and writing TPSRAM_0, the first RAM is read Writing module TPSRAM_1 and the 2nd RAM module for reading and writing TPSRAM_0 uses ping-pong operation, the first Read-write Catrol module Out_ TPCtrl controls the 2nd RAM module for reading and writing TPSRAM_0 to read behaviour while controlling the first RAM module for reading and writing TPSRAM_1 write operations Make, control RAM read through model TPSRAM_1 read operations while controlling the 2nd RAM module for reading and writing TPSRAM_0 write operations, so follow Ring operates；
    Pulse per second (PPS) and constant-temperature crystal oscillator of S3, the clock generation module Clock response from the time receiving module (10) (60) clock, clock generation module Clock produce homologous clock as the first RAM module for reading and writing TPSRAM_1 and the Two RAM module for reading and writing TPSRAM_0 reading clock, the first RAM module for reading and writing TPSRAM_1 and the 2nd RAM module for reading and writing TPSRAM_ 0, in turn by data in EMS memory with 1bit word lengths, exports 1000bit, obtains the IRIG-B direct current code synchronous with the pulse per second (PPS) DC waveform.
  3. 3. a kind of decoding method of IRIG-B direct currents code coding and decoding device as claimed in claim 1, it is characterised in that described Coding/decoding method specific steps include：
    S1, the symbol identification module EleDetect receive the IRIG-B direct current codes from IRIG-B codes receiving module (30), root According to IRIG-B direct current code agreements, symbol " P ", " 1 " and " 0 " is corresponded in automatic identification IRIG-B direct current codes, and use 10bit bis- respectively System symbol is expressed as 1111111100,1111100000 and 1100000000；Using with symbol identification module EleDetect's Local homologous clock catches the rising edge and trailing edge of IRIG-B direct current codes, when producing the rising edge homologous with local clock Clock and trailing edge clock；
    S2, the decoder module Decode are according to caused rising edge, binary element, decoder module in step S1 The frame reference mark of Decode automatic identification IRIG-B direct current codes, the frame of IRIG-B direct current codes is found by the frame reference mark Head, then when the rising edge arrives, binary element is exported, obtain complete frame IRIG-B direct current codes two enter Data processed, when decoder module Decode identifies the frame reference mark, opened with the rising edge of the IRIG-B direct current codes of input Begin to count, when meter it is full 99 when, the rising edges of next adjacent IRIG-B direct current codes is defined a second moment mark, decoder module Frame reference pulse and mark of quasi- moment second are sent into ARM microprocessor system MSS ports by Decode, and by pulse per second (PPS) send to when Between output module (40) signal input part；
    S3, the 3rd RAM module for reading and writing TPSRAM_3 and the 4th RAM module for reading and writing TPSRAM_4 use ping-pong operation, and second Read-write Catrol module RAMCtrl controls the 4th RAM module for reading and writing while controlling the 3rd RAM module for reading and writing TPSRAM_3 write operations TPSRAM_4 read operations, the 3rd RAM module for reading and writing is controlled while controlling the 4th RAM module for reading and writing TPSRAM_4 write operations TPSRAM_3 read operations, such circulate operation, the second Read-write Catrol module RAMCtrl control stream sending module RAMapb are by Binary data in three RAM module for reading and writing TPSRAM_3 or the 4th RAM module for reading and writing TPSRAM_4 internal memories is sent to the micro- places of ARM In the bus for managing device system MSS；
    When S4, the ARM microprocessor system MSS response are from frame reference pulse interruption, ARM microprocessor system MSS The synchronous binary data read in bus, and decoded, according to IRIG-B direct current code agreements, ARM microprocessor system MSS Extract in the binary data second, point, when, day, the moon, year temporal information and be converted into the TOD times of ASCII fromat；Institute When stating pulse per second (PPS) interruption of the MSS responses from FPGA demodulating units, the ARM microprocessor system MSS synchronously sends out the TOD times Deliver to the signal input part of output module (40).
  4. A kind of 4. decoding method of IRIG-B direct currents code coding and decoding device as claimed in claim 1, it is characterised in that：It is described The M2S025T chips of the SmartFusion2 series of Microsemi companies of on-chip system controller chip model U.S. production.
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