CN107562686B

CN107562686B - information processing method and device

Info

Publication number: CN107562686B
Application number: CN201710717525.0A
Authority: CN
Inventors: 刘雷波; 朱敏; 魏少军
Original assignee: Tsinghua University; Wuxi Research Institute of Applied Technologies of Tsinghua University
Current assignee: Tsinghua University; Wuxi Research Institute of Applied Technologies of Tsinghua University
Priority date: 2017-08-18
Filing date: 2017-08-18
Publication date: 2019-12-10
Anticipated expiration: 2037-08-18
Also published as: CN107562686A

Abstract

The embodiment of the disclosure provides an information processing method and device. The method comprises the following steps: generating a first command frame, wherein the first command frame comprises task information, and the task information is used for instructing the reconfigurable processing system to execute a first task; writing the first command frame into a PCIe command space, wherein the PCIe command space is shared by the first processor system and the reconfigurable processing system; and obtaining a first response frame from the reconfigurable processing system from the PCIe command space, wherein the first response frame comprises return information which is used for indicating the result obtained by the reconfigurable processing system aiming at the first task. By utilizing the embodiment of the disclosure, simple and efficient interaction between the first processor system and the reconfigurable processing system can be realized.

Description

Information processing method and device

Technical Field

The present disclosure relates to an information processing method and an information processing apparatus.

background

with the rapid development of electronic technology, the existing processor architecture (for example, the X86 processor architecture) needs to perform more and more functions and is more and more complex, which poses a great challenge to the performance, load and other aspects of the existing processor architecture. Therefore, it is highly desirable to provide corresponding technical solutions to address such challenges.

Disclosure of Invention

One aspect of the present disclosure provides an information processing method applied to a non-reconfigurable first processor system, the method including: generating a first command frame, wherein the first command frame includes task information, the task information is used for instructing a reconfigurable processing system to execute a first task, the first command frame is written into a peripheral component Interconnect Express (PCIe) command space, the PCIe command space is shared by the first processor system and the reconfigurable processing system, and a first response frame from the reconfigurable processing system is obtained from the PCIe command space, and the first response frame includes return information, and the return information is used for instructing the reconfigurable processing system to obtain a result for the first task.

Another aspect of the present disclosure provides an information processing method applied to a reconfigurable processing system, the method including: the method comprises the steps of obtaining a first command frame from a first processor system from a PCIe command space, wherein the first command frame comprises task information, the task information is used for indicating the reconfigurable processing system to execute a first task, the PCIe command space is shared by the first processor system and the reconfigurable processing system, the first task is executed to obtain return information, the return information is used for indicating a result obtained by the reconfigurable processing system aiming at the first task to generate a first response frame, the first response frame comprises the return information, and the first response frame is written into the PCIe command space.

Another aspect of the present disclosure provides an information processing apparatus applied to a non-reconfigurable first processor system, where the system includes a first generating module, a first writing module, and a first obtaining module. The first generating module generates a first command frame, wherein the first command frame comprises task information, and the task information is used for instructing the reconfigurable processing system to execute a first task. The first write module writes the first command frame into a PCIe command space, the PCIe command space being shared by the first processor system and the reconfigurable processing system. The first obtaining module obtains a first response frame from the reconfigurable processing system from the PCIe command space, wherein the first response frame comprises return information, and the return information is used for indicating a result obtained by the reconfigurable processing system for the first task.

another aspect of the present disclosure provides an information processing apparatus applied to a reconfigurable processing system, the system including: the device comprises a third acquisition module, an execution module, a third generation module and a third writing module. The third obtaining module obtains a first command frame from a first processor system from a PCIe command space, wherein the first command frame comprises task information, the task information is used for indicating the reconfigurable processing system to execute a first task, and the PCIe command space is shared by the first processor system and the reconfigurable processing system. And the execution module executes the first task to obtain return information, wherein the return information is used for indicating a result obtained by the reconfigurable processing system aiming at the first task. A third generation module generates a first reply frame, the first reply frame including the return information. The third write module writes the first reply frame into the PCIe command space.

Another aspect of the present disclosure provides an information processing apparatus applied to a first processor system, the system including: one or more processing units; storage means for storing one or more programs which, when executed by the one or more processing units, cause the one or more processing units to carry out the method as described above.

Another aspect of the present disclosure provides an information processing apparatus applied to a reconfigurable processing system, the system including: one or more processing units; storage means for storing one or more programs which, when executed by the one or more processing units, cause the one or more processing units to carry out the method as described above.

Another aspect of the present disclosure provides a computer-readable medium having stored thereon executable instructions that, when executed, implement the method as described above.

another aspect of the disclosure provides a computer program comprising computer executable instructions for implementing the method as described above when executed.

therefore, in the technical scheme of the embodiment of the disclosure, by using PCIe as a medium, simple and fast interaction between the non-reconfigurable first processor system and the reconfigurable processing system can be realized, so that the first processor system can call the reconfigurable processing system through PCIe to execute various functions, thereby greatly enhancing processing performance and processing flexibility.

Drawings

For a more complete understanding of the present disclosure and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

Fig. 1 schematically shows a schematic diagram of an application scenario according to an embodiment of the present disclosure;

FIG. 2 schematically shows a flow chart of an information processing method according to an embodiment of the present disclosure;

FIG. 3 schematically illustrates a flow diagram for establishing a mapping relationship between a first address space and a virtual address space at a reconfigurable processing system according to an embodiment of the disclosure;

fig. 4 schematically shows a block diagram of an information processing apparatus for a first processor system and an information processing apparatus for a reconfigurable processing system according to an embodiment of the present disclosure;

Fig. 5 schematically shows a block diagram of an information processing apparatus according to an embodiment of the present disclosure;

FIG. 6 schematically shows a schematic diagram of an application scenario according to another embodiment of the present disclosure;

fig. 7 schematically illustrates a mapping relationship between a first address space and a virtual address space according to an embodiment of the disclosure.

Detailed Description

hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. The words "a", "an" and "the" and the like as used herein are also intended to include the meanings of "a plurality" and "the" unless the context clearly dictates otherwise. Furthermore, the terms "comprises," "comprising," and the like, as used herein, specify the presence of stated features, steps, operations, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, or components.

All terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art unless otherwise defined. It is noted that the terms used herein should be interpreted as having a meaning that is consistent with the context of this specification and should not be interpreted in an idealized or overly formal sense.

Where a convention analogous to "at least one of A, B and C, etc." is used, in general such a construction is intended in the sense one having skill in the art would understand the convention (e.g., "a system having at least one of A, B and C" would include but not be limited to systems that have a alone, B alone, C alone, a and B together, a and C together, B and C together, and/or A, B, C together, etc.). Where a convention analogous to "A, B or at least one of C, etc." is used, in general such a construction is intended in the sense one having skill in the art would understand the convention (e.g., "a system having at least one of A, B or C" would include but not be limited to systems that have a alone, B alone, C alone, a and B together, a and C together, B and C together, and/or A, B, C together, etc.). It will be further understood by those within the art that virtually any disjunctive word and/or phrase presenting two or more alternative terms, whether in the description, claims, or drawings, should be understood to contemplate the possibilities of including one of the terms, either of the terms, or both terms. For example, the phrase "a or B" should be understood to include the possibility of "a" or "B", or "a and B".

Some block diagrams and/or flow diagrams are shown in the figures. It will be understood that some blocks of the block diagrams and/or flowchart illustrations, or combinations thereof, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the instructions, which execute via the processor, create means for implementing the functions/acts specified in the block diagrams and/or flowchart block or blocks.

accordingly, the techniques of this disclosure may be implemented in hardware and/or software (including firmware, microcode, etc.). In addition, the techniques of this disclosure may take the form of a computer program product on a computer-readable medium having instructions stored thereon for use by or in connection with an instruction execution system. In the context of this disclosure, a computer-readable medium may be any medium that can contain, store, communicate, propagate, or transport the instructions. For example, the computer readable medium can include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, device, or propagation medium. Specific examples of the computer readable medium include: magnetic storage devices, such as magnetic tape or Hard Disk Drives (HDDs); optical storage devices, such as compact disks (CD-ROMs); a memory, such as a Random Access Memory (RAM) or a flash memory; and/or wired/wireless communication links.

A reconfigurable processor is a new processor architecture that may typically take the form of a hardware computational array that may include a plurality of arithmetic logic units (also referred to as operators). The arithmetic logic unit can realize various arithmetic logic functions, so that the reconfigurable processor can flexibly realize various arithmetic functions by dynamically configuring the arithmetic logic units (for example, dynamically changing the interconnection relationship among the arithmetic logic units, and the like), and the operational performance can be greatly improved by using the hardware operation circuit.

as mentioned above, due to the rapid development of electronic technology, the existing processor architecture faces a great challenge in terms of performance, load, etc. If the reconfigurable processor is combined with the existing processor architecture, the reconfigurable processor is used to assist the existing processor architecture to execute some tasks, that is, some tasks of the existing processor architecture are "offloaded" (offloaded) to the reconfigurable processor, so that the overall processing performance and processing flexibility can be greatly enhanced. It will be appreciated that a wide variety of tasks may be "offloaded" from existing processor architectures to reconfigurable processors. For example, such tasks may include tasks that occupy a significant amount of the computational resources of existing processor architectures, such as encryption/decryption tasks, and the like. Thus, not only the processing efficiency of the offloaded task but also the efficiency of the existing processor architecture for processing other tasks can be improved.

However, how to make the reconfigurable processor interact with the existing processor architecture becomes a problem to be solved. In view of this, the embodiments of the present disclosure provide corresponding solutions, which enable efficient cooperative operations between a reconfigurable processor and an existing processor architecture.

Specifically, embodiments of the present disclosure provide an information processing method and an information processing apparatus to which the method can be applied. In an embodiment of the disclosure, a non-reconfigurable first processor system generates and writes a first command frame in a PCIe command space, the first command frame including task information for instructing the reconfigurable processing system to execute a first task. The PCIe command space is shared by the first processor system and the reconfigurable processing system. The reconfigurable processing system obtains a first command frame from the PCIe command space, executes a first task in the first command frame to obtain return information, generates a first response frame according to the return information, and writes the first response frame into the PCIe command space. The first processor system obtains a first reply frame from the PCIe command space, resulting in return information for the first task.

Fig. 1 schematically illustrates an application scenario of the information processing method and system according to the embodiment of the present disclosure.

As shown in fig. 1, the application scenario includes a non-reconfigurable first processor system 110 and a reconfigurable processing system 120.

The first processor system 110 may include any suitable variety of general-purpose or special-purpose processors known in the art, such as a Central Processing Unit (CPU), for example, the X86 architecture. The first processor system 110 may also include related components known in the art, such as a memory module. For example, for the X86 architecture, a Double Data Rate (DDR) memory or the like may be included.

The reconfigurable processing system 120 may include a reconfigurable processor. Reconfigurable processors may also be referred to as Reconfigurable Processing Units (RPUs). As previously mentioned, the reconfigurable processor may be in the form of a hardware computational array, i.e. may include a plurality of operators to implement various arithmetic logic operations.

The reconfigurable processing system may also include other components that cooperate to perform arithmetic and logical operations. For example, the reconfigurable processing system may include a Micro Controller Unit (MCU) and a storage control module. The MCU may control the reconfigurable processing unit, for example, configure the reconfigurable processing unit to implement a corresponding algorithm function, etc. The storage control module can be used for performing read-write operation on the memory and the like. For example, the storage control module may include a Direct Memory Access (DMA) module.

In one embodiment, the reconfigurable processing System may be implemented as a System on Chip (SoC).

Further, the first processor system 110 and the reconfigurable processing system 120 may each include PCIe modules. A PCIe module may also be referred to as a PCIe interface. The PCIe modules in both the first processor system 110 and the reconfigurable processing system 120 may be connected through a PCIe bus. In this way, the first processor system 110 and the reconfigurable processing system 120 may interact via a PCIe such high-speed serial computer expansion bus, for example, data and/or command interaction via a PCIe bus.

According to an embodiment of the disclosure, the first processor system 110 and the reconfigurable processing system 120 may have a shared PCIe command space therebetween. That is, the PCIe command space can be accessed by both the first processor system 110 and the reconfigurable processing system 120, for example, the first processor system 110 and the reconfigurable processing system 120 can write commands and/or data into the PCIe command space, and at the same time, can read commands and/or data from the PCIe command space. In the embodiment of the present disclosure, the PCIe command space may be disposed in a PCIe module of the reconfigurable processing system 120, may be disposed in a PCIe module of the first processor system 110, or may be disposed in a location where the reconfigurable processing system 120 and the first processor system 110 can access through a PCIe bus.

according to the embodiment of the disclosure, the first processor system 110 may generate a command frame and write the command frame into a PCIe command space, where the command frame may include task information, and the task information may be used to instruct the reconfigurable processing system 120 to execute a certain task. The reconfigurable processing system 120 acquires and analyzes the command frame from the PCIe command space, executes a corresponding task according to the task information to obtain return information, generates a response frame according to the return information, and writes the response frame into the PCIe command space. Then, the first processor system 110 obtains and parses the response frame from the PCIe command space, thereby obtaining a processing result for the task information.

In the embodiment of the disclosure, information interaction between the first processor system and the reconfigurable processing system is realized by using the PCIe command space as a hub, so that the first processor system can call the reconfigurable processing system through the PCIe bus to execute various functions, thereby improving the processing performance of tasks, and the reconfigurable processing system can assist the first processor system in completing various different tasks due to the configuration flexibility of the reconfigurable processing system. Therefore, the reconfigurable processing system and the existing processor architecture can efficiently cooperate to operate, so that the processing performance and the processing flexibility are greatly enhanced.

An information processing method according to an exemplary embodiment of the present invention is described below with reference to fig. 2 in conjunction with the application scenario of fig. 1. It should be noted that the above application scenarios are merely illustrated for the convenience of understanding the spirit and principles of the present invention, and the embodiments of the present invention are not limited in this respect. Rather, embodiments of the present invention may be applied to any scenario where applicable.

Fig. 2 schematically shows a flow chart of an information processing method according to an embodiment of the present disclosure.

As shown in fig. 2, the information processing method applied to the non-reconfigurable first processor system 110 includes operations S201 to S203, and the information processing method applied to the reconfigurable processing system 120 includes operations S211 to S214.

in operation S201, a first command frame is generated, where the first command frame includes task information, where the task information is used to instruct the reconfigurable processing system 120 to execute a first task.

According to the embodiment of the disclosure, the reconfigurable processing system can provide library functions and corresponding PCIe drivers which can be called by upper-layer applications. The operating system of the first processor system 110 may have a corresponding application program disposed therein, which may implement calls to library functions provided by the reconfigurable processing system. For example, when a first processor system wants to call a function of reconfigurable processing system 120, a library function of the corresponding function of the reconfigurable processing system may be called by a corresponding application program in the first processor system, and then the library function of the corresponding function may call a corresponding PCIe driver.

In one embodiment, the first task may also be a non-data processing task, i.e., the first processor system 110 may invoke the reconfigurable processing system 120 to perform some operation. For example, the first task is to instruct the reconfigurable processing system to perform operations such as restart, self-test, or formatting.

in another embodiment, the first task may be a data processing task, i.e., the first processor system 110 calls the reconfigurable processing system 120 to process certain data. For example, the first task is to instruct the reconfigurable processing system to perform encryption processing or decryption processing on certain data.

when the first task is a data processing task, the first processor system may also interact with the reconfigurable processing system for task data associated with the first task.

in the embodiment of the disclosure, the first processor system and the reconfigurable processing system may exchange task data through the storage area or exchange task data through the PCIe command space.

For example, the first processor system may interact with the reconfigurable processing system for task data in a memory area accessible to the first processor system. Wherein the first processor system accesses the memory region using the first address space. The first address space has a mapping relationship with a virtual address space at the reconfigurable processing system, so that the reconfigurable processing system can access the storage area based on the mapping relationship. In this way, the first processor system and the reconfigurable processing system can both access the memory region.

For example, the first processor system may write the task data into the memory area so that the reconfigurable processing system may retrieve the task data from the memory area. Alternatively, the reconfigurable processing system may write the task data into the storage area so that the first processor system can acquire the task data from the storage area.

The first address space used by the first processor system may be a physical address space or a logical address space corresponding to the storage area, which is not limited in this disclosure.

In another embodiment, the first processor system may write the task data in a command frame or the reconfigurable processing system writes the task data in a reply frame, thereby interacting with the task data through the PCIe command space.

According to an embodiment of the present disclosure, the task data may include source data that needs to be processed by the reconfigurable processing system, and the task information may indicate what kind of processing is performed on the source data by the reconfigurable processing system.

in one embodiment, the first processor system may write the source data in the first command frame, such that the source data may be directly transmitted to the reconfigurable processing system through the first command frame. In this way, the time for the reconfigurable processing system to acquire the source data can be shortened, and the processing speed of the reconfigurable processing system can be improved.

In another embodiment, the first processor system may write the source data into a storage area accessible to both the first processor system and the reconfigurable processing system so that the reconfigurable processing system may retrieve the source data from the storage area. This way, the size of the command frame can be reduced, and thus the time for writing or retrieving the command frame in the PCIe command space can be shortened.

The manner of delivery of the source data may be selected according to the actual situation.

For example, the manner of delivery of the source data may be related to the format of the first command frame. In this way, the reconfigurable processing system can know which transfer mode to acquire the source data after determining the format of the first command frame.

For another example, a flag bit may be added to the first command frame to indicate the manner of delivery of the source data. In this way, the reconfigurable processing system can determine the transmission mode of the source data according to the flag bit.

As another example, which delivery method to use may be selected based on the size of the source data.

For example, the first processor system may write the source data in the first command frame when the size of the source data is less than or equal to the first threshold. That is, when the first task is a data processing task and the size of source data that needs to be processed is less than or equal to the first threshold, the first command frame may include the source data and task information of what kind of processing needs to be performed on the source data. The first threshold value may be predefined according to the actual situation. In this embodiment, for relatively small source data, the source data can be transmitted to the reconfigurable processing system through the command frame, which can save the time for transmitting the source data, thereby accelerating the processing speed.

For example, when the size of the source data is larger than a first threshold, the first processor system and the reconfigurable processing system may transfer the source data through a memory area that can be commonly accessed. In this embodiment, relatively large source data can be transmitted to the reconfigurable processing system through the storage area, so that the size of the command frame can be reduced, and the writing or acquiring time of the command frame can be shortened.

For the case of communicating source data through the above-described storage region, the first command frame may further include source address information, which may indicate an address (may be referred to herein as a source address) for storing the source data. In particular, the source address information may indicate a first source address, which may be an address in a first address space, or a second source address, which may be an address in a virtual address space. In the case that the first command frame includes the second source address, the first processor system may first convert the first source address into the second source address, that is, into an address in the virtual address space, according to the mapping relationship, and then write the second source address into the first command frame.

In addition, since the reconfigurable processing system can only recognize the address in the virtual address space, that is, can only acquire the source data according to the address in the virtual address space, if the first command frame includes the first source address, the reconfigurable processing system can convert the first source address into the second source address by using the mapping relationship, so that the reconfigurable processing system can acquire the source data according to the second source address.

it is understood that the first processor system and the reconfigurable processing system may pre-define whether the source address information in the first command frame indicates an address in the first address space or an address in the virtual address space, so as to avoid generating incorrect address information due to repeated conversion.

In the embodiment of the present disclosure, the first command frame may further include a number, and the number may be used to match the command frame with the corresponding response frame. For example, the response frame may include the same number as the command frame to indicate that the response frame is feedback information obtained for the command frame having the same number.

For example, when the first processor system calls an Advanced Encryption Standard (AES) Encryption function of the reconfigurable processing system, if the source data is transferred through the first command frame, the first command frame may include therein: a frame number (to match the response frame), source data (i.e., plaintext data to be processed), and task information (e.g., invoking an encryption function of the reconfigurable processing system, implementing encryption of the source data by the AES algorithm, etc.), etc.

For the case where the source data (i.e., the plaintext data to be processed) is transferred through the storage area, the first command frame may include therein: a frame number (to match the response frame), source address information, a data length of the source data, and task information (for example, calling an encryption function of the reconfigurable processing system, implementing encryption of the source data by an AES algorithm, and the like).

in operation S202, a first command frame is written into a PCIe command space, where the PCIe command space is shared by the first processor system and the reconfigurable processing system.

According to an embodiment of the present disclosure, after writing the first command frame into the PCIe command space, the first processor system may further include: and sending a first interrupt instruction to the reconfigurable processing system, wherein the first interrupt instruction indicates that a first command frame is written into a PCIe command space so as to inform the reconfigurable processing system of receiving the first command frame.

In operation S211, the reconfigurable processing system obtains a first command frame from the first processor system from a PCIe command space.

According to one embodiment of the present disclosure, the reconfigurable processing system may obtain the first command frame from the PCIe space after receiving the first interrupt instruction from the first processor system. By initiating the interrupt to the reconfigurable processing system, the reconfigurable processing system can be rapidly informed of receiving a new instruction, and the time waste on waiting for the instruction is avoided, so that the interaction between the first processor system and the reconfigurable processing system is simple and convenient, and the efficient cooperative operation between the first processor system and the reconfigurable processing system can be further realized.

It is to be understood that the present disclosure is not limited to the method of initiating interrupts in the above examples to inform the reconfigurable processing system that a new instruction arrives. For example, the reconfigurable processing system may also determine whether there is a new instruction by polling or the like.

in operation S212, the reconfigurable processing system executes the first task, and obtains return information indicating a result obtained by the reconfigurable processing system for the first task.

According to an embodiment of the present disclosure, when the first task is a non-data processing task, for example, a restart, a self-test, or a formatting operation, the reconfigurable processing system executes a corresponding task according to task information, and obtains return information, where the return information may include, for example, a failure code that is successful in execution or failed in execution.

According to another embodiment of the present disclosure, the first task may be a data processing task, such as performing encryption processing on the source data.

in an embodiment, if the first command frame includes source data, the reconfigurable processing system parses the first command frame to obtain the source data and task information, and performs corresponding processing on the source data according to the task information, for example, performs AES algorithm encryption on the source data to obtain encrypted destination data.

In another embodiment, if the first command frame includes source address information, the reconfigurable processing system may parse the first command frame to obtain the source address information. As described above, the source address information may indicate a first source address or a second source address where the source data is stored. If the source address information indicates the first source address, the reconfigurable processing system may convert the first source address into the second source address according to the mapping relationship, and then acquire the source data in the storage area according to the second source address. If the source address information indicates a second source address, the reconfigurable processing system may acquire the source data in the storage area directly from the second source address. After the source data is acquired, the reconfigurable processing system can perform corresponding processing on the source data according to the task information to obtain processed target data.

in operation S213, the reconfigurable processing system generates a first response frame including the return information.

In the embodiment of the present disclosure, similar to the manner of transferring the source data, the destination data obtained by executing the first task may be transferred to the first processor system in two ways.

In one embodiment, the reconfigurable processing system may communicate the destination data to the first processor system via a memory region that is commonly accessible to the reconfigurable processing system and the first processor system. For example, the reconfigurable processing system may write the destination data into a storage area, and then the first processor system may acquire the destination data from the storage area. The first processor system may access the storage area through a first address space having a mapping relationship with a virtual address space at the reconfigurable processing system such that the reconfigurable processing system may access the storage area according to the mapping relationship.

In this case, destination address information may be included in the first command frame or the first response frame, and the destination address information may indicate an address (may be referred to as a destination address herein) where destination data is stored. For example, the destination address information may indicate a first destination address or a second destination address. The first destination address may be an address in a first address space and the second destination address may be an address in a virtual address space.

It will be appreciated that if destination address information is included in the first command frame, this means that the first processor system may specify to the reconfigurable processing system the location in the memory area for storing the destination data. And if the destination address information is included in the first response frame, this means that the reconfigurable processing system can select a location in the memory area for storing the destination data by itself. The specific selection method can be determined according to actual situations, and the embodiments of the present disclosure are not limited.

Further, if the first command frame includes destination address information and the destination address information indicates a second destination address, the first processor system may first convert the first destination address to the second destination address according to the mapping and then write the second destination address into the first command frame. If the first reply frame includes the destination address information and the destination address information indicates the first destination address, the reconfigurable processing system may first convert the second destination address into the first destination address according to the mapping relationship, and then write the first destination address into the first reply frame.

The first processor system may agree in advance with the reconfigurable processing system whether the destination address information in the first command frame or the first response frame indicates an address in the first address space or an address in the virtual address space, thereby avoiding generation of erroneous address information due to repeated conversion.

In another embodiment, the reconfigurable processing system may pass the destination data to the first processor system through a PCIe command space. For example, the reconfigurable processing system may write the destination data into a first reply frame, and then the first processor system may retrieve the first reply frame from the PCIe command space and then retrieve the destination data from the first reply frame.

the two ways of transferring the destination data may be chosen according to the actual situation.

For example, the manner of delivering the destination data may be related to the format of the first command frame or the format of the first response frame. If the transmission mode of the target data is related to the format of the first command frame, the reconfigurable processing system determines the transmission mode of the target data according to the format of the first command frame. If the manner in which the destination data is communicated is related to the format of the first reply frame, the first processor system may determine the manner in which the destination data is obtained based on the format of the first reply frame.

For another example, a flag bit may be added to the first command frame or the first response frame to indicate the transfer mode of the destination data.

For another example, the transfer mode may be selected according to the size of the destination data.

For example, if the size of the destination data is smaller than or equal to the second threshold, the reconfigurable processing system may include the destination data in the first reply frame. And if the size of the target data is larger than the second threshold value, the reconfigurable processing system can write the target data into the storage area.

In operation S214, the first reply frame is written into the PCIe command space.

According to the embodiment of the disclosure, after writing the first response frame into the PCIe command space, the reconfigurable processing system further includes: a second interrupt instruction is sent to the first processor system indicating that the first reply frame has been written into the PCIe command space to notify the first processor system to receive the first reply frame. By initiating the interrupt to the first processor system, the first processor system can be rapidly informed of receiving a new instruction, the waste of time on waiting for the instruction is avoided, the interaction between the first processor system and the reconfigurable processing system is simple and convenient, and the efficient cooperative operation between the first processor system and the reconfigurable processing system can be further realized.

it will be appreciated that the present disclosure is not limited to the method of initiating an interrupt in the above example to inform the first processor system that a new instruction has arrived. For example, the first processor system may also determine whether there is a new instruction by polling or the like.

In operation S203, the first processor system obtains a first reply frame from the reconfigurable processing system from a PCIe command space.

according to the embodiment of the disclosure, the first processor system acquires the first response frame from the PCIe space after receiving the second interrupt instruction from the reconfigurable processing system.

the source data transmission method and the destination data transmission method may be independent of each other. That is, the source data may be transferred in the same manner as or different from the destination data, and the embodiment of the present disclosure does not limit this.

in the embodiment of the disclosure, the information interaction between the first processor system and the reconfigurable processing system is realized by using the PCIe command space as a hub, so that the first processor system can call the functions provided by the reconfigurable processing system through the PCIe, and the efficient and high-performance processing of tasks can be realized; and due to the configuration flexibility of the reconfigurable processing system, the first processor system can complete various different tasks by using the reconfigurable processing system, so that the processing flexibility can be greatly enhanced.

It will be appreciated that both the first address space and the virtual address space described above actually point to the storage area. Preferably, the memory area may be located on the first processor system side. Of course in other embodiments the memory area may be located at any other suitable location as long as the first processor system and the reconfigurable processing system are commonly accessible.

In one embodiment, the storage area may be predefined. For example, a storage area for the interactive task data may be previously designated between the first processor system and the reconfigurable processing system. In this case, the reconfigurable processing system may store a mapping relationship between the first address space and its virtual address space in advance.

In another embodiment, the storage area may be dynamically assigned. For example, the first processor system may dynamically notify the reconfigurable processing system of a memory area for the interactive task data through a command frame or the like. In this case, the reconfigurable processing system may dynamically establish a mapping relationship between the first address space and its virtual address space in accordance with the notification of the first processor system.

For example, the mapping between the first address space and the virtual address space may be performed at an initial stage of the first processor system establishing communication with the reconfigurable processing system. The mapping relationship between the address spaces may remain unchanged during communication of the first processor system with the reconfigurable processing system. This configuration can reduce the instruction overhead between the first processor system and the reconfigurable processing system and improve the operating speeds of both systems.

As another example, the mapping between the first address space and the virtual address space may be performed before task data needs to be exchanged between the first processor system and the reconfigurable processing system in the memory area. For example, the first processor system instructs the reconfigurable processing system to process the source data, and the source data needs to be transferred to the reconfigurable processing system through the storage area, so that the first processor system may perform mapping between the first address space and the virtual address space with the reconfigurable processing system before writing the first command frame into the PCIe command space. The mode is relatively flexible, and the storage area for the interaction task data can be flexibly selected according to actual requirements.

For example, whether statically specified or dynamically established, the reconfigurable processing system may store the mapping relationship in a memory thereof, for example, in an Address Translation Unit (ATU) register.

For another example, the mapping relationship may be obtained by an address conversion formula known to both the first processor system and the reconfigurable processing system. The address translation formula may be specified in accordance with actual circumstances.

in general, the first processor system may not necessarily store the above mapping relationship, and each time an address in a virtual address space at the reconfigurable processing system needs to be used, the address in the first address space is converted according to an address conversion formula to obtain a corresponding address in the virtual address space.

Fig. 3 schematically illustrates a flowchart for establishing a mapping relationship between a first address space and a virtual address space at a reconfigurable processing system according to an embodiment of the present disclosure.

As shown in fig. 3, the method of establishing a mapping relationship applied to the first processor system 110 includes operations S301 to S303, and the method of establishing a mapping relationship applied to the reconfigurable processing system 120 includes operations S311 to S314.

In operation S301, the first processor system generates a second command frame including address space information indicating a first address space used by the first processor system.

For example, the first processor system may determine a block of memory area for storing task data interacting with the reconfigurable processing system and write address space information corresponding to the block of memory area to the second command frame.

For example, in the case where the first processor system is a similar processor system such as the X86 architecture, the storage area may be located in the DDR memory of the X86 architecture. The first address space may be a physical address space corresponding to the DDR memory, or may be a logical address space. That is, the first processor system may address the memory region by a physical address or a logical address.

For example, the address space information may include a start address and an address length of a memory area to be used. The start address and the address length may be for a first address space.

For example, the second command frame may include: a frame number, a start address and an address length of the storage area, task information (e.g., the task information may indicate that a mapping relationship between address spaces is established), and the like.

For example, the starting address of the storage area is an address in the first address space, and the address length is an address length in the first address space.

In operation S302, the first processor system writes a second command frame into the PCIe command space.

For example, after the first processor system generates the second command frame, the command frame may be written into a PCIe command space, and a third interrupt instruction is sent to the reconfigurable processing system, where the third interrupt instruction indicates that the second command frame has been written into the PCIe command space, so as to notify the reconfigurable processing system to obtain the second command frame from the command space and perform corresponding processing. By initiating the interrupt to the reconfigurable processing system, the reconfigurable processing system can be rapidly informed of receiving a new instruction, and the time waste on waiting for the instruction is avoided, so that the interaction between the first processor system and the reconfigurable processing system is simple and convenient, and the efficient cooperative operation between the first processor system and the reconfigurable processing system can be further realized.

In operation S311, the reconfigurable processing system acquires a second command frame from the PCIe command space. For example, the reconfigurable processing system may acquire the above-described address space information from the second command frame.

According to the embodiment of the disclosure, the reconfigurable processing system may obtain the second command frame from the PCIe command space after receiving the interrupt instruction sent by the first processor system.

In operation S312, the reconfigurable processing system establishes a mapping relationship according to the address space information in the second command frame.

For example, the first processor system and the reconfigurable processing system may have a conversion formula between the first address space and the virtual address space defined in advance. And after the reconfigurable processing system receives the second command frame, establishing a mapping relation between the first address space and the virtual address space according to the address space information in the second command frame. For example, the reconfigurable processing system may convert the address into the start address and the address length in the virtual address space according to the start address and the address length in the first address space included in the second command frame.

The reconfigurable processing system can store the established mapping relation and find the storage area indicated by the virtual address according to the virtual address at the reconfigurable processing system and the mapping relation.

by establishing the mapping relation, the first processor system and the reconfigurable processing system can access the same storage area. For example, even when the first processor system and the reconfigurable processing system have different address bit widths, both can still access an accurate memory address. For example, the address on the first processor system side is 64 bits, and the address on the reconfigurable processing system side is 32 bits, and the reconfigurable processing system may not recognize the 64 bits of address information. However, after the mapping relationship is established, the reconfigurable processing system may map the address on the first processor system side to the corresponding virtual address, so as to address the storage area through the virtual address.

in operation S313, the reconfigurable processing system generates a second response frame.

For example, the second response frame may include the same number as the second command frame and related information such as feedback information. The feedback information may include, for example: when the flow is normal, the address mapping is completed by feedback, and when the flow is abnormal, an error code is returned, and the like.

In operation S314, the reconfigurable processing system writes the second response frame to the PCIe command space.

For example, after writing the second response frame into the PCIe command space, the reconfigurable processing system may further include: a fourth interrupt instruction is sent to the first processor system to notify the first processor system to receive the second response frame.

In operation S303, the first processor system obtains a second response frame from the PCIe command space and parses the second response frame.

for example, if the feedback information indicates that the address mapping is completed, the storage area may be used to exchange task data in a subsequent flow.

For another example, if the feedback information indicates that the address mapping fails, the first processor system may reinitiate the address mapping or take other corresponding measures.

It will be appreciated that in the above process, although reference is made to the command frame and its corresponding reply frame each including a numbering field to match between them, this numbering is not required. For example, in the case of blocking single-instruction communication (i.e., for one command frame, after obtaining the corresponding response frame, the next command frame is sent), the number field may not be needed. In the case of non-blocking multithreading communication (i.e., multiple command frames may be sent simultaneously), a number field may be included in the command frame and the response frame.

It will also be appreciated that the PCIe command space may also be divided into a PCIe receive command space and a PCIe reply command space, as appropriate. The PCIe receive command space may be used to store command frames and the PCIe reply command space may be used to store reply frames.

The embodiment of the disclosure also provides an information processing device.

Fig. 4 schematically shows a block diagram of an information processing apparatus 400 for a first processor system and an information processing apparatus 500 for a reconfigurable processing system according to an embodiment of the present disclosure.

as shown in fig. 4, the information processing apparatus 400 for the first processor system may include a first generation module 401, a first writing module 402, a first acquisition module 403. Optionally, the information processing apparatus 400 may further include a first interaction module 404, a second generation module 405, a second writing module 406, a second obtaining module 407, a first interruption module 408, and a second interruption module 409.

In addition, as shown in fig. 4, the information processing apparatus 500 for a reconfigurable processing system may include a third obtaining module 501, an executing module 502, a third generating module 503, and a third writing module 504. Optionally, the information processing apparatus 500 may further include a second interaction module 505, a fourth obtaining module 506, an address establishing module 507, a fourth generating module 508, a fourth writing module 509, a third interruption module 510, and a fourth interruption module 511.

Each module in the information processing apparatus 400 may perform the corresponding operation in operations S201 to S203 and operations S301 to S303 described above with reference to fig. 2 to 3, and each module in the information processing apparatus 500 may perform the corresponding operation in operations S211 to S214 and operations S311 to S314 described above with reference to fig. 2 to 3, to implement the processing of information. Specific description may be made with reference to the above-described respective embodiments, and will be appropriately omitted herein.

Specifically, the first generation module 401 generates a first command frame, which includes task information for instructing the reconfigurable processing system to execute a first task.

The first write module 402 writes the first command frame into a PCIe command space, wherein the PCIe command space is shared by the first processor system and the reconfigurable processing system.

The first obtaining module 403 obtains a first response frame from the reconfigurable processing system (for example, the information processing apparatus 500 for a reconfigurable processing system) from a PCIe command space, where the first response frame includes return information indicating a result obtained by the reconfigurable processing system for the first task.

The first interaction module 404 interacts with the reconfigurable processing system task data associated with the first task when the first task is a data task. For example, interacting with the reconfigurable processing system task data associated with the first task may include: and interacting task data with the reconfigurable processing system in a storage area which can be accessed by the first processor system, wherein the first processor system uses a first address space to access the storage area, and the first address space and a virtual address space at the reconfigurable processing system have a mapping relation, so that the reconfigurable processing system can access the storage area based on the mapping relation.

the second generation module 405 generates a second command frame that includes address space information indicating the first address space.

the second writing module 406 writes the second command frame into the PCIe command space such that the address space information is used by the reconfigurable processing system to establish the mapping relationship.

The second obtaining module 407 obtains a second response frame from the reconfigurable processing system from the PCIe command space, where the second response frame indicates that the reconfigurable processing system successfully establishes the mapping relationship.

according to an embodiment of the disclosure, the task data includes source data, and the first task includes processing the source data.

Optionally, the first command frame may further include source address information indicating a first source address or a second source address for storing the source data, wherein the first source address is an address in the first address space and the second source address is an address in the virtual address space. Alternatively, in this case, the size of the source data may be larger than the first threshold.

Optionally, interacting with the reconfigurable processing system task data associated with the first task may include: the source data is written in a first command frame. In this case, the size of the source data may be less than or equal to the first threshold.

According to another embodiment of the disclosure, the task data includes destination data, the first task includes processing the source data, and the destination data is obtained by processing the source data by the reconfigurable processing system.

Optionally, the first command frame or the first reply frame includes destination address information indicating a first destination address or a second destination address for storing the destination data, the first destination address being an address in a first address space, the second destination address being an address in a virtual address space. Alternatively, in this case, the size of the destination data may be larger than the second threshold.

Optionally, interacting with the reconfigurable processing system task data associated with the first task comprises: and acquiring target data included in the first response frame. In this case, the size of the destination data may be less than or equal to the second threshold.

Optionally, the first interrupt module 408 sends a first interrupt instruction to the reconfigurable processing system after writing the first command frame in the PCIe command space, the first interrupt instruction indicating that the first command frame has been written in the PCIe command space.

optionally, the first interrupt module 408 may further generate a third interrupt instruction to the reconfigurable processing system after writing the second command frame into the PCIe command space, the third interrupt instruction indicating that the second command frame has been written into the PCIe command space.

Optionally, the second interrupt module 409 receives a second interrupt instruction from the reconfigurable processing system indicating that the first reply frame has been written into the PCIe command space before obtaining the first reply frame from the reconfigurable processing system from the PCIe command space.

Optionally, the second interrupt module 409 may further receive a fourth interrupt instruction from the reconfigurable processing system before obtaining the second reply frame from the reconfigurable processing system from the PCIe command space, the fourth interrupt instruction indicating that the second reply frame has been written into the PCIe command space.

The operation of each module included in the information processing apparatus 500 will be briefly described below.

the third obtaining module 501 obtains a first command frame from a first processor system (for example, the information processing apparatus 400 for the first processor system) from a PCIe command space, the first command frame including task information for instructing the reconfigurable processing system to execute a first task, the PCIe command space being shared by the first processor system and the reconfigurable processing system.

The execution module 502 executes the first task to obtain return information, where the return information is used to indicate a result obtained by the reconfigurable processing system for the first task.

the third generating module 503 generates a first reply frame, which includes return information.

The third write module 504 writes the first reply frame in the PCIe command space.

The second interaction module 505 interacts with the first processor system task data associated with the first task when the first task is a data processing task. Interacting task data associated with the first task with the reconfigurable processing system may include: and interacting task data with the reconfigurable processing system in a storage area which can be accessed by the first processor system, wherein the first processor system uses a first address space to access the storage area, and the first address space and a virtual address space at the reconfigurable processing system have a mapping relation, so that the reconfigurable processing system can access the storage area based on the mapping relation.

The fourth obtaining module 506 obtains a second command frame from the PCIe command space, where the second command frame includes address space information indicating the first address space.

The address establishing module 507 establishes a mapping relationship according to the address space information.

The fourth generating module 508 generates a second response frame, wherein the second response frame may indicate that the mapping relationship is successfully established.

The fourth write module 509 writes the second reply frame into the PCIe command space.

According to an embodiment of the present disclosure, the task data may include source data, and the first task includes processing the source data.

Optionally, interacting with the reconfigurable processing system task data associated with the first task comprises: the source data is written in a first command frame. Alternatively, in this case, the size of the source data may be less than or equal to the first threshold.

According to another embodiment of the disclosure, the task data may include destination data, and the first task includes processing the source data, and the destination data is obtained by processing the source data by the reconfigurable processing system.

Optionally, the first command frame or the first reply frame includes destination address information, the destination address information indicating a first destination address or a second destination address for storing destination data, the first destination address being an address in a first address space, and the second destination address being an address in a virtual address space. Alternatively, in this case, the size of the destination data may be larger than the second threshold.

optionally, interacting with the reconfigurable processing system task data associated with the first task comprises: and acquiring target data included in the first response frame. Alternatively, in this case, the size of the destination data may be less than or equal to the second threshold.

the third interrupt module 510 receives a first interrupt instruction from the first processor system indicating that the first command frame has been written into the PCIe command space prior to obtaining the first command frame from the first processor system from the PCIe command space.

Optionally, the third interrupt module 510 may also receive a third interrupt instruction from the first processor system before obtaining the second command frame from the first processor system from the PCIe command space, the third interrupt instruction indicating that the second command frame has been written into the PCIe command space.

The fourth interrupt module 511, after writing the first reply frame in the PCIe command space, sends a second interrupt instruction to the first processor system, the second interrupt instruction indicating that the first reply frame has been written in the PCIe command space.

Optionally, the fourth interrupt module 511 may send a fourth interrupt instruction to the first processor system after writing the second response frame in the PCIe command space, the fourth interrupt instruction indicating that the second response frame has been written in the PCIe command space.

It is understood that the first generation module 401, the first writing module 402, the first obtaining module 403, the first interaction module 404, the second generation module 405, the second writing module 406, the second obtaining module 407, the first interruption module 408, and the second interruption module 409 of the information processing apparatus 400 may be combined in one module to be implemented, or any one of them may be split into a plurality of modules. Alternatively, at least part of the functionality of one or more of these modules may be combined with at least part of the functionality of the other modules and implemented in one module. According to the embodiment of the present invention, at least one of the first generating module 401, the first writing module 402, the first acquiring module 403, the first interacting module 404, the second generating module 405, the second writing module 406, the second acquiring module 407, the first interrupting module 408, and the second interrupting module 409 of the information processing apparatus 400 may be at least partially implemented as a hardware circuit, such as a Field Programmable Gate Array (FPGA), a Programmable Logic Array (PLA), a system on a chip, a system on a substrate, a system on a package, an Application Specific Integrated Circuit (ASIC), or may be implemented in hardware or firmware in any other reasonable manner of integrating or packaging a circuit, or implemented in a suitable combination of three implementations of software, hardware, and firmware. Alternatively, at least one of the first generating module 401, the first writing module 402, the first acquiring module 403, the first interacting module 404, the second generating module 405, the second writing module 406, the second acquiring module 407, the first interrupting module 408, and the second interrupting module 409 of the information processing apparatus 400 may be at least partially implemented as a computer program module that can perform the functions of the respective modules when the program is executed by a computer.

Similarly, the third obtaining module 501, the executing module 502, the third generating module 503, the third writing module 504, the second interacting module 505, the fourth obtaining module 506, the address establishing module 507, the fourth generating module 508, the fourth writing module 509, the third interrupting module 510, and the fourth interrupting module 511 of the information processing apparatus 500 may be combined and implemented in one module, or any one of the modules may be split into a plurality of modules. Alternatively, at least part of the functionality of one or more of these modules may be combined with at least part of the functionality of the other modules and implemented in one module. According to an embodiment of the present invention, at least one of the third obtaining module 501, the executing module 502, the third generating module 503, the third writing module 504, the second interacting module 505, the fourth obtaining module 506, the address establishing module 507, the fourth generating module 508, the fourth writing module 509, the third interrupting module 510, and the fourth interrupting module 511 of the information processing apparatus 500 may be at least partially implemented as a hardware circuit, such as a Field Programmable Gate Array (FPGA), a Programmable Logic Array (PLA), a system on a chip, a system on a substrate, a system on a package, an Application Specific Integrated Circuit (ASIC), or may be implemented in hardware or firmware in any other reasonable manner of integrating or packaging a circuit, or in a suitable combination of three implementations of software, hardware, and firmware. Alternatively, at least one of the third obtaining module 501, the executing module 502, the third generating module 503, the third writing module 504, the second interacting module 505, the fourth obtaining module 506, the address establishing module 507, the fourth generating module 508, the fourth writing module 509, the third interrupting module 510 and the fourth interrupting module 511 of the information processing apparatus 500 may be at least partially implemented as a computer program module, which, when executed by a computer, may perform the functions of the respective modules.

Fig. 5 schematically shows a block diagram of an information processing apparatus 600 according to another embodiment of the present disclosure.

As shown in fig. 5, the information processing apparatus 600 includes a processing unit 610, a computer-readable storage medium 620. The information processing apparatus 600 may perform the operations S201 to S203 and S301 to S303 in the method described above with reference to fig. 2 to 3, and may also perform the processing of the information of the operations S211 to S214 and S311 to S314 in the method described above with reference to fig. 2 to 3.

In particular, processing unit 610 may include, for example, a general purpose microprocessor, an instruction set processor and/or related chip set and/or a special purpose microprocessor (e.g., an Application Specific Integrated Circuit (ASIC)), and/or the like. The processing unit 610 may also include onboard memory for caching purposes. The processing unit 610 may be a single processing unit or a plurality of processing units for performing different actions of the information processing method flows (e.g., operations S201 to S203 and operations S301 to S303) for the first processor system according to the embodiment of the present disclosure described with reference to fig. 2 to 3, or may be a single processing unit or a plurality of processing units for performing different actions of the information processing method flows (e.g., operations S211 to S214 and operations S311 to S314) for the reconfigurable processing system according to the embodiment of the present disclosure described with reference to fig. 2 to 3.

For example, for the case where the information processing apparatus 600 is used for the first processor system, assuming that the first processor system is the X86 architecture, the processing unit 610 may be implemented as a CPU in the X86 architecture. For the case where information processing apparatus 600 is used in a reconfigurable processing system, processing unit 610 may be implemented as an MCU in the reconfigurable processing system.

Computer-readable storage medium 620 may be, for example, any medium that can contain, store, communicate, propagate, or transport the instructions. For example, a readable storage medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, device, or propagation medium. Specific examples of the readable storage medium include: magnetic storage devices, such as magnetic tape or Hard Disk Drives (HDDs); optical storage devices, such as compact disks (CD-ROMs); a memory, such as a Random Access Memory (RAM) or a flash memory; and/or wired/wireless communication links.

The computer-readable storage medium 620 may include a computer program 621, which computer program 621 may include code/computer-executable instructions that, when executed by the processing unit 610, cause the processing unit 610 to perform a method flow such as described above in connection with fig. 2-3, and any variations thereof.

The computer program 621 may be configured with, for example, computer program code comprising computer program modules. For example, in an example embodiment, code in computer program 621 may include one or more program modules, including 621A, 621B, … …, for example. It should be noted that the division and number of modules are not fixed, and those skilled in the art may use suitable program modules or program module combinations according to actual situations, so that when the program modules are executed by the processing unit 610, the processing unit 610 may execute the method flows described above with reference to fig. 2 to 3, for example, and any variations thereof.

according to an embodiment of the present disclosure, at least one of the first generating module 401, the first writing module 402, the first obtaining module 403, the first interacting module 404, the second generating module 405, the second writing module 406, the second obtaining module 407, the first interrupting module 408, and the second interrupting module 409 of the information processing apparatus 400 may be implemented as a computer program module described with reference to fig. 5, which, when executed by the processing unit 610, may implement the corresponding operations described above.

According to another embodiment of the present disclosure, at least one of the third obtaining module 501, the executing module 502, the third generating module 503, the third writing module 504, the second interacting module 505, the fourth obtaining module 506, the address establishing module 507, the fourth generating module 508, the fourth writing module 509, the third interrupting module 510 and the fourth interrupting module 511 of the information processing apparatus 500 may be implemented as a computer program module described with reference to fig. 5, which, when executed by the processing unit 610, may implement the corresponding operations described above.

embodiments of the present disclosure will be described below with reference to specific examples. It should be understood that the following examples are intended only to facilitate understanding of the disclosed embodiments by those skilled in the art, and are not intended to limit the scope of the disclosed embodiments.

fig. 6 schematically shows an application scenario of the information processing method and system according to another embodiment of the present disclosure. The scenario includes an X86 architecture 710 and a SoC 720. For example, the X86 architecture 710 may be the first processor system described above and the SoC720 may be the reconfigurable processing system described above.

For example, as shown in fig. 6, the X86 architecture 710 may include: an X86 CPU711, PCIe module 712, DDR memory 713, and DMA module 714.

SoC720 may include: MCU721, PCIe module 722, RPU723, and DMA module 724.

it is to be appreciated that, for ease of illustration, only some of the modules relevant to embodiments of the present disclosure are shown in the X86 architecture 710 and SoC720 of fig. 6. However, in other embodiments, the X86 architecture 710 and the SoC720 may also include other modules known in the art. Alternatively, the modules may have other names commonly used in the art.

according to embodiments of the present disclosure, there may be a shared PCIe command space between the X86 architecture 710 and the SoC 720. That is, both the X86 architecture 710 and the SoC720 may access the PCIe command space. In the disclosed embodiment, the PCIe command space may be disposed in the PCIe module 712, may be disposed in the PCIe module 722, or may be disposed at a location where the X86 architecture 710 and the SoC720 can be commonly accessed through a PCIe bus.

preferably, in the scenario shown in fig. 6, the PCIe command space may be provided in the PCIe module 722 of the SoC 720. For example, the PCIe command space may be divided into a PCIe receive command space and a PCIe reply command space.

The X86 CPU711, for example, can be used to generate command frames, which can then be written into a PCIe command space (e.g., PCIe receive command space) in the PCIe module 722. Alternatively, the X86 CPU711 may also obtain a reply frame from the SoC720 from a PCIe command space (e.g., PCIe reply command space) in the PCIe module 722, then analyze the reply frame, and so on.

PCIe module 712 and PCIe module 722 may be referred to as PCIe interfaces, for example. For example, the PCIe module 712 and the PCIe module 722 may be connected via a PCIe bus. Thus, the X86 architecture 710 and the SoC720 can interact over a PCIe high-speed serial computer expansion bus.

DDR memory 713 may be used, for example, to store source data and/or destination data.

the DMA module 714 may be used to transfer data, for example, to assist the X86 CPU711 in transferring source data into the DDR memory 713, or assist the X86 CPU711 in transferring destination data from the DDR memory 713, so as to save the time for the X86 CPU711 to transfer data.

MCU721 may be used, for example, to obtain a command frame from a PCIe command space (e.g., PCIe receive command space) in PCIe module 722 and to parse out executing the command frame. Alternatively, the MCU721 generates the reply frame and writes the reply frame in a PCIe command space (e.g., PCIe reply command space) in the PCIe module 722. The MCU721 may also be used to control the RPU723, e.g., configure the RPU723 to implement a corresponding task (e.g., a first task in the embodiments of the present disclosure), and so on.

The RPU723 may be in the form of a hardware computational array, i.e., may include multiple operators to implement various arithmetic logic operations. For example, the tasks in the command frame are processed and results (e.g., destination data) are generated.

The DMA module 724 may be used, for example, to carry data. For example, the DMA module 724 assists the MCU721 in transferring source data from the DDR memory 713 to the RPU723, or assists the MCU721 in transferring destination data obtained by the RPU723 to the DDR memory 713, so as to save the time for the MCU721 to transfer data.

in the application scenario shown in fig. 6, the operations in the above embodiments may be implemented. For example, the X86 CPU711 may perform the above-described respective operations related to the first processor system (e.g., operations S201 to S203 and operations S301 to S303), and the MCU721 may perform the above-described respective operations related to the reconfigurable processing system (e.g., operations S211 to S214 and operations S311 to S314). For specific description, reference may be made to the above embodiments, which are not described herein again.

According to the embodiment of the disclosure, the first processor system and the reconfigurable processing system can access the same memory area. The first processor system may access the memory region through a first address space, and the reconfigurable processing system may access the memory region through a virtual address space. In the application scenario shown in fig. 6, the X86 architecture 710 may be the first processor system described above, and the SoC720 may be the reconfigurable processing system described above. The storage area may be located in DDR memory 713. The X86 CPU711 may access the DDR memory 713 using a DDR address space, and the MCU721 may access the DDR memory 713 using an MCU address space. The DDR address space here may be the first address space, and the MCU address space may be the virtual address space. In order to make the X86 CPU711 and the MCU721 access the same memory region in the DDR memory 713, a mapping relationship may be established between the DDR address space and the MCU address space.

In the following, in conjunction with the application scenario shown in fig. 6, a mapping relationship between a DDR address space and an MCU address space according to an exemplary embodiment of the present disclosure is described with reference to fig. 7.

Fig. 7 schematically shows a mapping relationship between a DDR address space and an MCU address space according to an embodiment of the present disclosure.

as shown in fig. 7, a mapping relationship may be established between the DDR address space and the MCU address space. For example, a mapping relationship may be established between a Source Address (SRC ADDR) in the DDR Address space and an SRC ADDR in the MCU Address space. For another example, a mapping relationship may be established between a Destination Address (DST ADDR) in the DDR Address space and a DST ADDR in the MCU Address space.

The SRC ADDR may be an address of the DDR memory 713 where the source data is stored. The DST ADDR may be an address of the DDR memory 713 where destination data is stored.

The X86 CPU may write source data at corresponding locations in DDR memory 713 based on the SRC ADDR in DDR address space. The MCU may obtain source data at a corresponding location in the DDR memory 713 based on the SRC ADDR in the MCU address space.

the MCU may write the destination data to a corresponding location in the DDR memory 713 based on the DST ADDR in the MCU address space. The X86 CPU may obtain destination data from a corresponding location in the DDR memory 713 based on the DST ADDR in the DDR address space.

According to an embodiment of the present disclosure, the DDR address space may be, for example, a physical address space, and the MCU address space may be, for example, a virtual address space.

As can be seen, in the above embodiment, by establishing a mapping relationship between the DDR address space and the MCU address space, the X86 CPU and the MCU can access the same memory region.

As described above, in the embodiments of the present disclosure, the first processor system may call the reconfigurable processing system to execute various tasks, thereby enhancing processing performance and increasing processing speed. For example, the first processor system may schedule the reconfigurable processing system for encryption and decryption processing.

With the rapid development of electronic technology, the security situation of information systems becomes more and more severe, and more stringent requirements are placed on encryption and decryption processes. Currently, various technologies typically use software algorithms or implement encryption and decryption through a fixed-function cryptographic chip.

However, the encryption and decryption speed achieved by the software algorithm is low, the security is low, and although the encryption and decryption speed is improved by the password chip with fixed functions and is safer than the software algorithm to a certain extent, the hardware structure cannot be changed, and the requirement of the existing password application on the flexibility cannot be met.

the reconfigurable processing system can realize different combination of cryptographic algorithms, and a user can customize the loading mode of the algorithms, so that the flexibility of encryption and decryption can be improved, and the reconfigurable processing system has higher execution speed compared with a software algorithm.

Furthermore, software algorithms typically consume significant computing resources of existing processor systems, which can result in significant performance degradation of existing processor systems. If the reconfigurable processing system is used to execute the encryption and decryption tasks, that is, the encryption and decryption tasks occupying a large amount of computing resources are unloaded from the existing processor system to the reconfigurable processing system, not only the processing efficiency of the unloaded encryption and decryption tasks can be improved, but also the efficiency of the existing processor architecture for processing other tasks can be improved.

More preferably, the reconfigurable processing system can be specially configured to process the encryption and decryption tasks, so that the processing efficiency and the processing performance of the encryption and decryption tasks can be further improved.

In order to realize encryption and decryption by using the reconfigurable processing system, interaction between the existing processor system and the reconfigurable processing system is required. Then, by using the embodiment of the present disclosure, the existing processor system and the reconfigurable processing system can efficiently cooperate, so that efficient and secure encryption and decryption can be realized.

The application scenarios described below in conjunction with fig. 6-7 and the methods described in fig. 2-3 describe a process for implementing AES encryption in cooperation between the X86 architecture 710 and the SoC 720. It is to be understood that this embodiment is only for the sake of understanding, and the present disclosure does not limit the function of the reconfigurable processing system that is called. Furthermore, although the AES Encryption Algorithm is described as an example in the following examples, in various embodiments, the reconfigurable processing system may be configured to execute various types of Encryption and decryption algorithms, such as a Hash Algorithm like MD5(Message Digest Algorithm 5), SM3, SHA256(Secure Hash Algorithm 256), SM4, DES (Data Encryption Standard), and a grouping Algorithm like the AES described above, and the like.

In the following description, it is assumed that the X86 architecture 710 first performs mapping between address spaces and the SoC720, and then the X86 architecture 710 schedules the SoC720 for encryption processing, wherein plaintext and encrypted ciphertext are exchanged between the X86 architecture 710 and the SoC720 by using a storage area in the DDR memory 713.

in addition, in this example, it is assumed that the PCIe command space is provided in the PCIe module 722, and the PCIe command space may include a PCIe receive command space and a PCIe reply command space.

the mapping process between address spaces can be as follows.

(1) The X86 CPU711 generates an address mapping command frame.

For example, the address mapping command frame may include the following fields:

A CommandID parameter for indicating the ID number of the address mapping command frame for matching the response frame;

an Operation parameter for indicating that the address mapping command frame is used for indicating the SoC720 to establish an address mapping relationship;

a RemapAddress parameter indicating the start address of a storage area opened in the DDR memory 713 by the X86 CPU711 (the start address is an address in the DDR address space);

the RemapSize parameter is used to indicate the address length corresponding to the memory region opened by the X86 CPU711 (the address length is the length in the DDR address space).

It should be understood that only four fields in the address map command frame are shown above. The address map command frame may also include fewer or more fields, as is practical.

(2) the X86 CPU711 writes an address mapping command frame into the PCIe receive command space in the PCIe module 722, and then sends an interrupt instruction to the MCU 721.

(3) the MCU721 obtains the address mapping command frame from the PCIe receive command space after receiving the interrupt command.

(4) The MCU721 parses the address mapping command frame, and establishes the mapping relationship between the DDR address space and the DDR address space according to the RemapAddress parameter, the RemapSize parameter, and the address conversion formula agreed by both parties.

for example, the MCU721 maps the start address in the DDR address space indicated by the RemapAddress parameter and the address length in the DDR address space indicated by the RemapSize parameter into the MCU address space.

The mapping may be stored in a register (e.g., ATU) of SoC 720.

(5) The MCU721 generates an address mapping response frame after completing the address mapping.

For example, the address mapping response frame may include: a CommandID parameter for indicating the ID number of the address mapping response frame to match the command frame; and processing the result parameters. The process result parameter may indicate, for example, a process success or an error code (when the process is unsuccessful). In this example, the processing result parameter may indicate that the address mapping was successful.

(6) The MCU721 writes the address mapping response frame in the PCIe reply command space and then sends an interrupt instruction to the X86 CPU 711.

(7) After receiving the interrupt command, the X86 CPU711 acquires the address mapping response frame from the PCIe reply command space.

After completing the address mapping, the X86 CPU711 may call the SoC720 for encryption processing. The specific procedure may be as follows.

(1) The X86 CPU711 can write plaintext data into the above-described storage area, and additionally generate an AES encrypted command frame. For example, the X86 CPU711 may carry the plaintext data to a location in the storage area through the DMA module 714.

For example, the AES encrypted command frame may include:

A CommandID parameter for indicating an ID number of the AES encrypted command frame to match a response frame;

an Operation parameter for indicating that the AES encryption command frame is used to instruct the SoC720 to perform an encryption function;

An Algorithm parameter indicating that the AES encryption command frame is to be used to indicate encryption using the AES Algorithm;

The DMAInAddress parameter is used to indicate the address where plaintext data is stored, which may be, for example, an address in the MCU address space. For example, the address where the plaintext data is stored in the DDR memory 713 is an SRC ADDR in the DDR address space, which may be denoted as DDR SRC for convenience of description. Thus, the DMAInAddress parameter may be the SRC ADDR in the MCU address space mapped with the DDR SRC, and for convenience of description, the SRC ADDR in the MCU address space may be denoted as MCU SRC;

A dmainddatalength parameter used to indicate the length of the plaintext data;

the DMAOutAddress parameter is used to indicate the address where the ciphertext is stored. The address may be, for example, an address in the MCU address space. For example, assuming that an address where ciphertext is to be stored is a DST ADDR in a DDR address space, the address may be represented as a DDR DST for convenience of description. The DMAOutAddress parameter may be a DST ADDR in the MCU address space mapped with the DDR DST, and for convenience of description, the DST ADDR in the MCU address space may be represented as an MCU DST;

DMAOutDataLength, which represents the length of the ciphertext;

An IV parameter (array) for representing an initial vector of the AES encryption algorithm,

a Key parameter (array) for representing a Key of an AES encryption algorithm,

A KeyLength parameter for indicating a key length of the AES encryption algorithm.

(2) the X86 CPU711 writes the AES encrypted command frame in the PCIe receive command space and then sends an interrupt instruction to the MCU 721.

(3) after receiving the interrupt command, the MCU721 obtains the AES encrypted command frame from the PCIe receive command space.

(4) The MCU721 invokes the DMA module 724 to obtain plaintext data from the storage area according to the DMAInAddress parameter and the DMAInDataLength parameter. Then, the MCU721 calls the RPU723 to encrypt the obtained plaintext data according to the Operation parameter, the Algorithm parameter, the IV parameter (array), the Key parameter (array), and the KeyLength parameter to obtain a ciphertext.

The MCU721 invokes the DMA module 724 to store the ciphertext to a corresponding location in the DDR memory 713 according to the DMAOutAddress parameter and the DMAOutDataLength parameter.

(5) The MCU721 generates an AES encrypted response frame.

For example, the AES encrypted response frame may include a CommandID parameter indicating the ID number of the AES encrypted response frame to use to match the command frame. The AES encrypted response frame may also include a processing result field. The processing result field may indicate, for example, a processing success or an error code. For example, in this example, the processing result field indicates that the encryption is successful.

(6) The MCU721 writes the AES encrypt response frame in the PCIe reply command space and then sends an interrupt instruction to the X86 CPU 711.

(7) After receiving the interrupt instruction, the X86 CPU711 acquires the AES encrypted response frame from the PCIe reply command space. Since in this example the processing result field in the AES encrypt response frame indicates that the encryption was successful, the X86 CPU711 may read the ciphertext from the DDR memory 713 according to the DDR DST mapped by the MCU DST in the AES encrypt response frame.

According to the embodiment of the disclosure, the X86 architecture can be simply and efficiently interacted with the SoC serving as the reconfigurable processing system, so that the X86 architecture can call the SoC to perform encryption and decryption processing, and the performance and efficiency of the encryption and decryption processing can be greatly improved. Moreover, due to the flexibility of the reconfigurable processing system, different cryptographic algorithms or combinations thereof can be implemented, thereby greatly enhancing security. Meanwhile, since the encryption and decryption tasks are offloaded from the X86 architecture to the SoC, the processing performance of the X86 architecture on other tasks can also be greatly improved.

Those skilled in the art will appreciate that various combinations and/or combinations of features recited in the various embodiments and/or claims of the present disclosure can be made, even if such combinations or combinations are not expressly recited in the present disclosure. In particular, various combinations and/or combinations of the features recited in the various embodiments and/or claims of the present disclosure may be made without departing from the spirit or teaching of the present disclosure. All such combinations and/or associations are within the scope of the present disclosure.

while the disclosure has been shown and described with reference to certain exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure as defined by the appended claims and their equivalents. Accordingly, the scope of the present disclosure should not be limited to the above-described embodiments, but should be defined not only by the appended claims, but also by equivalents thereof.

Claims

1. An information processing method applied to a first processor system, the first processor system being non-reconfigurable, the method comprising:

Generating a first command frame, wherein the first command frame comprises task information, the task information is used for instructing the reconfigurable processing system to execute a first task, and the first task is a data processing task;

Writing the first command frame into a peripheral component interconnect-express (PCIe) command space, the PCIe command space shared by the first processor system and the reconfigurable processing system;

Generating a second command frame, the second command frame including address space information indicating a first address space, wherein the first processing system uses the first address space to access a memory region;

Writing the second command frame into the PCIe command space so that the address space information is used by the reconfigurable processing system to establish a mapping relationship between the first address space and a virtual address space at the reconfigurable processing system;

Obtaining a second response frame from the reconfigurable processing system from the PCIe command space, wherein the second response frame indicates that the reconfigurable processing system successfully establishes the mapping relation;

Interacting task data associated with the first task with the reconfigurable processing system in the storage area, wherein the reconfigurable processing system is capable of accessing the storage area based on the mapping;

and obtaining a first response frame from the reconfigurable processing system from the PCIe command space, wherein the first response frame comprises return information which is used for indicating a result obtained by the reconfigurable processing system aiming at the first task.

2. the method of claim 1, wherein:

The task data comprises source data, and the first task comprises processing the source data;

The first command frame further includes source address information indicating a first source address or a second source address for storing the source data, the first source address being an address in the first address space, the second source address being an address in the virtual address space.

3. The method of claim 2, wherein the size of the source data is greater than a first threshold.

4. The method of claim 1, wherein:

The task data comprises target data, the first task comprises processing source data, and the target data is obtained by processing the source data by the reconfigurable processing system;

The first command frame or the first reply frame includes destination address information indicating a first destination address or a second destination address for storing the destination data, the first destination address being an address in the first address space, the second destination address being an address in the virtual address space.

5. the method of claim 4, wherein the size of the destination data is greater than a second threshold.

6. The method of any of claims 1-5, wherein:

After writing the first command frame in the PCIe command space, the method further comprises: sending a first interrupt instruction to the reconfigurable processing system, the first interrupt instruction indicating that the first command frame has been written into the PCIe command space; and/or

Prior to obtaining a first reply frame from the reconfigurable processing system from the PCIe command space, the method further comprises: receiving a second interrupt instruction from the reconfigurable processing system, the second interrupt instruction indicating that the first reply frame has been written into the PCIe command space.

7. An information processing method applied to a first processor system, the first processor system being non-reconfigurable, the method comprising:

Generating a first command frame, wherein the first command frame comprises task information and source data, the size of the source data is smaller than or equal to a first threshold, the task information is used for instructing a reconfigurable processing system to execute a first task, and the first task comprises processing the source data;

And obtaining a first response frame from the reconfigurable processing system from the PCIe command space, wherein the first response frame comprises return information and destination data, the destination data is obtained by processing the source data by the reconfigurable processing system, the size of the destination data is smaller than or equal to a second threshold, and the return information is used for indicating a result obtained by the reconfigurable processing system for the first task.

8. The method of claim 7, wherein:

9. An information processing method applied to a reconfigurable processing system, the method comprising:

Obtaining a first command frame from a first processor system from a peripheral component interconnect-express (PCIe) command space, the first command frame including task information instructing the reconfigurable processing system to execute a first task, the first task being a data processing task, the PCIe command space being shared by the first processor system and the reconfigurable processing system, the first processor system being non-reconfigurable;

Obtaining a second command frame from the PCIe command space, the second command frame including address space information indicating a first address space, wherein the first processing system uses the first address space to access a memory region;

Establishing a mapping relation between the first address space and a virtual address space at the reconfigurable processing system according to the address space information;

Generating a second response frame, and writing the second response frame into the PCIe command space, wherein the second response frame indicates that the reconfigurable processing system successfully establishes the mapping relationship;

Interacting task data associated with the first task with the first processor system in the memory area, wherein the reconfigurable processing system is capable of accessing the memory area based on the mapping;

Executing the first task to obtain return information, wherein the return information is used for indicating a result obtained by the reconfigurable processing system aiming at the first task;

Generating a first response frame, wherein the first response frame comprises the return information;

And writing the first response frame into the PCIe command space.

10. the method of claim 9, wherein:

The task data comprises source data, and the first task comprises processing the source data; the first command frame further includes source address information indicating a first source address or a second source address for storing the source data, the first source address being an address in the first address space, the second source address being an address in the virtual address space;

or:

The task data comprises target data, the first task comprises processing source data, and the target data is obtained by processing the source data by the reconfigurable processing system; the first command frame or the first reply frame includes destination address information indicating a first destination address or a second destination address for storing the destination data, the first destination address being an address in the first address space, the second destination address being an address in the virtual address space.

11. an information processing method applied to a reconfigurable processing system, the method comprising:

obtaining a first command frame from a first processor system from a peripheral component interconnect-express (PCIe) command space, the first command frame including task information and source data, the task information for instructing the reconfigurable processing system to perform a first task, the first task including processing the source data, the PCIe command space shared by the first processor system and the reconfigurable processing system, the first processor system being non-reconfigurable;

Executing the first task to obtain return information and destination data, wherein the destination data is obtained by processing the source data by the reconfigurable processing system, and the return information is used for indicating a result obtained by the reconfigurable processing system for the first task;

And generating a first response frame, and writing the first response frame into the PCIe command space, wherein the first response frame comprises the return information and the target data.

12. An information processing apparatus applied to a first processor system which is non-reconfigurable, the apparatus comprising:

The reconfigurable processing system comprises a first generation module, a second generation module and a processing module, wherein the first generation module is used for generating a first command frame, the first command frame comprises task information, and the task information is used for instructing the reconfigurable processing system to execute a first task, and the first task is a data processing task;

a first write module to write the first command frame into a peripheral component interconnect-express (PCIe) command space, the PCIe command space shared by the first processor system and the reconfigurable processing system;

A second generating module, configured to generate a second command frame, where the second command frame includes address space information indicating a first address space, and where the first processing system uses the first address space to access a storage area;

a second writing module, configured to write the second command frame into the PCIe command space, so that the address space information is used by the reconfigurable processing system to establish a mapping relationship between the first address space and a virtual address space at the reconfigurable processing system;

a second obtaining module, configured to obtain a second response frame from the reconfigurable processing system from the PCIe command space, where the second response frame indicates that the reconfigurable processing system successfully establishes the mapping relationship;

A first interaction module, configured to interact task data associated with the first task with the reconfigurable processing system in the storage area, wherein the reconfigurable processing system is capable of accessing the storage area based on the mapping relationship;

The first obtaining module is configured to obtain a first response frame from the reconfigurable processing system from the PCIe command space, where the first response frame includes return information, and the return information is used to indicate a result obtained by the reconfigurable processing system for the first task.

13. The apparatus of claim 12, wherein:

Or:

14. An information processing apparatus applied to a first processor system which is non-reconfigurable, the apparatus comprising:

The reconfigurable processing system comprises a first generation module, a second generation module and a processing module, wherein the first generation module is used for generating a first command frame, the first command frame comprises task information and source data, the task information is used for instructing the reconfigurable processing system to execute a first task, and the first task comprises processing the source data;

The first obtaining module is configured to obtain a first response frame from the reconfigurable processing system from the PCIe command space, where the first response frame includes return information and destination data, the destination data is obtained by processing the source data by the reconfigurable processing system, and the return information is used to indicate a result obtained by the reconfigurable processing system for the first task.

15. An information processing apparatus applied to a reconfigurable processing system, the apparatus comprising:

A third obtaining module, configured to obtain a first command frame from a first processor system from a peripheral component interconnect-express PCIe command space, where the first command frame includes task information, where the task information is used to instruct the reconfigurable processing system to execute a first task, the first task is a data processing task, and the PCIe command space is shared by the first processor system and the reconfigurable processing system;

A fourth obtaining module, configured to obtain a second command frame from the PCIe command space, where the second command frame includes address space information, and the address space information is used to indicate a first address space, where the first processor system uses the first address space to access an inter-access storage area;

The address establishing module is used for establishing a mapping relation between the first address space and a virtual address space at the reconfigurable processing system according to the address space information;

A fourth generating module, configured to generate a second response frame, where the second response frame indicates that the mapping relationship is successfully established;

A fourth writing module, configured to write the second response frame into the PCIe command space;

A second interaction module for interacting with the first processor system task data associated with the first task, wherein the reconfigurable processing system is capable of accessing the memory regions based on the mapping;

the execution module is used for executing the first task to obtain return information, and the return information is used for indicating a result obtained by the reconfigurable processing system aiming at the first task;

a third generating module, configured to generate a first response frame, where the first response frame includes the return information;

And the third writing module is used for writing the first response frame into the PCIe command space.

16. The apparatus of claim 15, wherein:

Or:

17. An information processing apparatus applied to a reconfigurable processing system, the apparatus comprising:

A third obtaining module, configured to obtain a first command frame from a first processor system from a peripheral component interconnect-express PCIe command space, where the first command frame includes task information and source data, the task information is used to instruct the reconfigurable processing system to execute a first task, the first task includes processing the source data, and the PCIe command space is shared by the first processor system and the reconfigurable processing system;

The execution module is used for executing the first task to obtain return information and target data, the target data is obtained by processing the source data by the reconfigurable processing system, and the return information is used for indicating a result obtained by the reconfigurable processing system aiming at the first task;

a third generating module, configured to generate a first response frame, where the first response frame includes the return information and the destination data;