CN107562410A - The harvester and acquisition method of true random number - Google Patents
The harvester and acquisition method of true random number Download PDFInfo
- Publication number
- CN107562410A CN107562410A CN201710756289.3A CN201710756289A CN107562410A CN 107562410 A CN107562410 A CN 107562410A CN 201710756289 A CN201710756289 A CN 201710756289A CN 107562410 A CN107562410 A CN 107562410A
- Authority
- CN
- China
- Prior art keywords
- random number
- generating circuit
- voltage
- true random
- control device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
The present invention provides a kind of acquisition system and acquisition method of true random number, the acquisition system includes generating means, control device and harvester, the generating means include random signal generating circuit and the comparator being connected with the output end of the random signal generating circuit, the random signal generating circuit includes diode, and the material of the diode is superlattice semiconductor material；Output digit signals are to the control device after the comparator is used for the size of the magnitude of voltage of the output end of the random signal generating circuit and the magnitude of voltage of reference voltage；The control device is used to the data signal being converted to true random number；The harvester is used to be acquired the true random number.Whole generating means have high bandwidth, fireballing feature, can ensure to ensure the stability of true random number while high efficiency generates true random number.
Description
Technical field
The present invention relates to random number generation technology field, more particularly to a kind of harvester of true random number and collection side
Method.
Background technology
The popularization and evolution of communication network allow people to change the mode of information communication, and in the process promoted IT application
In with a variety of social and economic activities have very close association.On the one hand this association brings huge social value and warp
Ji value, on the other hand also implies that huge potential danger, once there is security incident in communication network, it is possible to makes thousands of
There is obstacle in communication between people up to ten thousand, brings the unforeseen loss of social value and economic value.True random number is being protected
There is very important application in the fields such as close communication, information security, authentication, cipher protocol, digital signature.Relative to puppet with
Machine number, true random number can not be predicted, do not reproduce, and therefore, true random number is capable of the transmission of preferably protection information.It is however, existing
The performance for the random number that the speed of random number caused by some random number chips is slow, obtains is unstable.Therefore, it is necessary to carry
For it is a kind of can either efficiently generate true random number sequence while and can enough ensure generation true random number sequence stabilization
Property.
The content of the invention
In order to solve the above problems, the present invention proposes a kind of harvester and acquisition method of true random number, can be in height
Efficiency ensures the stability of true random number while generating true random number.
Concrete technical scheme proposed by the present invention is：A kind of acquisition system of true random number, the acquisition system bag are provided
Generating means, control device and harvester are included, the generating means include random signal generating circuit and believed at random with described
The comparator of the output end connection of number generation circuit, the random signal generating circuit include diode, the material of the diode
Matter is superlattice semiconductor material；
The comparator is used for the magnitude of voltage of output end and the electricity of reference voltage of the random signal generating circuit
Output digit signals are to the control device after the size of pressure value；
The control device is used to the data signal being converted to true random number；
The harvester is used to be acquired the true random number.
Further, the random signal generating circuit also includes voltage source, pull-up resistor, electric capacity and pull down resistor, institute
State pull-up resistor to be connected with the voltage source, the diode is connected with the output end of the pull-up resistor, the diode warp
It is grounded by the pull down resistor, output end and the random signal generating circuit of the capacitance connection in the pull-up resistor
Between output end.
Further, the control device includes processor and adjuster, and the processor is used to detect the numeral letter
Number whether it is random signal and the data signal is converted into true random number when the data signal is random signal, it is described
Adjuster is used for the voltage that the voltage source is adjusted when the data signal is not random signal.
Further, the processor is connected by PCIE interfaces with the harvester.
Further, the processor detects whether the data signal is random signal by machine learning algorithm.
Further, the processor passes through linear feedback shift register algorithm (Linear Feedback Shift
Register, LFSR) data signal is converted into true random number.
Further, the processor is fpga chip.
Further, the adjuster is MCU chip.
Present invention also offers a kind of acquisition method of true random number, the acquisition method includes：
After comparator compares the size of the magnitude of voltage of the output end of random signal generating circuit and the magnitude of voltage of reference voltage
Output digit signals are to control device, and the random signal generating circuit includes diode, and the material of the diode is super brilliant
Lattice semiconductor material；
The data signal is converted to true random number by the control device；
Harvester is acquired to the true random number.
The acquisition system of true random number provided by the invention includes generating means, control device and harvester, the life
Include random signal generating circuit and comparator into device, the random signal generating circuit includes diode, the diode
Material be superlattice semiconductor material；So as to which the signal of the output end output of the random signal generating circuit is believed for chaos
Number so that whole generating means have high bandwidth, fireballing feature, can ensure whole acquisition system high efficiency generation very with
Ensure the stability of true random number while machine number.
Brief description of the drawings
The following description carried out in conjunction with the accompanying drawings, above and other aspect, feature and the advantage of embodiments of the invention
It will become clearer, in accompanying drawing：
Fig. 1 is the schematic diagram of the acquisition system of true random number；
Fig. 2 is another schematic diagram of the acquisition system of true random number；
Fig. 3 is the schematic diagram that LFSR algorithms are realized by FPGA；
Fig. 4 is the flow chart of the acquisition method of true random number.
Embodiment
Hereinafter, with reference to the accompanying drawings to embodiments of the invention are described in detail.However, it is possible to come in many different forms real
Apply the present invention, and the specific embodiment of the invention that should not be construed as limited to illustrate here.Conversely, there is provided these implementations
Example is in order to explain the principle and its practical application of the present invention, so that others skilled in the art are it will be appreciated that the present invention
Various embodiments and be suitable for the various modifications of specific intended application.
Referring to Figures 1 and 2, the acquisition system for the true random number that the present embodiment provides includes generating means 1, control device 2
And harvester 3, generating means 1 include random signal generating circuit 11 and the output end V with random signal generating circuit 11o1Even
The comparator 12 connect.
Generating means 1 also include circuit board (not shown), and random signal generating circuit 11 is integrated on the circuit board.With
Machine signal generating circuit 11 includes diode 110, and diode 110 is fixed on circuit boards by fixed pedestal (not shown).Its
In, the material of diode 110 is superlattice semiconductor material, because the diode 110 of superlattice semiconductor material is according to electronics
Resonance tunnel-through principle can produce chaotic signal in the presence of bias voltage, and to be that one kind can show similar for chaotic signal
The signal of random character, it have random signal relatively common-path interference and it is difficult intercept and capture property, therefore, by by diode 110
Material, which elects superlattice semiconductor material as, can cause the output end V of random signal generating circuit 11o1The signal of output is chaos
Signal.
Comparator 12 is used for the output end V for comparing random signal generating circuit 11o1The magnitude of voltage of the chaotic signal of output with
To control device 2, control device 2 is used to turn the data signal output digit signals after the size of the magnitude of voltage of reference voltage
True random number is changed to, harvester 3 is used to be acquired the true random number.
The in-phase input end connection reference voltage source V of comparator 121, reference voltage source V1For the same phase for comparator 12
Input provides reference voltage, the output end V of the inverting input connection random signal generating circuit 11 of comparator 12o1, compare
The output end connection control device 2 of device 12.In other embodiments, the in-phase input end of comparator 12 can also connect periphery
Circuit, it is that comparator 12 provides driving voltage and reference voltage by peripheral circuit.
Output end V of the comparator 12 in random signal generating circuit 11o1Magnitude of voltage be less than the magnitude of voltage of reference voltage
1 is exported during size, output end V of the comparator 12 in random signal generating circuit 11o1Magnitude of voltage be more than reference voltage voltage
0 is exported during the size of value, so, the output end V of random signal generating circuit 11 is compared by comparator 12o1Magnitude of voltage and ginseng
Examining after the size of the magnitude of voltage of voltage can be to produce one by 0,1 digital signal sequences formed.
Specifically, random signal generating circuit 11 also includes voltage source 111, pull-up resistor 112, electric capacity 113 and drop-down electricity
Resistance 114.Pull-up resistor 112 is connected with voltage source 111, the output end V of diode 110 and pull-up resistor 112o2Connection, diode
110 are grounded via pull down resistor 114, and electric capacity 113 is connected to the output end V of pull-up resistor 112o2With random signal generating circuit 11
Output end Vo1Between.
Control device 2 includes processor 21 and adjuster 22, and processor 21 is used to detect whether data signal is to believe at random
Number and the data signal is converted into true random number when data signal is random signal, adjuster 22 is used in the numeral
The voltage that voltage source 111 is adjusted when signal is not random signal adjusts the bias voltage of diode 110.
Processor 21 in the present embodiment is fpga chip, and the bandwidth of generating means 1 is from hundreds of MHz magnitudes to several GHz amounts
Level, therefore, it is necessary to control device 2 and harvester 3 have high-speed data processing and transmittability.Wherein, processor 21 uses
Xilinx virtex6 sequence fpga chips, it has the characteristics of Low Power High Performance, and dominant frequency reaches 600MHz, chip internal
With PCIE stones.From virtex6 sequence fpga chips, on the one hand, can effectively meet the high-speed data of generating means 1
Processing needs, and on the other hand, the high-speed data acquisition function based on PCIE interfaces is realized using built-in PCIE stones.Here, locate
Reason device 21 is connected by PCIE interfaces with harvester 3, can overcome pci interface using serial point-to-point PCIE interface protocols
The system bandwidth, transmission speed etc. the defects of.
Processor 21 detects whether the data signal is random signal by machine learning algorithm, the machine in the present embodiment
Device learning algorithm is using SVM algorithm of support vector machine, and here, robot learning algorithm can also be selected known in the art
Other robot algorithm, for example, decision tree, random forests algorithm, naive Bayesian, K nearest neighbor algorithms, neutral net etc.,
Here do not limit.
The data signal is converted to true random number by processor 21 by LFSR algorithms.LFSR algorithms are by two parts group
Into：Shift register and feedback function.Shift register is a bit sequence, and being deposited in each position of the bit sequence has number
According to when generating a new data every time, the data of all in shift register all move to right one, and the data of removal are just shifting
The output of bit register, the leftmost bit vacated are used to store the new data, and the new data is entered by feedback function to other all positions
Row computing and obtain, wherein, feedback function is linear function.
Wherein, the proper polynomial of the LFSR algorithms in this implementation example is：
F (x)=x128+x7+x2+x+1
Or
F (x)=x128+x127+x126+x121+1
LFSR algorithms by the FPGA schematic diagrams realized as shown in figure 3, the LFSR algorithms in the present embodiment be 128 grades, its
DFF (d type flip flop) is directly based upon to realize, i.e. 128 DFF are front and rear to be cascaded, according to features described above multinomial by 120 grades, 125
Level, 126 grades, export the DFF for feeding back to most prime after 127 grades of XORs.
Because comparator 12 is influenceed the numeral that (such as null offset, shake) cause output sometimes by its physical characteristic
Occur abnormal continuous 0 or continuous 1 in signal sequence.Can effectively solve this problem by LFSR algorithms.Comparator
Data signal caused by 12 is constantly changing the input value of LFSR algorithms, can be to obtain the random of high quality by LFSR algorithms
Number Sequence, because the input value of LFSR algorithms is unpredictable, then the random number sequence of output is also unpredictable certainly
I.e. processor 21 export be true random number sequence.
Adjuster 22 in the present embodiment is MCU chip, detects that the data signal is not to believe at random in processor 21
Number when, processor 21 can send control signal to adjuster 22, and adjuster 22 adjusts voltage source 111 according to the control signal
Voltage is the bias voltage for adjusting diode 110 so that the output end V of random signal generating circuit 11o1Output is believed for chaos
Number.
Harvester 3 can be computer or other human-computer interaction devices, and it is used to be acquired true random number and look into
See the quality for the true random number that the speed of gathered data, test collect.
Reference picture 4, the present embodiment additionally provide a kind of acquisition method of true random number, and the acquisition method includes step：
S1, comparator 12 compare the output end V of random signal generating circuit 11o1Magnitude of voltage and reference voltage magnitude of voltage
Size after output digit signals to control device.
Before step S1, harvester 3 is first opened, harvester 3 is that control device 2 is powered, now, control device 2
Establish and communicate between harvester 3.Then, harvester 3 sends data acquisition instructions and opened to control device 2, control device 2
Beginning receives the output end V of random signal generating circuit 11o1The data signal of output.
The data signal is converted to true random number by S2, control device 2.
In step s 2, first pass through processor 21 and detect whether data signal is random signal and is random in data signal
The data signal is converted into true random number during signal；If the data signal is not random signal, processor 21 is sent
For control signal to adjuster 22, the voltage that adjuster 22 adjusts voltage source 111 according to control signal is the inclined of regulation diode 110
Put voltage so that the output end V of random signal generating circuit 11o1Even if output for chaotic signal data signal be to believe at random
Number.
S3, harvester 3 are acquired to the true random number.
By electing the material of diode 110 as superlattice semiconductor material in the present embodiment so that generating means 1 have
Bandwidth is high, fireballing feature.The data signal is converted to true random number by processor 21 by LFSR algorithms, improves life
The quality of the random number generated into device 1.Processor 21 is connected and communicated with harvester 3 by PCIE interfaces, is overcome
Pci interface is the system bandwidth, transmission speed etc. the defects of.
It should be noted that in this manual, term " comprising ", "comprising" or its any other variant are intended to
Nonexcludability includes, so that process, method, article or equipment including a series of elements not only will including those
Element, but also the other element including being not expressly set out, or it is this process, method, article or equipment also to include
Intrinsic key element.
Described above is only the embodiment of the application, it is noted that for the ordinary skill people of the art
For member, on the premise of the application principle is not departed from, some improvements and modifications can also be made, these improvements and modifications also should
It is considered as the protection domain of the application.
Claims (9)
1. a kind of acquisition system of true random number, it is characterised in that described including generating means, control device and harvester
Generating means include random signal generating circuit and the comparator being connected with the output end of the random signal generating circuit, described
Random signal generating circuit includes diode, and the material of the diode is superlattice semiconductor material；
The comparator is used for the magnitude of voltage of output end and the magnitude of voltage of reference voltage of the random signal generating circuit
Size after output digit signals to the control device；
The control device is used to the data signal being converted to true random number；
The harvester is used to be acquired the true random number.
2. acquisition system according to claim 1, it is characterised in that the random signal generating circuit also includes voltage
Source, pull-up resistor, electric capacity and pull down resistor, the pull-up resistor are connected with the voltage source, the diode and the pull-up
The output end connection of resistance, the diode are grounded via the pull down resistor, and the capacitance connection is in the pull-up resistor
Between output end and the output end of the random signal generating circuit.
3. acquisition system according to claim 2, it is characterised in that the control device includes processor and adjuster,
The processor be used for detect the data signal whether be random signal and when the data signal is random signal by institute
State data signal and be converted to true random number, the adjuster is used to adjust the electricity when the data signal is not random signal
The voltage of potential source.
4. acquisition system according to claim 3, it is characterised in that the processor passes through PCIE interfaces and the collection
Device connects.
5. acquisition system according to claim 3, it is characterised in that the processor detects institute by machine learning algorithm
State whether data signal is random signal.
6. acquisition system according to claim 3, it is characterised in that the processor passes through linear feedback shift register
The data signal is converted to true random number by algorithm.
7. acquisition system according to claim 3, it is characterised in that the processor is fpga chip.
8. acquisition system according to claim 3, it is characterised in that the adjuster is MCU chip.
A kind of 9. acquisition method of true random number, it is characterised in that including：
Comparator exports after comparing the size of the magnitude of voltage of the output end of random signal generating circuit and the magnitude of voltage of reference voltage
Data signal is to control device, and the random signal generating circuit includes diode, and the material of the diode is superlattices half
Conductive material；
The data signal is converted to true random number by the control device；
Harvester is acquired to the true random number.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710756289.3A CN107562410A (en) | 2017-08-29 | 2017-08-29 | The harvester and acquisition method of true random number |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710756289.3A CN107562410A (en) | 2017-08-29 | 2017-08-29 | The harvester and acquisition method of true random number |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107562410A true CN107562410A (en) | 2018-01-09 |
Family
ID=60976129
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710756289.3A Pending CN107562410A (en) | 2017-08-29 | 2017-08-29 | The harvester and acquisition method of true random number |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107562410A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110286878A (en) * | 2019-06-25 | 2019-09-27 | 电子科技大学 | The true Random Number Generator and production method of MCU random interval conversion bridge voltage |
| RU199488U1 (en) * | 2020-02-21 | 2020-09-03 | Общество с ограниченной ответственностью Фирма "Анкад" | Device for obtaining sequences of random binary numbers |
| CN111651085A (en) * | 2020-06-01 | 2020-09-11 | 上海爱信诺航芯电子科技有限公司 | Self-capacitance detection scanning circuit |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060161758A1 (en) * | 2005-01-14 | 2006-07-20 | International Business Machines Corporation | Multiple page size address translation incorporating page size prediction |
| CN201654763U (en) * | 2010-05-21 | 2010-11-24 | 房慧龙 | Bit stream generator of true random |
-
2017
- 2017-08-29 CN CN201710756289.3A patent/CN107562410A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060161758A1 (en) * | 2005-01-14 | 2006-07-20 | International Business Machines Corporation | Multiple page size address translation incorporating page size prediction |
| CN201654763U (en) * | 2010-05-21 | 2010-11-24 | 房慧龙 | Bit stream generator of true random |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110286878A (en) * | 2019-06-25 | 2019-09-27 | 电子科技大学 | The true Random Number Generator and production method of MCU random interval conversion bridge voltage |
| WO2020259721A3 (en) * | 2019-06-25 | 2021-02-18 | 电子科技大学 | Truly random number generator and truly random number generation method for conversion of bridge voltage at random intervals in mcu |
| RU199488U1 (en) * | 2020-02-21 | 2020-09-03 | Общество с ограниченной ответственностью Фирма "Анкад" | Device for obtaining sequences of random binary numbers |
| CN111651085A (en) * | 2020-06-01 | 2020-09-11 | 上海爱信诺航芯电子科技有限公司 | Self-capacitance detection scanning circuit |
| CN111651085B (en) * | 2020-06-01 | 2022-09-27 | 上海爱信诺航芯电子科技有限公司 | Self-capacitance detection scanning circuit |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107562410A (en) | The harvester and acquisition method of true random number | |
| CN103168424B (en) | For changing the technology of periodic signal based on the change of data rate | |
| US8738675B2 (en) | Random numbers generation using continuous-time chaos | |
| US7961830B2 (en) | Clock and data recovery circuit having wide phase margin | |
| US6240432B1 (en) | Enhanced random number generator | |
| US8102904B2 (en) | Methods and systems for data rate detection for multi-speed embedded clock serial receivers | |
| US8612501B2 (en) | Method and hardware for generating random numbers using dual oscillator architecture and continuous-time chaos | |
| CN106293616B (en) | True Random Number Generator based on time delay feedback oscillator | |
| Zidan et al. | Controllable V-shape multiscroll butterfly attractor: system and circuit implementation | |
| US10224937B1 (en) | Clock and data recovery circuit having tunable fractional-N phase locked loop | |
| CN109167664B (en) | Reconfigurable ring oscillator PUF circuit based on exclusive-OR gate | |
| WO2020055744A1 (en) | Frequency/phase lock detector for clock and data recovery circuits | |
| CN111490757B (en) | Random number generation electronic circuit and method | |
| Choi et al. | A 0.65-to-10.5 Gb/s reference-less CDR with asynchronous baud-rate sampling for frequency acquisition and adaptive equalization | |
| CN113672199B (en) | Multi-entropy source random number generator with physical unclonable function | |
| CN107392057A (en) | A kind of unclonable circuit structure of physics | |
| WO2021232255A1 (en) | True random number generator and electronic device | |
| CN1446345A (en) | Data processing arrangement comprising confidential data | |
| Garcia-Bosque et al. | FPGA implementation of a new PUF based on Galois ring oscillators | |
| CN103297296A (en) | FPGA-based logical operation search method and system | |
| Sajal et al. | Concealable physically unclonable functions and key generation using a Geiger mode imager | |
| Wu et al. | High throughput design and implementation of SHA-3 hash algorithm | |
| Kumar et al. | METAPUF: A challenge response pair generator | |
| Mahalat et al. | Design of latch based configurable ring oscillator puf targeting secure fpga | |
| US20160006519A1 (en) | Quantum Transceiver |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| TA01 | Transfer of patent application right | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20180419 Address after: 215123 Suzhou Industrial Park, Jiangsu Province, if the waterway No. 398, No. Applicant after: Suzhou Institute of Nano-Tech and Bionics (SINANO), Chinese Academy of Sciences Applicant after: University of Chinese Academy of Sciences Address before: 215123 Suzhou Industrial Park, Jiangsu Province, if the waterway No. 398, No. Applicant before: Suzhou Institute of Nano-Tech and Bionics (SINANO), Chinese Academy of Sciences |
|
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20180109 |