CN107544917A - A kind of storage resource sharing method and device - Google Patents
A kind of storage resource sharing method and device Download PDFInfo
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- CN107544917A CN107544917A CN201610474784.0A CN201610474784A CN107544917A CN 107544917 A CN107544917 A CN 107544917A CN 201610474784 A CN201610474784 A CN 201610474784A CN 107544917 A CN107544917 A CN 107544917A
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- 238000001514 detection method Methods 0.000 claims abstract description 63
- 238000007599 discharging Methods 0.000 claims description 3
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- 238000010586 diagram Methods 0.000 description 4
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
Abstract
The invention discloses a kind of storage resource sharing method, including：Whether the memory cell of detection port will overflow, if so, then the shared memory cell level being not used by is associated in behind the afterbody memory cell of the port.The present invention further simultaneously discloses a kind of storage resource sharing means.
Description
Technical field
The present invention relates to storage resource technology of sharing, more particularly to a kind of storage resource sharing method and device.
Background technology
In the prior art, to field programmable gate array (Field-Programmable Gate Array, FPGA) chip
Port in the data message that is transmitted carry out caching process method mainly include it is following two：One kind is by port point
Storage resource with fixed size caches to data message, and the storage resource of the distribution can make port run into data
Message will not overflow when happening suddenly；Another kind is that whole storage resource and port are concentrated by using array dispatching method
Management, so as to be cached to data message, this method can ensure port when carrying out caching process to data message, there is provided
Storage resource required for port, but whole storage resource and each port are required for safeguarding the dispatch list of respective complexity,
And need that there is larger register transfer level circuit (Register Transport Level, RTL) resource.
However, storage resource and the size of RTL resources that each fpga chip is included are fixed.If to each
The storage resource of port assignment fixed size, because the storage resource size required for each port is inconsistent, this can drop
The utilization rate of low storage resource and it is simple expand required storage resource, once required storage resource has exceeded this
The maximum of the intrinsic storage resource of model fpga chip, it may be desirable to which there is the fpga chip of bigger storage resource could meet to want
Ask；Use is scheduled to storage resource according to array dispatching method, by the size for the RTL resources that fpga chip is included
Be it is fixed, then it is simple to expand required RTL resources, once required RTL resources have exceeded model FPGA cores
The maximum of the intrinsic RTL resources of piece, it equally may require that the fpga chip with bigger RTL resources could meet to require.
The content of the invention
In view of this, the embodiment of the present invention it is expected to provide a kind of storage resource sharing method and device, disclosure satisfy that port
To the demand of storage resource, and improve utilization ratio of storage resources.
To reach above-mentioned purpose, the technical proposal of the invention is realized in this way：
The invention provides a kind of storage resource sharing method, methods described includes：
Whether the memory cell of detection port will overflow, if so, being then associated in the shared memory cell level being not used by
Behind the afterbody memory cell of the port.
Further, the afterbody memory cell that the shared memory cell level being not used by is associated in the port
Behind before, methods described also includes：
Detect whether the shared memory cell being not used by be present, if in the presence of by the shared storage being not used by
Unit distributes to the port.
Further, methods described also includes：
It is whether idle and whether be shared memory cell to detect the afterbody memory cell of the port, if the port
Afterbody memory cell it is idle and be shared memory cell, then discharge the afterbody memory cell of the port.
Further, methods described also includes：
When detecting to be not present the shared memory cell being not used by, the port lower than the priority of the port is discharged
Afterbody memory cell, and the afterbody memory cell that the low port of the priority than the port is discharged
Distribute to the port；The afterbody memory cell of the low port of the priority than the port is that shared storage is single
Member.
Further, methods described also includes：
When the afterbody memory cell for detecting the port is idle and after be shared memory cell, detects the end
Whether the penultimate stage memory cell of mouth will overflow, if it is not, then discharging the afterbody memory cell of the port.
The embodiment of the present invention additionally provides a kind of storage resource sharing means, and described device includes：Detection module, processing mould
Block；Wherein,
Whether the detection module, the memory cell for detecting port will overflow；
The processing module, will when the memory cell for detecting the port when the detection module will overflow
The shared memory cell level being not used by is associated in behind the afterbody memory cell of the port.
Further,
The detection module, it is additionally operable to detect whether the shared memory cell being not used by be present；
The processing module, it is additionally operable to when the detection module detects to exist the shared memory cell being not used by,
The shared memory cell being not used by is distributed into the port.
Further,
The detection module, it is additionally operable to when the shared memory cell level being not used by is associated in the end by the processing module
Mouthful afterbody memory cell below after, detect the port afterbody memory cell whether free time and whether be
Shared memory cell；
The processing module, it is additionally operable to when the detection module detects that the afterbody memory cell of the port is idle
And when being shared memory cell, discharge the afterbody memory cell of the port.
Further,
The processing module, it is additionally operable to when the detection module detects that the shared memory cell being not used by is not present
When, discharge the afterbody memory cell of the port lower than the priority of the port；The priority than the port is low
The afterbody memory cell of port be shared memory cell；
The processing module, it is additionally operable to deposit the afterbody that the low port of the priority than the port is discharged
Storage unit distributes to the port.
Further,
The detection module, it is additionally operable to when the afterbody memory cell for detecting the port is idle and is stored to be shared
Whether after unit, detecting the penultimate stage memory cell of the port will overflow；
The processing module, it is additionally operable to when the detection module detects the penultimate stage memory cell of the port not
When can overflow, the afterbody memory cell of the port is discharged.
Whether storage resource sharing method provided in an embodiment of the present invention and device, detecting the memory cell of port will overflow
Go out, if so, then the shared memory cell level being not used by is associated in behind the afterbody memory cell of the port；Such as
This, in the storage resource deficiency needed for port, distributes storage resource to the port, meets port to storage resource in time
Demand, so that it is guaranteed that port normally can be handled data message.
In addition, whether the afterbody memory cell of detection port is idle and be shared memory cell, if the end
The afterbody memory cell of mouth is idle and is shared memory cell, then discharges the afterbody memory cell of the port；Such as
This, when detection exit port no longer needs allocated shared memory cell, discharges the shared memory cell, it is ensured that every in time
The service efficiency of individual shared memory cell maximizes, so as to improve utilization ratio of storage resources.
Brief description of the drawings
Fig. 1 is the implementation process schematic diagram of the storage resource sharing method of the embodiment of the present invention one；
Fig. 2 is the implementation process schematic diagram of the storage resource sharing method of the embodiment of the present invention two；
Fig. 3 is the composition structural representation of storage resource sharing means of the embodiment of the present invention.
Embodiment
Embodiment one
A kind of implementation process schematic diagram of storage resource sharing method of the embodiment of the present invention one, as shown in figure 1, including：
Step 101：Whether the memory cell of detection port will overflow；
Generally, due to the storage resource that fpga chip inside is included all be by multiple random storage blocks (Block RAM,
BRAM) formed, and BRAM is typically sized to 18KB or 36KB.After fpga chip startup, first by FPGA cores
Storage resource inside piece is divided into a number of memory cell, and each memory cell includes a number of BRAM；Then,
A part of memory cell in whole memory cell is distributed into each port inside fpga chip, and makes to distribute to identical
The memory cell of port cascades up respectively, and remaining memory cell is used for follow-up dynamically distributes.
Here, it is necessary to explanation, the memory cell is to represent a kind of storage resource, each memory cell by one or
More than one BRAM is formed；The BRAM quantity that each memory cell is included be able to can also be differed with identical, i.e., each storage
The size of unit may be identical, it is also possible to differs；The number of memory cells that each port is obtained can be with identical, can also not
Identical, i.e., the storage resource that each port is obtained may be identical, it is also possible to differs；The port can be multiple specific
Physical port or multiple different subports, or multiple queues in some port；For to distributing to port
Memory cell makes a distinction with the remaining memory cell, and the memory cell that port is distributed to described in mark is fixed storage list
Member, and it is shared memory cell to identify the remaining memory cell.
Specifically, fpga chip detects to the working condition of port in the course of the work, if detection exit port is deposited
Storage unit will overflow, then demonstrate the need for reallocating shared memory cell for the port so that the port disclosure satisfy that pair
Data message carries out the needs of caching process, that is, performs step 102；If the memory cell of detection exit port will not overflow, after
It is continuous to perform step 101.
Here, whether the memory cell of the detection port will overflow, and can be the afterbody storage for detecting port
Removing most for port will be overflowed or be detected to the penultimate stage memory cell whether unit will overflow or detect port whether
Whether the memory cell outside rear stage memory cell and penultimate stage memory cell will overflow, with inspection in the present embodiment
Whether the afterbody memory cell of survey port illustrates exemplified by will overflowing；The afterbody memory cell of the port is
Static memory cell or shared memory cell, i.e., non-level is associated with shared memory cell behind the static memory cell of the port
When, the afterbody memory cell of the port is static memory cell；Cascaded behind the static memory cell of the port
When having shared memory cell, the afterbody memory cell of the port is shared memory cell.
Step 102：If so, the afterbody that the shared memory cell level being not used by then is associated in the port stores list
Behind member.
Specifically, when the memory cell for detecting exit port in step 101 will overflow, i.e., detect to hold in the present embodiment
When the afterbody memory cell of mouth will overflow, the shared memory cell level being not used by is associated in last of the port
Behind level memory cell, meet that the port carries out the needs of caching process to data message.
Here, the shared memory cell being not used by refers to that the shared memory cell is any currently without being assigned to
Port uses；Situation is needed to storage resource according to the port, can be not used by one or more shared deposits
Storage unit level is associated in behind the afterbody memory cell of the port；It is described to cascade the shared memory cell being not used by
After behind the afterbody memory cell of the port, the afterbody memory cell of the port is shared storage
Unit.
Further, before step 102, methods described also includes：Detect whether the shared storage being not used by be present
Unit, if in the presence of the shared memory cell being not used by is distributed into the port.
Specifically, when in step 101 detect exit port memory cell will overflow when, detect whether exist be not used by
Shared memory cell, if in the presence of the shared memory cell being not used by is distributed into the port.
Here, if the shared memory cell for detecting to be not used by has multiple, can by any one or more than one not
The shared memory cell used distributes to the port；If the afterbody of all of the port included inside fpga chip is deposited
Storage unit did not all occur detecting the situation that will be overflowed, then was stored in the afterbody for detecting some port for the first time
When unit will overflow, it can not have to detect whether the shared memory cell being not used by be present.
Here, can also be according to each port of setting if detecting that the shared memory cell being not used by is not present
Priority, discharges the afterbody memory cell of the port lower than the priority of the port, and by described than the port
The afterbody memory cell that the low port of priority is discharged distributes to the port；The priority than the port is low
The afterbody memory cell of port be shared memory cell.
Here, the priority of the port is that user is running into situations such as data message happens suddenly to solve port, causes sky
Not busy shared memory cell has been allocated, and needs preferential ensure set by certain port acquisition shared memory cell；If
The priority that port described in the priority ratio of multiple ports be present is low and the afterbody memory cell of the multiple port is all
Shared memory cell, then the afterbody memory cell of the port in the multiple port with lowest priority can be released
Put or discharge the afterbody memory cell of any one port in the multiple port.
Further, methods described also includes：Whether whether the afterbody memory cell of detection port is idle and be altogether
Memory cell is enjoyed, if the afterbody memory cell is idle and is shared memory cell, discharges the port last
Level memory cell.
Specifically, if the afterbody storage list of the afterbody memory cell free time of detection exit port and the port
When member is shared memory cell, the afterbody memory cell of the port is discharged；If detect the afterbody storage of exit port
Unit is not idle, then does not discharge the afterbody memory cell of the port.
Here, the memory cell free time refers to that the memory cell is current not to data message progress caching process, or not
It is cached with data message；If the afterbody memory cell of port is idle, be relative to the port it is idle, unnecessary,
The afterbody memory cell of the releasable port, make that the state of the memory cell is changed into being not used by again shared deposits
Storage unit.
Here, in order to avoid producing, frequently scheduling operation, methods described also include：Detect the second from the bottom of the port
Whether level memory cell will overflow, if it is not, the afterbody memory cell of the port is then discharged, otherwise without operation.
Specifically, if detecting the afterbody memory cell free time of the port and penultimate stage memory cell general
When overflowing, the afterbody memory cell of the port is not discharged；If detect the afterbody memory cell of the port
When idle and penultimate stage memory cell will not overflow, the afterbody memory cell of the port is discharged.
Here, the penultimate stage memory cell of the port is static memory cell or shared memory cell, the end
The afterbody memory cell of mouth is shared memory cell；If not considering, whether the penultimate stage memory cell of the port will
The state to be overflowed, and the afterbody memory cell of the port is directly discharged, if now detecting falling for the port
Number second level memory cell will overflow, then need to obtain the shared storage being not used by again according to step 101 and step 102
Unit simultaneously distributes to the port, will so produce frequently scheduling operation, is unfavorable for improving efficiency.
Describe the specific implementation process of the present embodiment in detail with specific embodiment below in conjunction with the accompanying drawings, be described as follows：
It is assumed that fpga chip shares 4 ports, each port assignment has a static memory cell, in addition with 10
Shared memory cell for dynamically distributes.In order to identify port and the corresponding state where each memory cell, respectively
Set a property parameter to static memory cell and shared memory cell：For each static memory cell, labeled as Port_RAM,
The property parameters of setting are including R_Port, F_last, F_almost_full etc.；For each shared memory cell, it is labeled as
Dyn_RAM, the property parameters of setting include F_Used, R_Port, F_last, R_RAM_Before, F_empty and F_
almost_full.Wherein, the R_Port represents the port where memory cell, and 1 represents that port 1,2 represents that port 2,3 represents
Port 3,4 represents that port 4,5 represents to be not belonging to any one port；The F_last indicates whether to be in last of port
Level, it is in the afterbody of port for 1 expression memory cell, is the non-afterbody that 0 expression memory cell is in port；It is described
F_almost_full represents whether memory cell will overflow, and will overflow for 1 expression memory cell, be 0 expression memory cell
It will not overflow；The F_Used represents whether memory cell has been used, and is not used by for 0 expression memory cell, is that 1 expression is deposited
Storage unit has been used；The R_RAM_Before is the label of the previous stage memory cell of port residing for memory cell, is used for
Indicate data-message transmission direction；The F_empty represents whether memory cell is idle, and 1 represents that free time, 0 represent busy.
The state of port 1 is detected, detects that the higher level of port 1 is associated with 3 memory cell, respectively Port_RAM_
1、Dyn_RAM_1、Dyn_RAM_2；Wherein, data message flows to Dyn_RAM_1 from Dyn_RAM_2 successively, flows to Port_ again
RAM_1, and now Dyn_RAM_2 F_last numerical value is 1.
If detecting, the numerical value of the F_almost_full corresponding to Dyn_RAM_2 is equal to 1, that is, represents that Dyn_RAM_2's is slow
Deposit inadequate resource and cause data message to overflow；Then detect whether the Dyn_RAM being not used by be present, that is, detect whether to deposit
It is equal to 5 Dyn_RAM in numerical value of the F_Used numerical value equal to 0 and R_Port；If, will in the presence of the Dyn_RAM being not used by
The Dyn_RAM levels being not used by are associated in behind the Dyn_RAM_2 of port 1；And by the F_Used of Dyn_RAM number
The numerical value that value is changed to 1, R_Port is changed to 1, F_last numerical value and is changed in 1, R_RAM_Before corresponding previous stage RAM's
Labelled notation is Dyn_RAM_2, and Dyn_RAM_2 F_last numerical value is changed into 0.
If detecting, the numerical value of the F_empty corresponding to Dyn_RAM_2 is equal to 1, when representing that Dyn_RAM_2 is in idle,
It is then Dyn_RAM_1 according to previous stage RAM corresponding in Dyn_RAM_2 R_RAM_Before label, detects Dyn_
Whether the numerical value of the F_almost_full corresponding to RAM_1 is equal to 0；If equal to 0, the Dyn_RAM_2 is discharged, and by institute
The numerical value for stating Dyn_RAM_2 R_Port is changed to 5, F_last numerical value and is changed in 0, R_RAM_Before corresponding previous stage
RAM labelled notation is changed to 0, and Dyn_RAM_1 F_last numerical value is changed into 1 for nothing, F_Used numerical value；If it is equal to
1, then the Dyn_RAM_2 is not discharged.
Embodiment two
A kind of implementation process schematic diagram of storage resource sharing method of the embodiment of the present invention two, as shown in Fig. 2 including：
Step 201：Whether whether the afterbody memory cell of detection port is idle and be shared memory cell；
All it is made up of generally, due to the storage resource that fpga chip inside is included multiple BRAM, and one
BRAM's is typically sized to 18KB or 36KB.After fpga chip startup, the storage resource inside fpga chip is divided first
For a number of memory cell, each memory cell includes a number of BRAM；Then, by whole memory cell
A part of memory cell distribute to each port inside fpga chip, and make the memory cell difference level for distributing to identical port
Connection gets up, and remaining memory cell is used for follow-up dynamically distributes.
Here, it is necessary to explanation, the memory cell is to represent a kind of storage resource, each memory cell by one or
More than one BRAM is formed；The BRAM quantity that each memory cell is included be able to can also be differed with identical, i.e., each storage
The size of unit may be identical, it is also possible to differs；The number of memory cells that each port is obtained can be with identical, can also not
Identical, i.e., the storage resource that each port is obtained may be identical, it is also possible to differs；The port can be multiple specific
Physical port or multiple different subports, or multiple queues in some port；For to distributing to port
Memory cell makes a distinction with the remaining memory cell, and the memory cell that port is distributed to described in mark is fixed storage list
Member, and it is shared memory cell to identify the remaining memory cell.
Specifically, fpga chip detects to the working condition of port in the course of the work, if detection exit port is most
Rear stage memory cell is idle, then shows that the afterbody memory cell of the port is not carried out at caching currently to data message
Reason or it is uncached have a data message, the afterbody memory cell of the port relative to the port be it is idle, unnecessary,
Then perform step 202；If the afterbody memory cell for detecting exit port is not idle, step 201 is continued executing with.
Here, the afterbody memory cell of the port is shared memory cell, i.e., when the port level be associated with it is shared
During memory cell, step 202 is just performed.
Step 202：If the afterbody memory cell of the port is idle and is shared memory cell, the end is discharged
The afterbody memory cell of mouth.
Specifically, if the afterbody memory cell that exit port is detected in step 201 is idle and the port last
When level memory cell is shared memory cell, then the afterbody memory cell of the port is discharged, make the memory cell
State be changed into the shared memory cell being not used by again.
Here, the shared memory cell being not used by refer to the state of the shared memory cell be not used by,
It is not allocated to arbitrary port.
Further, before step 202, methods described also includes：The penultimate stage storage for detecting the port is single
Whether member will overflow, if it is not, then discharging the afterbody memory cell of the port.
Specifically, if detecting the afterbody memory cell free time of the port and penultimate stage memory cell general
When overflowing, the afterbody memory cell of the port is not discharged；If detect the afterbody memory cell of the port
When idle and penultimate stage memory cell will not overflow, the afterbody memory cell of the port is discharged.
Here, the penultimate stage memory cell of the port is static memory cell or shared memory cell, the end
The afterbody memory cell of mouth is shared memory cell；If not considering, whether the penultimate stage memory cell of the port will
The state to be overflowed, and the afterbody memory cell of the port is directly discharged, if now detecting falling for the port
Number second level memory cell will overflow, then need to obtain the shared memory cell being not used by again and distribute to the end
Mouthful, frequently scheduling operation will be so produced, is unfavorable for improving efficiency.
Describe the specific implementation process of the present embodiment in detail with specific embodiment below in conjunction with the accompanying drawings, be described as follows：
It is assumed that fpga chip shares 4 ports, each port assignment has a static memory cell, in addition with 10
Shared memory cell for dynamically distributes.In order to identify port and the corresponding state where each memory cell, respectively
Set a property parameter to static memory cell and shared memory cell：For each static memory cell, labeled as Port_RAM,
The property parameters of setting are including R_Port, F_last, F_almost_full etc.；For each shared memory cell, it is labeled as
Dyn_RAM, the property parameters of setting include F_Used, R_Port, F_last, R_RAM_Before, F_empty and F_
almost_full.Wherein, the R_Port represents the port where memory cell, and 1 represents that port 1,2 represents that port 2,3 represents
Port 3,4 represents that port 4,5 represents to be not belonging to any one port；The F_last indicates whether to be in last of port
Level, it is in the afterbody of port for 1 expression memory cell, is the non-afterbody that 0 expression memory cell is in port；It is described
F_almost_full represents whether memory cell will overflow, and will overflow for 1 expression memory cell, be 0 expression memory cell
It will not overflow；The F_Used represents whether memory cell has been used, and is not used by for 0 expression memory cell, is that 1 expression is deposited
Storage unit has been used；The R_RAM_Before is the label of the previous stage memory cell of port residing for memory cell, is used for
Indicate data-message transmission direction；The F_empty represents whether memory cell is idle, and 1 represents that free time, 0 represent busy.
The state of port 1 is detected, detects that the higher level of port 1 is associated with 3 memory cell, respectively Port_RAM_
1、Dyn_RAM_1、Dyn_RAM_2；Wherein, data message flows to Dyn_RAM_1 from Dyn_RAM_2 successively, flows to Port_ again
RAM_1, and now Dyn_RAM_2 F_last numerical value is 1.When the numerical value for detecting the F_empty corresponding to Dyn_RAM_2
Equal to 1, when representing that Dyn_RAM_2 is in idle, then according to previous stage corresponding in Dyn_RAM_2 R_RAM_Before
RAM label is Dyn_RAM_1, and whether the numerical value for detecting the F_almost_full corresponding to Dyn_RAM_1 is equal to 0；If it is equal to
0, then discharge the Dyn_RAM_2, and by the R_Port of Dyn_RAM_2 numerical value be changed to 5, F_last numerical value be changed to 0,
Corresponding previous stage RAM labelled notation is to be changed to 0 without, F_Used numerical value in R_RAM_Before, and by Dyn_
RAM_1 F_last numerical value is changed to 1；If equal to 1, the Dyn_RAM_2 is not discharged.
To realize the above method, the embodiment of the present invention additionally provides a kind of storage resource sharing means, and described device can be set
It is placed in above fpga chip, as shown in figure 3, described device includes：Detection module 31, processing module 32；Wherein,
Whether the detection module 31, the memory cell for detecting port will overflow；
The processing module 32, for detecting that the memory cell of the port will overflow when the detection module 31
When, the shared memory cell level of free time is associated in behind the afterbody memory cell of the port.
All it is made up of generally, due to the storage resource that fpga chip inside is included multiple BRAM, and one
BRAM's is typically sized to 18KB or 36KB.After fpga chip startup, the storage resource inside fpga chip is divided first
For a number of memory cell, each memory cell includes a number of BRAM；Then, by whole memory cell
A part of memory cell distribute to each port inside fpga chip, and make the memory cell difference level for distributing to identical port
Connection gets up, and remaining memory cell is used for follow-up dynamically distributes.
Here, it is necessary to explanation, the memory cell is to represent a kind of storage resource, each memory cell by one or
More than one BRAM is formed；The BRAM quantity that each memory cell is included be able to can also be differed with identical, i.e., each storage
The size of unit may be identical, it is also possible to differs；The number of memory cells that each port is obtained can be with identical, can also not
Identical, i.e., the storage resource that each port is obtained may be identical, it is also possible to differs；The port can be multiple specific
Physical port or multiple different subports, or multiple queues in some port；For to distributing to port
Memory cell makes a distinction with the remaining memory cell, and the memory cell that port is distributed to described in mark is fixed storage list
Member, and it is shared memory cell to identify the remaining memory cell.
Here, if the memory cell that the detection module 31 detects exit port will overflow, demonstrate the need for as the end
Mouth reallocation shared memory cell so that the port disclosure satisfy that the needs that caching process is carried out to data message, that is, inform
Processing module 32 performs corresponding operation；If the memory cell that the detection module 31 detects exit port will not overflow, continue
Perform detection operates.
Here, whether the memory cell of the detection of detection module 31 port will overflow, and can detect port most
Whether the penultimate stage memory cell that port will be overflowed or be detected to rear stage memory cell whether will overflow or detect
Whether the memory cell in addition to afterbody memory cell and penultimate stage memory cell of port will overflow, this reality
Apply in example and illustrated so that whether the afterbody memory cell of the detection module 31 detection port will overflow as an example；It is described
The afterbody memory cell of port is static memory cell or shared memory cell, the i.e. static memory cell when the port
When non-level is associated with shared memory cell below, the afterbody memory cell of the port is static memory cell；When the end
When the static memory cell later stages of mouth are associated with shared memory cell, the afterbody memory cell of the port is shared storage
Unit.
The processing module 32, is specifically used for：When the memory cell of the detection module 31 detection exit port will overflow
When, i.e., the afterbody memory cell of the detection of detection module 31 exit port will overflow described in the present embodiment, will be not used by
Shared memory cell level be associated in behind the afterbody memory cell of the port, meet that the port is entered to data message
The needs of row caching process.
Here, the shared memory cell being not used by refers to that the shared memory cell is any currently without being assigned to
Port uses；Situation is needed to storage resource according to the port, can be not used by one or more shared deposits
Storage unit level is associated in behind the afterbody memory cell of the port；It is described to cascade the shared memory cell being not used by
After behind the afterbody memory cell of the port, the afterbody memory cell of the port is shared storage
Unit.
Further, the detection module 31, it is additionally operable to detect whether the shared memory cell being not used by be present；
The processing module 32, for detecting the shared memory cell being not used by be present when the detection module 31
When, the shared memory cell being not used by is distributed into the port.
Here, if the shared memory cell for detecting to be not used by has multiple, can by any one or more than one not
The shared memory cell used distributes to the port；If the afterbody of all of the port included inside fpga chip is deposited
Storage unit did not all occur detecting the situation that will be overflowed, then was stored in the afterbody for detecting some port for the first time
When unit will overflow, it can not have to detect whether the shared memory cell being not used by be present.
Further, the processing module 32, it is additionally operable to when the detection module 31 detects to be not present what is be not used by
During shared memory cell, according to the priority of each port of setting, the port lower than the priority of the port is discharged most
Rear stage memory cell, and the afterbody memory cell that the low port of the priority than the port is discharged is distributed
To the port；The afterbody memory cell of the low port of the priority than the port is shared memory cell；
Here, the priority of the port is that user is running into situations such as data message happens suddenly to solve port, causes sky
Not busy shared memory cell has been allocated, and needs preferential ensure set by certain port acquisition shared memory cell；If
The priority that port described in the priority ratio of multiple ports be present is low and the afterbody memory cell of the multiple port is all
Shared memory cell, then the afterbody memory cell of the port in the multiple port with lowest priority can be released
Put or discharge the afterbody memory cell of any one port in the multiple port.
Further, whether the detection module 31, the afterbody memory cell for being additionally operable to detect port are idle and be
No is shared memory cell；
The processing module 32, it is additionally operable to when the detection module 31 detects the afterbody memory cell of the port
It is idle and when being shared memory cell, discharge the afterbody memory cell of the port.
Here, if the detection module 31 detect exit port afterbody memory cell is idle and the port most
When rear stage memory cell is shared memory cell, the processing module 32 discharges the afterbody memory cell of the port；
If the afterbody memory cell that the detection module 31 detects exit port is not idle, the processing module 32 does not discharge institute
State the afterbody memory cell of port.
Here, the memory cell free time refers to that the memory cell is current not to data message progress caching process, or not
It is cached with data message；If the afterbody memory cell of port is idle, be relative to the port it is idle, unnecessary,
The afterbody memory cell of the releasable port, make that the state of the memory cell is changed into being not used by again shared deposits
Storage unit.
The detection module 31, it is additionally operable to after the afterbody memory cell free time of exit port is detected, described in detection
Whether the penultimate stage memory cell of port will overflow；
The processing module 32, it is additionally operable to when the detection module 31 detects that the penultimate stage storage of the port is single
When member will not overflow, the afterbody memory cell of the port is discharged.
Here, if the detection module 31 detects that the afterbody memory cell of the port is idle and second from the bottom
When level memory cell will overflow, the processing module 32 does not discharge the afterbody memory cell of the port；If the inspection
When survey module 31 detects that the afterbody memory cell of the port is idle and penultimate stage memory cell will not overflow,
The processing module 32 discharges the afterbody memory cell of the port.
Here, the penultimate stage memory cell of the port is static memory cell or shared memory cell, the end
The afterbody memory cell of mouth is shared memory cell；If not considering, whether the penultimate stage memory cell of the port will
The state to be overflowed, and the afterbody memory cell of the port is directly discharged, if now detecting falling for the port
Number second level memory cell will overflow, then need to be total to again according to what detection module 31 and the acquisition of processing module 32 were not used by
Enjoy memory cell and distribute to the port, will so produce frequently scheduling operation, be unfavorable for improving efficiency.
Describe the specific implementation process of the present embodiment in detail with specific embodiment below in conjunction with the accompanying drawings, be described as follows：
It is assumed that fpga chip shares 4 ports, each port assignment has a static memory cell, in addition with 10
Shared memory cell for dynamically distributes.In order to identify port and the corresponding state where each memory cell, respectively
Set a property parameter to static memory cell and shared memory cell：For each static memory cell, labeled as Port_RAM,
The property parameters of setting are including R_Port, F_last, F_almost_full etc.；For each shared memory cell, it is labeled as
Dyn_RAM, the property parameters of setting include F_Used, R_Port, F_last, R_RAM_Before, F_empty and F_
almost_full.Wherein, the R_Port represents the port where memory cell, and 1 represents that port 1,2 represents that port 2,3 represents
Port 3,4 represents that port 4,5 represents to be not belonging to any one port；The F_last indicates whether to be in last of port
Level, it is in the afterbody of port for 1 expression memory cell, is the non-afterbody that 0 expression memory cell is in port；It is described
F_almost_full represents whether memory cell will overflow, and will overflow for 1 expression memory cell, be 0 expression memory cell
It will not overflow；The F_Used represents whether memory cell has been used, and is not used by for 0 expression memory cell, is that 1 expression is deposited
Storage unit has been used；The R_RAM_Before is the label of the previous stage memory cell of port residing for memory cell, is used for
Indicate data-message transmission direction；The F_empty represents whether memory cell is idle, and 1 represents that free time, 0 represent busy.
Detection module 31 detects to the state of port 1, detects that the higher level of port 1 is associated with 3 memory cell, is respectively
Port_RAM_1、Dyn_RAM_1、Dyn_RAM_2；Wherein, data message flows to Dyn_RAM_1 from Dyn_RAM_2 successively, flowed again
To Port_RAM_1, and now Dyn_RAM_2 F_last numerical value is 1.
If detection module 31 detects that the numerical value of the F_almost_full corresponding to Dyn_RAM_2 is equal to 1, that is, represent
Dyn_RAM_2 cache resources are insufficient and cause data message to overflow；Then detection module 31 continues to detect whether exist not
The Dyn_RAM used, that is, detect whether the Dyn_RAM that numerical value of the numerical value equal to 0 and R_Port that F_Used be present is equal to 5；
If in the presence of the Dyn_RAM being not used by, the Dyn_RAM levels being not used by are associated in the Dyn_ of port 1 by processing module 32
Behind RAM_2, and the numerical value that the F_Used of Dyn_RAM numerical value is changed to 1, R_Port is changed to 1, F_last numerical value
The labelled notation for being changed to previous stage RAM corresponding in 1, R_RAM_Before is Dyn_RAM_2, and by Dyn_RAM_2's
F_last numerical value is changed to 0.
If detection module 31 detects that the numerical value of the F_empty corresponding to Dyn_RAM_2 is equal to 1, represent at Dyn_RAM_2
Then it is Dyn_RAM_1 according to previous stage RAM corresponding in Dyn_RAM_2 R_RAM_Before label when the free time, inspection
Survey module 31 and whether continue to detect the numerical value of the F_almost_full corresponding to Dyn_RAM_1 equal to 0；If equal to 0, handle
Module 32 discharges the Dyn_RAM_2, and the numerical value that the R_Port of Dyn_RAM_2 numerical value is changed to 5, F_last is changed to
0th, previous stage RAM corresponding in R_RAM_Before labelled notation is to be changed to 0 without, F_Used numerical value, and by Dyn_
RAM_1 F_last numerical value is changed to 1；If equal to 1, the Dyn_RAM_2 is not discharged.
The foregoing is only a preferred embodiment of the present invention, is not intended to limit the scope of the present invention.It is all
All any modification, equivalent and improvement made within the spirit and scope of the present invention etc., it is all contained in the protection model of the present invention
Within enclosing.
Claims (10)
1. a kind of storage resource sharing method, it is characterised in that methods described includes：
Whether the memory cell of detection port will overflow, if so, being then associated in the shared memory cell level being not used by described
Behind the afterbody memory cell of port.
2. according to the method for claim 1, it is characterised in that described that the shared memory cell level being not used by is associated in institute
Before stating behind the afterbody memory cell of port, methods described also includes：
Detect whether the shared memory cell being not used by be present, if in the presence of by the shared memory cell being not used by
Distribute to the port.
3. according to the method for claim 1, it is characterised in that described that the shared memory cell level being not used by is associated in institute
After stating behind the afterbody memory cell of port, methods described also includes：
It is whether idle and whether be shared memory cell to detect the afterbody memory cell of the port, if the port is most
Rear stage memory cell is idle and is shared memory cell, then discharges the afterbody memory cell of the port.
4. according to the method for claim 2, it is characterised in that methods described also includes：
When detecting to be not present the shared memory cell being not used by, the port lower than the priority of the port is discharged most
Rear stage memory cell, and the afterbody memory cell that the low port of the priority than the port is discharged is distributed
To the port；The afterbody memory cell of the low port of the priority than the port is shared memory cell.
5. according to the method for claim 3, it is characterised in that methods described also includes：
When the afterbody memory cell for detecting the port is idle and after be shared memory cell, detects the port
Whether penultimate stage memory cell will overflow, if it is not, then discharging the afterbody memory cell of the port.
6. a kind of storage resource sharing means, it is characterised in that described device includes：Detection module, processing module；Wherein,
Whether the detection module, the memory cell for detecting port will overflow；
The processing module, when the memory cell for detecting the port when the detection module will overflow, will not by
The shared memory cell level used is associated in behind the afterbody memory cell of the port.
7. device according to claim 6, it is characterised in that
The detection module, it is additionally operable to detect whether the shared memory cell being not used by be present；
The processing module, it is additionally operable to when the detection module detects to exist the shared memory cell being not used by, by institute
State the shared memory cell being not used by and distribute to the port.
8. device according to claim 6, it is characterised in that
The detection module, it is additionally operable to when the shared memory cell level being not used by is associated in the port by the processing module
After behind afterbody memory cell, whether the afterbody memory cell for detecting the port idle and be shared
Memory cell；
The processing module, it is additionally operable to when the detection module detects that the afterbody memory cell of the port is idle and is
During shared memory cell, the afterbody memory cell of the port is discharged.
9. device according to claim 7, it is characterised in that
The processing module, it is additionally operable to, when the detection module detects to be not present the shared memory cell being not used by, release
Put the afterbody memory cell of the port lower than the priority of the port；The low port of the priority than the port
Afterbody memory cell be shared memory cell；
The processing module, the afterbody for being additionally operable to be discharged the low port of the priority than the port store single
Member distributes to the port.
10. device according to claim 8, it is characterised in that
The detection module, it is additionally operable to when the afterbody memory cell for detecting the port is idle and is shared memory cell
Afterwards, whether detect the penultimate stage memory cell of the port will overflow；
The processing module, it is additionally operable to when the detection module detects that the penultimate stage memory cell of the port will not overflow
When going out, the afterbody memory cell of the port is discharged.
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| CN201610474784.0A CN107544917A (en) | 2016-06-24 | 2016-06-24 | A kind of storage resource sharing method and device |
| PCT/CN2017/089761 WO2017220020A1 (en) | 2016-06-24 | 2017-06-23 | Storage resource allocation method and device |
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| CN109688070A (en) * | 2018-12-13 | 2019-04-26 | 迈普通信技术股份有限公司 | A kind of data dispatching method, the network equipment and retransmission unit |
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