CN107533512A - 目录中表项合并的方法以及设备 - Google Patents

目录中表项合并的方法以及设备 Download PDF

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CN107533512A
CN107533512A CN201580079604.2A CN201580079604A CN107533512A CN 107533512 A CN107533512 A CN 107533512A CN 201580079604 A CN201580079604 A CN 201580079604A CN 107533512 A CN107533512 A CN 107533512A
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CN107533512B (zh
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方磊
顾雄礼
蔡卫光
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G06F12/082—Associative directories
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0808—Multiuser, multiprocessor or multiprocessing cache systems with cache invalidating means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/084—Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G06F2212/1021—Hit rate improvement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1041—Resource optimization
    • G06F2212/1044—Space efficiency improvement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/62—Details of cache specific to multiprocessor cache arrangements

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

本发明实施例公开了一种表项合并的方法包括确定待合并的N个表项，N个表项中的每个表项的表项标签所指示的缓存块属于合并范围，合并范围指示2a个缓存块；合并N个表项为第一表项，其中，第一表项的表项标签指示2a个缓存块，第一表项的共享者编号包括N个表项中每个表项的共享者编号，通过该方法可以有效合并目录中的表项，提升目录的使用效率。

Description

PCT国内申请，说明书已公开。

Claims (30)

  1. PCT国内申请，权利要求书已公开。
CN201580079604.2A 2015-06-29 2015-06-29 目录中表项合并的方法以及设备 Active CN107533512B (zh)

Applications Claiming Priority (1)

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PCT/CN2015/082672 WO2017000124A1 (zh) 2015-06-29 2015-06-29 目录中表项合并的方法以及设备

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CN107533512A true CN107533512A (zh) 2018-01-02
CN107533512B CN107533512B (zh) 2020-07-28

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US (1) US20180101475A1 (zh)
CN (1) CN107533512B (zh)
WO (1) WO2017000124A1 (zh)

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* Cited by examiner, † Cited by third party
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CN109683744A (zh) * 2018-12-24 2019-04-26 杭州达现科技有限公司 一种基于显示界面的目录整合方法和装置
CN109710582A (zh) * 2018-12-13 2019-05-03 创新科存储技术有限公司 一种共享目录管理方法和装置

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CN104133785A (zh) * 2014-07-30 2014-11-05 浪潮集团有限公司 采用混合目录的双控存储服务器的缓存一致性实现方法

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CN100442681C (zh) * 2002-10-11 2008-12-10 松下电器产业株式会社 环路干扰消除器、中继系统和环路干扰消除方法
US7991963B2 (en) * 2007-12-31 2011-08-02 Intel Corporation In-memory, in-page directory cache coherency scheme
US8825957B2 (en) * 2012-01-17 2014-09-02 International Business Machines Corporation Demoting tracks from a first cache to a second cache by using an occupancy of valid tracks in strides in the second cache to consolidate strides in the second cache
US20160070714A1 (en) * 2014-09-10 2016-03-10 Netapp, Inc. Low-overhead restartable merge operation with efficient crash recovery

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CN101176078A (zh) * 2005-03-17 2008-05-07 高通股份有限公司 用于优化转换后备缓冲器条目的方法及系统
US20110029738A1 (en) * 2006-03-23 2011-02-03 International Business Machines Corporation Low-cost cache coherency for accelerators
CN101859281A (zh) * 2009-04-13 2010-10-13 廖鑫 基于集中式目录的嵌入式多核缓存一致性方法
US20100325360A1 (en) * 2009-06-19 2010-12-23 Kabushiki Kaisha Toshiba Multi-core processor and multi-core processor system
US20130024629A1 (en) * 2011-07-18 2013-01-24 William Henry Flanders Data processing apparatus and method for managing coherency of cached data
US20140032848A1 (en) * 2011-09-09 2014-01-30 University Of Rochester Sharing Pattern-Based Directory Coherence for Multicore Scalability ("SPACE")
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109710582A (zh) * 2018-12-13 2019-05-03 创新科存储技术有限公司 一种共享目录管理方法和装置
CN109683744A (zh) * 2018-12-24 2019-04-26 杭州达现科技有限公司 一种基于显示界面的目录整合方法和装置
CN109683744B (zh) * 2018-12-24 2022-05-13 杭州达现科技有限公司 一种基于显示界面的目录整合方法和装置

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CN107533512B (zh) 2020-07-28
WO2017000124A1 (zh) 2017-01-05
US20180101475A1 (en) 2018-04-12

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