CN107527953B - Semiconductor device and method of making the same - Google Patents

Semiconductor device and method of making the same Download PDF

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CN107527953B
CN107527953B CN201610486009.7A CN201610486009A CN107527953B CN 107527953 B CN107527953 B CN 107527953B CN 201610486009 A CN201610486009 A CN 201610486009A CN 107527953 B CN107527953 B CN 107527953B
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polycrystalline silicon
polysilicon layer
semiconductor device
silicon layer
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CN107527953A (en
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陈永
董天化
吴亮
金岚
包小燕
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Tianjin Corp
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Semiconductor Manufacturing International Tianjin Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers

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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

The invention provides a semiconductor device and a preparation method thereof, comprising the following steps: providing a semiconductor substrate, wherein a first polycrystalline silicon layer and a dielectric layer which are arranged in a stacked mode and a side wall which surrounds the first polycrystalline silicon layer and the dielectric layer are formed on part of the semiconductor substrate; forming a composite polycrystalline silicon layer, wherein the composite polycrystalline silicon layer covers the dielectric layer, the side wall and the rest part of the semiconductor substrate, and the composite polycrystalline silicon layer on the side wall is provided with at least one step; according to the invention, the composite polycrystalline silicon layer is formed on the semiconductor substrate, the composite polycrystalline silicon layer on the side wall is provided with at least one step, so that the gradient of the composite polycrystalline silicon layer at the side wall is reduced, and the formed metal layer can completely cover the composite polycrystalline silicon layer, thereby forming complete metal silicide, reducing the resistance of the composite polycrystalline silicon layer and improving the performance of a semiconductor device.

Description

半导体器件及其制备方法Semiconductor device and method of making the same

技术领域technical field

本发明涉及半导体制造技术领域，尤其涉及一种半导体器件及其制备方法。The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor device and a preparation method thereof.

背景技术Background technique

随着半导体技术的不断发展，半导体器件的关键尺寸不断减小。因此现有技术中已采用双层多晶硅制备的互连器件，使得器件的面积不断减小。现有技术中，参考图1所示，制备双层多晶硅时，先在半导体衬底1上形成第一多晶硅2，再在第一多晶硅2上形成绝缘层6，之后，在第一多晶硅2和绝缘层6周围形成侧墙4，接着，在器件上形成第二多晶硅3，从而形成双栅极的互连器件。接着，在第二多晶硅3的表面形成金属硅化物，以减小第二多晶硅3的电阻。With the continuous development of semiconductor technology, the critical dimensions of semiconductor devices continue to decrease. Therefore, interconnection devices made of double-layer polysilicon have been used in the prior art, so that the area of the devices is continuously reduced. In the prior art, referring to FIG. 1 , when preparing double-layer polysilicon, first polysilicon 2 is formed on a semiconductor substrate 1 , and then an insulating layer 6 is formed on the first polysilicon 2 . A spacer 4 is formed around a polysilicon 2 and an insulating layer 6, and then a second polysilicon 3 is formed on the device, thereby forming a dual-gate interconnection device. Next, metal silicide is formed on the surface of the second polysilicon 3 to reduce the resistance of the second polysilicon 3 .

然而，现有技术中侧墙4上的第二多晶硅3的坡度较大，如图中虚线A中所示，在第二多晶硅3上难以形成金属层，从而不能形成完整的金属硅化物，影响器件的性能。However, in the prior art, the slope of the second polysilicon 3 on the sidewall 4 is relatively large, as shown in the dotted line A in the figure, it is difficult to form a metal layer on the second polysilicon 3, so that a complete metal layer cannot be formed Silicide, which affects the performance of the device.

发明内容SUMMARY OF THE INVENTION

本发明的目的在于，提供一种半导体器件及其制备方法，解决现有技术第二多晶硅中坡度较大的区域不能形成金属硅化物的技术问题。The purpose of the present invention is to provide a semiconductor device and a preparation method thereof, so as to solve the technical problem that metal silicide cannot be formed in a region with a relatively large slope in the second polysilicon in the prior art.

为解决上述技术问题，本发明提供一种半导体器件的制备方法，包括：In order to solve the above-mentioned technical problems, the present invention provides a preparation method of a semiconductor device, comprising:

提供半导体衬底，部分所述半导体衬底上形成有层叠设置的第一多晶硅层和介质层，以及围绕所述第一多晶硅层和所述介质层的侧墙；A semiconductor substrate is provided, on which a first polysilicon layer and a dielectric layer stacked and disposed, and spacers surrounding the first polysilicon layer and the dielectric layer are formed on part of the semiconductor substrate;

形成复合多晶硅层，所述复合多晶硅层覆盖所述介质层、所述侧墙以及剩余的部分所述半导体衬底，所述侧墙上的所述复合多晶硅层具有至少一个台阶；forming a composite polysilicon layer, the composite polysilicon layer covering the dielectric layer, the sidewall and the remaining part of the semiconductor substrate, the composite polysilicon layer on the sidewall having at least one step;

在所述复合多晶硅层表面形成金属硅化物。Metal silicide is formed on the surface of the composite polysilicon layer.

可选的，所述侧墙上的所述复合多晶硅层形成至少一个所述台阶的具体步骤包括：Optionally, the specific steps of forming at least one of the steps by the composite polysilicon layer on the sidewalls include:

形成第二多晶硅层，所述第二多晶硅层覆盖所述介质层、所述侧墙以及剩余的部分所述半导体衬底；forming a second polysilicon layer, the second polysilicon layer covering the dielectric layer, the spacers and the remaining part of the semiconductor substrate;

去除所述介质层上的和部分所述侧墙上的所述第二多晶硅层；removing the second polysilicon layer on the dielectric layer and part of the sidewall;

形成第三多晶硅层，所述第三多晶硅层覆盖剩余的所述第二多晶硅层、暴露的所述侧墙以及所述介质层，剩余的所述第二多晶硅层和所述第三多晶硅层形成所述复合多晶硅层，所述侧墙上的所述第三多晶硅层形成一个所述台阶。forming a third polysilicon layer covering the remaining second polysilicon layer, the exposed spacers and the dielectric layer, and the remaining second polysilicon layer The composite polysilicon layer is formed with the third polysilicon layer, and the third polysilicon layer on the sidewall forms one of the steps.

可选的，所述第二多晶硅层的厚度为50nm～200nm，所述第三多晶硅层的厚度为50nm～200nm。Optionally, the thickness of the second polysilicon layer is 50 nm to 200 nm, and the thickness of the third polysilicon layer is 50 nm to 200 nm.

可选的，去除所述介质层上的以及部分所述侧墙上的所述第二多晶硅层的具体步骤包括：Optionally, the specific step of removing the second polysilicon layer on the dielectric layer and part of the sidewalls includes:

沉积牺牲层，所述牺牲层覆盖所述第二多晶硅层；depositing a sacrificial layer covering the second polysilicon layer;

刻蚀所述牺牲层和所述第二多晶硅层，去除所述介质层上的和部分所述侧墙上的所述第二多晶硅层，暴露出所述介质层和部分所述侧墙；etching the sacrificial layer and the second polysilicon layer, removing the second polysilicon layer on the dielectric layer and part of the sidewall, exposing the dielectric layer and part of the side wall;

去除剩余的所述牺牲层。The remainder of the sacrificial layer is removed.

可选的，在刻蚀所述牺牲层和所述第二多晶硅层的步骤中，暴露出1/3～2/3的所述侧墙。Optionally, in the step of etching the sacrificial layer and the second polysilicon layer, 1/3˜2/3 of the sidewall spacers are exposed.

可选的，在刻蚀所述牺牲层和所述第二多晶硅层的步骤中，采用等离子体工艺刻蚀所述第二多晶硅层和所述牺牲层。Optionally, in the step of etching the sacrificial layer and the second polysilicon layer, a plasma process is used to etch the second polysilicon layer and the sacrificial layer.

可选的，刻蚀所述第二多晶硅层采用的等离子体为C2F2，CF4，O2和HBr。Optionally, the plasma used for etching the second polysilicon layer is C 2 F 2 , CF 4 , O 2 and HBr.

可选的，还包括：Optionally, also include:

去除所述介质层上的和部分所述侧墙上的所述第三多晶硅层；removing the third polysilicon layer on the dielectric layer and part of the sidewall;

形成第四多晶硅层，所述第四多晶硅层覆盖剩余的所述第三多晶硅层、暴露的所述侧墙以及所述介质层，剩余的所述第二多晶硅层、剩余的所述第三多晶硅层和所述第四多晶硅层形成所述复合多晶硅层，所述侧墙上的所述第四多晶硅层形成另一个所述台阶。forming a fourth polysilicon layer covering the remaining third polysilicon layer, the exposed spacers and the dielectric layer, and the remaining second polysilicon layer and the remaining third polysilicon layer and the fourth polysilicon layer form the composite polysilicon layer, and the fourth polysilicon layer on the sidewall forms another step.

可选的，所述介质层的材料为氮化硅，所述介质层的厚度为50nm～200nm。Optionally, the material of the dielectric layer is silicon nitride, and the thickness of the dielectric layer is 50 nm˜200 nm.

可选的，所述侧墙的材料为氮化硅。Optionally, the material of the sidewall is silicon nitride.

可选的，在所述复合多晶硅层表面形成所述金属硅化物的具体步骤包括：Optionally, the specific step of forming the metal silicide on the surface of the composite polysilicon layer includes:

在所述复合多晶硅层上沉积一金属层；depositing a metal layer on the composite polysilicon layer;

采用退火工艺处理所述半导体衬底，所述金属层与所述复合多晶硅层之间形成所述金属硅化物。The semiconductor substrate is treated by an annealing process, and the metal silicide is formed between the metal layer and the composite polysilicon layer.

可选的，所述金属层为钴金属层，采用物理气相沉积工艺形成所述金属层。Optionally, the metal layer is a cobalt metal layer, and the metal layer is formed by a physical vapor deposition process.

可选的，所述退火工艺采用的温度为400℃～900℃。Optionally, the temperature used in the annealing process is 400°C to 900°C.

可选的，所述半导体器件为多晶硅互连器件。Optionally, the semiconductor device is a polysilicon interconnect device.

相应的，本发明还提供一种半导体器件，采用上述制备方法形成，包括：Correspondingly, the present invention also provides a semiconductor device formed by the above-mentioned preparation method, comprising:

半导体衬底，层叠设置在部分所述半导体衬底上的第一多晶硅层和介质层，以及围绕所述第一多晶硅层和所述介质层的侧墙；a semiconductor substrate, stacking a first polysilicon layer and a dielectric layer disposed on a part of the semiconductor substrate, and spacers surrounding the first polysilicon layer and the dielectric layer;

复合多晶硅层，所述复合多晶硅层覆盖所述介质层、所述侧墙以及剩余的部分所述半导体衬底，所述侧墙上的所述复合多晶硅层具有至少一个台阶；a composite polysilicon layer, the composite polysilicon layer covers the dielectric layer, the sidewalls and the remaining part of the semiconductor substrate, and the composite polysilicon layer on the sidewalls has at least one step;

金属硅化物，位于所述复合多晶硅层的表面。A metal silicide is located on the surface of the composite polysilicon layer.

相对于现有技术，本发明的半导体器件及其制备方法具有以下有益效果：Compared with the prior art, the semiconductor device and the preparation method thereof of the present invention have the following beneficial effects:

本发明的半导体器件的制备方法中，在半导体衬底上形成复合多晶硅层，侧墙上的复合多晶硅层具有至少一个台阶，使得复合多晶硅层在侧墙处的坡度降低，使得形成的金属层可以完整的覆盖复合多晶硅层，从而形成完整的金属硅化物，降低复合多晶硅层的电阻，从而提高半导体器件的性能。In the preparation method of the semiconductor device of the present invention, a compound polysilicon layer is formed on the semiconductor substrate, and the compound polysilicon layer on the sidewall has at least one step, so that the slope of the compound polysilicon layer at the sidewall is reduced, so that the formed metal layer can be The composite polysilicon layer is completely covered, thereby forming a complete metal silicide, reducing the resistance of the composite polysilicon layer, thereby improving the performance of the semiconductor device.

附图说明Description of drawings

图1为现有技术中形成的双层多晶硅栅极的结构剖面示意图；1 is a schematic cross-sectional view of the structure of a double-layer polysilicon gate formed in the prior art;

图2为本发明一实施例中半导体器件的制备方法的流程图；2 is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention;

图3a为本发明一实施例中形成第二多晶硅层的结构示意图；3a is a schematic structural diagram of forming a second polysilicon layer according to an embodiment of the present invention;

图3b为本发明一实施例中形成牺牲层的结构示意图；3b is a schematic structural diagram of forming a sacrificial layer in an embodiment of the present invention;

图3c为本发明一实施例中刻蚀第二多晶硅层的结构示意图；3c is a schematic structural diagram of etching the second polysilicon layer according to an embodiment of the present invention;

图3d为本发明一实施例中去除牺牲层的结构示意图；3d is a schematic structural diagram of removing a sacrificial layer in an embodiment of the present invention;

图3e为本发明一实施例中形成复合多晶硅层的结构示意图；3e is a schematic structural diagram of forming a composite polysilicon layer according to an embodiment of the present invention;

图3f为本发明另一实施例中形成复合多晶硅层的结构示意图。FIG. 3f is a schematic structural diagram of forming a composite polysilicon layer in another embodiment of the present invention.

具体实施方式Detailed ways

下面将结合示意图对本发明的半导体器件及其制备方法进行更详细的描述，其中表示了本发明的优选实施例，应该理解本领域技术人员可以修改在此描述的本发明，而仍然实现本发明的有利效果。因此，下列描述应当被理解为对于本领域技术人员的广泛知道，而并不作为对本发明的限制。The semiconductor device of the present invention and its preparation method will be described in more detail below with reference to the schematic diagrams, wherein the preferred embodiments of the present invention are shown, and it should be understood that those skilled in the art can modify the present invention described herein and still realize the present invention. beneficial effect. Therefore, the following description should be construed as widely known to those skilled in the art and not as a limitation of the present invention.

为了清楚，不描述实际实施例的全部特征。在下列描述中，不详细描述公知的功能和结构，因为它们会使本发明由于不必要的细节而混乱。应当认为在任何实际实施例的开发中，必须做出大量实施细节以实现开发者的特定目标，例如按照有关系统或有关商业的限制，由一个实施例改变为另一个实施例。另外，应当认为这种开发工作可能是复杂和耗费时间的，但是对于本领域技术人员来说仅仅是常规工作。In the interest of clarity, not all features of an actual embodiment are described. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention with unnecessary detail. It should be recognized that in the development of any actual embodiment, a number of implementation details must be made to achieve the developer's specific goals, such as changing from one embodiment to another in accordance with system-related or business-related constraints. Additionally, it should be appreciated that such a development effort may be complex and time consuming, but would be merely routine for those skilled in the art.

在下列段落中参照附图以举例方式更具体地描述本发明。根据下面说明和权利要求书，本发明的优点和特征将更清楚。需说明的是，附图均采用非常简化的形式且均使用非精准的比例，仅用以方便、明晰地辅助说明本发明实施例的目的。The invention is described in more detail by way of example in the following paragraphs with reference to the accompanying drawings. The advantages and features of the present invention will become apparent from the following description and claims. It should be noted that, the accompanying drawings are all in a very simplified form and in inaccurate scales, and are only used to facilitate and clearly assist the purpose of explaining the embodiments of the present invention.

本发明的核心思想在于，本发明的半导体器件及其制备方法中，在半导体衬底上形成复合多晶硅层，侧墙上的复合多晶硅层具有至少一个台阶，使得复合多晶硅层在侧墙处的坡度降低，使得形成的金属层可以完整的覆盖复合多晶硅层，从而形成完整的金属硅化物，降低复合多晶硅层的电阻，从而提高半导体器件的性能。The core idea of the present invention is that, in the semiconductor device and the manufacturing method thereof of the present invention, a compound polysilicon layer is formed on the semiconductor substrate, and the compound polysilicon layer on the sidewall has at least one step, so that the slope of the compound polysilicon layer at the sidewall is The metal layer can completely cover the composite polysilicon layer, so as to form a complete metal silicide, reduce the resistance of the composite polysilicon layer, and improve the performance of the semiconductor device.

以下结合附图2以及图3a～图3f对本发明的半导体器件的制备方法进行详细的描述，其中，图2为本发明的半导体器件制备方法的流程图，图3a-图3e为本发明一实施例中半导体器件的制备方法中各步骤对应的结构的剖面示意图，图3f为本发明另一实施例中形成的半导体器件的结构示意图。本发明的半导体器件制备方法包括如下步骤：The method for manufacturing a semiconductor device of the present invention will be described in detail below with reference to FIG. 2 and FIGS. 3a to 3f , wherein FIG. 2 is a flowchart of the method for manufacturing a semiconductor device of the present invention, and FIGS. 3a to 3e are an implementation of the present invention. Figure 3f is a schematic diagram of the structure of the semiconductor device formed in another embodiment of the present invention. The semiconductor device preparation method of the present invention comprises the following steps:

执行步骤S1，参考图3a所示，提供半导体衬底10，部分所述半导体衬底10上形成有层叠设置的第一多晶硅层20和介质层30，在本实施例中，所述介质层30的材料为氮化硅，所述介质层30的厚度为50nm～200nm，例如，100nm、150nm等。接着，形成围绕所述第一多晶硅层20和所述介质层30的侧墙40，其中，所述侧墙40的材料为氮化硅。Step S1 is performed. Referring to FIG. 3a, a semiconductor substrate 10 is provided, and a first polysilicon layer 20 and a dielectric layer 30 are formed on part of the semiconductor substrate 10. In this embodiment, the dielectric The material of the layer 30 is silicon nitride, and the thickness of the dielectric layer 30 is 50 nm˜200 nm, for example, 100 nm, 150 nm, and the like. Next, a spacer 40 surrounding the first polysilicon layer 20 and the dielectric layer 30 is formed, wherein the material of the spacer 40 is silicon nitride.

接着，执行步骤S2，结合图3b～图3e所示，在半导体衬底10上形成复合多晶硅层70，所述复合多晶硅层70覆盖所述介质层30、所述侧墙40以及剩余的部分所述半导体衬底10，所述侧墙40上的所述复合多晶硅层70具有至少一个台阶71。本发明中，形成的所述半导体器件包括第一多晶硅层20和复合多晶硅层70，从而形成双栅极器件，第一多晶硅层20为双栅极器件中的一个栅极结构。复合多晶硅层70作为双栅极器件中的另一个栅极结构。Next, step S2 is performed, and as shown in FIGS. 3b to 3e , a compound polysilicon layer 70 is formed on the semiconductor substrate 10 , and the compound polysilicon layer 70 covers the dielectric layer 30 , the sidewall spacers 40 and the remaining parts. In the semiconductor substrate 10 , the composite polysilicon layer 70 on the sidewall spacers 40 has at least one step 71 . In the present invention, the formed semiconductor device includes a first polysilicon layer 20 and a composite polysilicon layer 70 to form a dual gate device, and the first polysilicon layer 20 is a gate structure in the dual gate device. The composite polysilicon layer 70 acts as another gate structure in a dual gate device.

具体的，在本实施例中，所述侧墙40上的所述复合多晶硅层70形成至少一个所述台阶71的具体步骤包括：Specifically, in this embodiment, the specific steps of forming at least one of the steps 71 on the composite polysilicon layer 70 on the sidewall 40 include:

首先，参考图3b所示，形成第二多晶硅层50，所述第二多晶硅层50覆盖所述介质层30、所述侧墙40以及剩余的部分所述半导体衬底10。本实施例中，采用外延或气相沉积的方法形成第二多晶硅层50，所述第二多晶硅层50的厚度为50nm～200nm。First, as shown in FIG. 3 b , a second polysilicon layer 50 is formed, and the second polysilicon layer 50 covers the dielectric layer 30 , the spacers 40 and the remaining part of the semiconductor substrate 10 . In this embodiment, the second polysilicon layer 50 is formed by means of epitaxy or vapor deposition, and the thickness of the second polysilicon layer 50 is 50 nm˜200 nm.

之后，去除所述介质层30上的和部分所述侧墙40上的第二多晶硅层50。在本实施例中，去除所述介质层30上的以及部分所述侧墙40上的第二多晶硅层50的具体步骤包括：继续参考图3b所示，沉积牺牲层60，所述牺牲层60完全覆盖所述第二多晶硅层50，牺牲层60为有机膜层，例如有机酚醛树脂；接着，参考图3c所示，刻蚀所述牺牲层60和所述第二多晶硅层50，去除所述介质层30上的和部分所述侧墙40上的第二多晶硅层50，暴露出所述介质层30和部分所述侧墙40。在本实施例中，采用等离子体工艺刻蚀所述第二多晶硅层50和所述牺牲层60。刻蚀所述第二多晶硅层50采用的等离子体为C2F2，CF4，O2和HBr，且C2F2，CF4，O2和HBr同时刻蚀牺牲层60。并且，本实施例中，暴露出1/3～2/3的所述侧墙40，优选的，暴露出1/2的侧墙，使得后续形成的台阶位于侧墙40的中间位置，金属层能够更好的沉积在侧墙40上。之后，参考图3d所示，去除剩余的所述牺牲层60，例如，采用有机溶剂去除所述牺牲层60。After that, the second polysilicon layer 50 on the dielectric layer 30 and part of the sidewall spacers 40 is removed. In this embodiment, the specific steps of removing the second polysilicon layer 50 on the dielectric layer 30 and part of the sidewall spacers 40 include: continuing to refer to FIG. 3b, depositing a sacrificial layer 60, the sacrificial layer The layer 60 completely covers the second polysilicon layer 50, and the sacrificial layer 60 is an organic film layer, such as an organic phenolic resin; then, as shown in FIG. 3c, the sacrificial layer 60 and the second polysilicon are etched layer 50 , the second polysilicon layer 50 on the dielectric layer 30 and part of the spacer 40 is removed to expose the dielectric layer 30 and part of the spacer 40 . In this embodiment, the second polysilicon layer 50 and the sacrificial layer 60 are etched by a plasma process. The plasma used for etching the second polysilicon layer 50 is C 2 F 2 , CF 4 , O 2 and HBr, and the sacrificial layer 60 is simultaneously etched by C 2 F 2 , CF 4 , O 2 and HBr. In addition, in this embodiment, 1/3˜2/3 of the sidewall 40 is exposed, preferably, 1/2 of the sidewall is exposed, so that the step formed subsequently is located in the middle of the sidewall 40 , and the metal layer It can be better deposited on the sidewall 40 . After that, referring to FIG. 3d, the remaining sacrificial layer 60 is removed, for example, the sacrificial layer 60 is removed by using an organic solvent.

接着，参考图3e所示，形成第三多晶硅层(图中未示出)，所述第三多晶硅层覆盖剩余的第二多晶硅层50、暴露的所述侧墙40以及所述介质层30，剩余的所述第二多晶硅层50和所述第三多晶硅层形成复合多晶硅层70，所述侧墙40上的第三多晶硅层形成一个所述台阶71。在本实施例中，采用外延或气相沉积工艺形成第三多晶硅层，所述第三多晶硅层的厚度为50nm～200nm，使得最终形成的复合多晶硅层70的厚度为100nm～400nm。Next, referring to FIG. 3e, a third polysilicon layer (not shown in the figure) is formed, the third polysilicon layer covers the remaining second polysilicon layer 50, the exposed sidewall spacers 40 and the The dielectric layer 30, the remaining second polysilicon layer 50 and the third polysilicon layer form a composite polysilicon layer 70, and the third polysilicon layer on the sidewall spacers 40 forms one of the steps 71. In this embodiment, an epitaxial or vapor deposition process is used to form the third polysilicon layer, and the thickness of the third polysilicon layer is 50 nm˜200 nm, so that the thickness of the finally formed composite polysilicon layer 70 is 100 nm˜400 nm.

此外，在本发明的另一实施例中，复合多晶硅层70上还可以不止形成一个台阶71，而形成两个或两个以上台阶，使得侧墙上的复合多晶硅层的坡度更小。在该实施例中，本发明的半导体器件的制备方法还包括：In addition, in another embodiment of the present invention, not only one step 71 but two or more steps may be formed on the composite polysilicon layer 70 , so that the slope of the composite polysilicon layer on the sidewall is smaller. In this embodiment, the preparation method of the semiconductor device of the present invention further comprises:

去除所述介质层30上的和部分所述侧墙40上的第三多晶硅层，可以理解的是，本实施例中，可以先在半导体衬底10的表面上形成牺牲层，牺牲层覆盖第三多晶硅层，接着，采用等离子体刻蚀的方法去除部分第三多晶硅层和部分牺牲层，从而去除介质层30和部分侧墙上的第三多晶硅层，最终，去除牺牲层。The third polysilicon layer on the dielectric layer 30 and part of the sidewall spacers 40 is removed. It can be understood that, in this embodiment, a sacrificial layer can be formed on the surface of the semiconductor substrate 10 first. Covering the third polysilicon layer, and then removing part of the third polysilicon layer and part of the sacrificial layer by plasma etching, thereby removing the dielectric layer 30 and part of the third polysilicon layer on the sidewalls, and finally, Remove the sacrificial layer.

参考图3f所示，形成第四多晶硅层，所述第四多晶硅层覆盖剩余的第三多晶硅层、暴露的侧墙以及所述介质层，剩余的所述第二多晶硅层、剩余的所述第三多晶硅层和所述第四多晶硅层形成所述复合多晶硅层70，所述侧墙上的第四多晶硅层形成另一个所述台阶71，从而本实施例中，所述复合多晶硅层70中具有两个台阶71。Referring to FIG. 3f, a fourth polysilicon layer is formed, the fourth polysilicon layer covers the remaining third polysilicon layer, the exposed spacers and the dielectric layer, and the remaining second polysilicon layer is The silicon layer, the remaining third polysilicon layer and the fourth polysilicon layer form the composite polysilicon layer 70, and the fourth polysilicon layer on the sidewalls forms another step 71, Therefore, in this embodiment, the composite polysilicon layer 70 has two steps 71 .

本实施例中，刻蚀第三多晶硅层时，暴露出1/2～3/4的所述侧墙40。例如，在该实施例中，刻蚀第二多晶硅层时，暴露出1/3的侧墙，而在刻蚀第三多晶硅层，暴露出2/3的侧墙，从而使得第三多晶硅层形成的台阶位于侧墙的1/3处，第四多晶硅层形成的台阶位于侧墙的2/3处。In this embodiment, when the third polysilicon layer is etched, 1/2˜3/4 of the sidewall spacers 40 are exposed. For example, in this embodiment, when the second polysilicon layer is etched, 1/3 of the sidewall spacers are exposed, and when the third polysilicon layer is etched, 2/3 of the sidewall spacers are exposed, so that the first The step formed by the three polysilicon layers is located at 1/3 of the sidewall, and the step formed by the fourth polysilicon layer is located at 2/3 of the sidewall.

最后，执行步骤S3，在所述复合多晶硅层70表面上形成金属硅化物(图中未示出)，金属硅化物用于降低复合多晶硅层70的电阻。在所述复合多晶硅层70表面上形成金属硅化物的具体步骤包括：Finally, step S3 is performed to form metal silicide (not shown in the figure) on the surface of the composite polysilicon layer 70 , and the metal silicide is used to reduce the resistance of the composite polysilicon layer 70 . The specific steps of forming metal silicide on the surface of the composite polysilicon layer 70 include:

在所述复合多晶硅层70上沉积一金属层，在本实施例中，所述金属层为钴金属层，例如，采用物理气相沉积工艺形成所述金属层。本发明中，侧墙40上的复合多晶硅层70具有至少一个台阶71，使得复合多晶硅层70在侧墙40处的坡度降低，使得金属层的沉积过程中，坡度上均可以覆盖金属层，从而金属层可以完整的覆盖复合多晶硅层70，A metal layer is deposited on the composite polysilicon layer 70. In this embodiment, the metal layer is a cobalt metal layer. For example, the metal layer is formed by a physical vapor deposition process. In the present invention, the composite polysilicon layer 70 on the sidewall 40 has at least one step 71, so that the slope of the composite polysilicon layer 70 at the sidewall 40 is reduced, so that the metal layer can be covered on the slope during the deposition of the metal layer, thereby The metal layer can completely cover the composite polysilicon layer 70,

之后，采用退火工艺处理所述半导体衬底10，所述金属层与所述复合多晶硅层70之间形成所述金属硅化物，本实施例中，退火工艺采用的维度为400℃～900℃，例如，450℃、600℃、750℃、800℃，在所述复合多晶硅层70上形成钴硅金属硅化物。After that, the semiconductor substrate 10 is treated by an annealing process, and the metal silicide is formed between the metal layer and the composite polysilicon layer 70 . In this embodiment, the dimension of the annealing process is 400° C.˜900° C. For example, at 450° C., 600° C., 750° C., and 800° C., cobalt-silicon metal silicide is formed on the composite polysilicon layer 70 .

相应的，参考图3e和图3f所示，本发明的另一面还提供一种半导体器件，包括：Correspondingly, referring to FIG. 3e and FIG. 3f, another aspect of the present invention further provides a semiconductor device, comprising:

半导体衬底10，层叠设置在部分所述半导体衬底10上的第一多晶硅层20和介质层30，以及围绕所述第一多晶硅层20和所述介质层30的侧墙40；A semiconductor substrate 10 , a first polysilicon layer 20 and a dielectric layer 30 disposed on a part of the semiconductor substrate 10 , and a spacer 40 surrounding the first polysilicon layer 20 and the dielectric layer 30 ;

复合多晶硅层70，所述复合多晶硅层70覆盖所述介质层30、所述侧墙40以及剩余的部分所述半导体衬底10，所述侧墙40上的所述复合多晶硅层70具有至少一个台阶71，图3e中给出了复合多晶硅层70具有一个台阶71的结构示意图，图3f给出复合多晶硅层70具有两个台阶72的结构示意图；A composite polysilicon layer 70 covering the dielectric layer 30 , the spacers 40 and the remaining part of the semiconductor substrate 10 , the composite polysilicon layer 70 on the spacers 40 has at least one Step 71, FIG. 3e shows a schematic structural diagram of the composite polysilicon layer 70 having one step 71, and FIG. 3f shows a structural schematic diagram of the composite polysilicon layer 70 having two steps 72;

金属硅化物，位于所述复合多晶硅层70的表面。Metal silicide is located on the surface of the composite polysilicon layer 70 .

综上所述，本发明的半导体器件的制备方法，在半导体衬底上形成复合多晶硅层，侧墙上的复合多晶硅层具有至少一个台阶，使得复合多晶硅层在侧墙处的坡度降低，使得形成的金属层可以完整的覆盖复合多晶硅层，从而形成完整的金属硅化物，降低复合多晶硅层的电阻，从而提高半导体器件的性能。To sum up, in the method for preparing a semiconductor device of the present invention, a compound polysilicon layer is formed on a semiconductor substrate, and the compound polysilicon layer on the sidewall has at least one step, so that the slope of the compound polysilicon layer at the sidewall is reduced, so that the formation of The metal layer can completely cover the composite polysilicon layer, thereby forming a complete metal silicide, reducing the resistance of the composite polysilicon layer, thereby improving the performance of the semiconductor device.

显然，本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention. Thus, provided that these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims (13)

1. A method of manufacturing a semiconductor device, comprising:
providing a semiconductor substrate, wherein a first polycrystalline silicon layer and a dielectric layer which are arranged in a stacked mode and a side wall which surrounds the first polycrystalline silicon layer and the dielectric layer are formed on part of the semiconductor substrate;
forming a composite polycrystalline silicon layer, wherein the composite polycrystalline silicon layer covers the dielectric layer, the side wall and the rest part of the semiconductor substrate, and the composite polycrystalline silicon layer on the side wall is provided with at least one step; the step of forming at least one step on the composite polycrystalline silicon layer on the side wall comprises the following specific steps: forming a second polycrystalline silicon layer, wherein the second polycrystalline silicon layer covers the dielectric layer, the side wall and the rest part of the semiconductor substrate; removing the second polysilicon layer on the dielectric layer and part of the side wall; forming a third polysilicon layer, wherein the third polysilicon layer covers the remaining second polysilicon layer, the exposed side wall and the dielectric layer, the remaining second polysilicon layer and the third polysilicon layer form the composite polysilicon layer, and the third polysilicon layer on the side wall forms one step;
and forming metal silicide on the surface of the composite polycrystalline silicon layer.
2. The method of manufacturing a semiconductor device according to claim 1, wherein the second polysilicon layer has a thickness of 50nm to 200nm, and the third polysilicon layer has a thickness of 50nm to 200 nm.
3. The method for manufacturing a semiconductor device according to claim 1, wherein the step of removing the second polysilicon layer on the dielectric layer and on a part of the sidewall spacers comprises:
depositing a sacrificial layer, wherein the sacrificial layer covers the second polycrystalline silicon layer;
etching the sacrificial layer and the second polycrystalline silicon layer, removing the second polycrystalline silicon layer on the dielectric layer and part of the side wall, and exposing the dielectric layer and part of the side wall;
and removing the rest of the sacrificial layer.
4. The method for manufacturing a semiconductor device according to claim 3, wherein the side walls of 1/3-2/3 are exposed in the step of etching the sacrificial layer and the second polysilicon layer.
5. The method for manufacturing a semiconductor device according to claim 3, wherein in the step of etching the sacrifice layer and the second polysilicon layer, the second polysilicon layer and the sacrifice layer are etched by a plasma process.
6. The method for manufacturing a semiconductor device according to claim 5, wherein plasma used for etching the second polysilicon layer is C2F2，CF4，O2And HBr.
7. The method for manufacturing a semiconductor device according to claim 1, further comprising:
removing the third polysilicon layer on the dielectric layer and part of the side wall;
and forming a fourth polycrystalline silicon layer, wherein the fourth polycrystalline silicon layer covers the rest of the third polycrystalline silicon layer, the exposed side wall and the dielectric layer, the rest of the second polycrystalline silicon layer, the rest of the third polycrystalline silicon layer and the fourth polycrystalline silicon layer form the composite polycrystalline silicon layer, and the fourth polycrystalline silicon layer on the side wall forms the other step.
8. The method for manufacturing a semiconductor device according to claim 1, wherein the dielectric layer is made of silicon nitride, and has a thickness of 50nm to 200 nm.
9. The method for manufacturing a semiconductor device according to claim 1, wherein the material of the sidewall is silicon nitride.
10. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming the metal silicide on the surface of the composite polysilicon layer comprises:
depositing a metal layer on the composite polycrystalline silicon layer;
and processing the semiconductor substrate by adopting an annealing process, and forming the metal silicide between the metal layer and the composite polycrystalline silicon layer.
11. The method for manufacturing a semiconductor device according to claim 10, wherein the metal layer is a cobalt metal layer, and the metal layer is formed by a physical vapor deposition process.
12. The method for manufacturing a semiconductor device according to claim 10, wherein the annealing process is performed at a temperature of 400 ℃ to 900 ℃.
13. The method for manufacturing a semiconductor device according to any one of claims 1 to 12, wherein the semiconductor device is a polysilicon interconnection device.
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1204869A (en) * 1997-07-04 1999-01-13 联华电子股份有限公司 Method of forming dynamic random access memory
CN103871882A (en) * 2012-12-17 2014-06-18 中芯国际集成电路制造(上海)有限公司 Semiconductor device and manufacturing method thereof

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Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1204869A (en) * 1997-07-04 1999-01-13 联华电子股份有限公司 Method of forming dynamic random access memory
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