CN107527823A - The preparation method and package substrate of a kind of package substrate - Google Patents
The preparation method and package substrate of a kind of package substrate Download PDFInfo
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- CN107527823A CN107527823A CN201710740315.3A CN201710740315A CN107527823A CN 107527823 A CN107527823 A CN 107527823A CN 201710740315 A CN201710740315 A CN 201710740315A CN 107527823 A CN107527823 A CN 107527823A
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- basic unit
- silicon wafer
- wiring layer
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- 239000000758 substrate Substances 0.000 title claims abstract description 69
- 238000002360 preparation method Methods 0.000 title claims abstract description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 138
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 138
- 239000010703 silicon Substances 0.000 claims abstract description 138
- 238000000034 method Methods 0.000 claims abstract description 33
- 238000002161 passivation Methods 0.000 claims description 15
- 230000003014 reinforcing effect Effects 0.000 claims description 8
- 230000004888 barrier function Effects 0.000 claims description 7
- 241001562042 Physa Species 0.000 claims description 4
- 239000004744 fabric Substances 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 230000002787 reinforcement Effects 0.000 claims 1
- 239000000463 material Substances 0.000 description 17
- 238000001259 photo etching Methods 0.000 description 8
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- 239000010949 copper Substances 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 238000005538 encapsulation Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910003481 amorphous carbon Inorganic materials 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000002156 mixing Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000001684 chronic effect Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000000280 densification Methods 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000001151 other effect Effects 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4885—Wire-like parts or pins
- H01L21/4889—Connection or disconnection of other leads to or from wire-like parts, e.g. wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a kind of preparation method of package substrate and package substrate, methods described includes：Silicon Wafer basic unit is provided, Silicon Wafer basic unit side is provided with pad；Form the first wiring layer again backwards to the side of the pad in Silicon Wafer basic unit, wherein, the pad and described first again wiring layer electrically connect.By the above-mentioned means, the present invention can make the line width of the wiring layer again of package substrate and line-spacing narrower.
Description
Technical field
The present invention relates to technical field of semiconductor encapsulation, preparation method and encapsulation base more particularly to a kind of package substrate
Plate.
Background technology
Commonly use package substrate in technical field of semiconductor encapsulation, package substrate can be provided for chip electrical connection, protection,
Support, radiating, assembling and other effects, to realize more pins, reduce encapsulating products volume, improve the mesh such as electrical property and thermal diffusivity
's.At present, package substrate just develops towards the direction of densification.
The present inventor has found that in general Feng Ce enterprises are difficult to the system of package substrate in chronic study procedure
Make, even if can manufacture, its manufacture package substrate wiring layer again on narrow linewidth/line-spacing all by a definite limitation.
The content of the invention
The present invention solves the technical problem of a kind of preparation method and package substrate of package substrate is provided, envelope can be made
Line width and the line-spacing for filling the wiring layer again of substrate are narrower.
In order to solve the above technical problems, one aspect of the present invention is：A kind of preparation of package substrate is provided
Method, methods described include：Silicon Wafer basic unit is provided, Silicon Wafer basic unit side is provided with pad；Carried on the back in Silicon Wafer basic unit
Form the first wiring layer again to the side of the pad, wherein, the pad and described first again wiring layer electrically connect.
In order to solve the above technical problems, another technical solution used in the present invention is：A kind of package substrate is provided, it is described
Package substrate includes：The wiring layer again of Silicon Wafer basic unit, pad and first, wherein, the pad is arranged at the Silicon Wafer basic unit
Side, described first again wiring layer be arranged at the opposite side of the Silicon Wafer basic unit, the pad and the described first wiring layer again
Electrical connection.
The beneficial effects of the invention are as follows：It is different from the situation of prior art, the preparation of package substrate of the present invention
In method pad and first again wiring layer respectively be located at Silicon Wafer basic unit both sides, pad with first again wiring layer electrically connect；One
Aspect, the pad of package substrate provided by the present invention and first again wiring layer be located at the opposite sides of glass-base, be follow-up
The two-sided encapsulating structure for having ball structure is provided technical support is provided；Another aspect, package substrate provided by the present invention are advance
Wiring layer again is prepared, the package substrate is attached by the later stage with chip, and this method is done chip than first and carried out again on chip
The line width and line-spacing of the wiring layer again of the method connected up again are narrower.
Brief description of the drawings
Fig. 1 is the schematic flow sheet of the embodiment of preparation method one of package substrate of the present invention；
Fig. 2 is the top view of the embodiment of field of semiconductor package wafer one；
Fig. 3 is the structural representation that Silicon Wafer basic unit sets the embodiment of silicon hole one；
Fig. 4 is the schematic flow sheet of the embodiment of preparation method one of package substrate of the present invention；
Fig. 5 is the structural representation of the embodiment of package substrate one corresponding to step S201-S206 in Fig. 4；
Fig. 6 is the structural representation of the embodiment of package substrate one corresponding to step S207-S214 in Fig. 4；
Fig. 7 is the schematic flow sheet of the embodiment of preparation method one of package substrate of the present invention；
Fig. 8 is the structural representation of the embodiment of package substrate one corresponding to step S301-S307 in Fig. 7；
Fig. 9 is the schematic flow sheet of the embodiment of preparation method one of package substrate of the present invention；
Figure 10 is the structural representation of the embodiment of package substrate one corresponding to step S407-S419 in Fig. 9；
Figure 11 is the structural representation of the embodiment of package substrate one of the present invention；
Figure 12 is the schematic flow sheet of another embodiment of package substrate of the present invention.
Embodiment
Referring to Fig. 1, Fig. 1 is the schematic flow sheet of the embodiment of preparation method one of package substrate of the present invention, this method
Including：
S101：Silicon Wafer basic unit is provided, Silicon Wafer basic unit side is provided with pad；
In an application scenarios, Silicon Wafer basic unit can be provided directly with pad, as shown in Fig. 2 Fig. 2 is semiconductor package
The top view of the embodiment of dress field wafer one.The wafer 10 includes basic unit 120 and pad 100, and basic unit 120 is provided with front and the back of the body
Face, pad 100 are formed at the front of basic unit 120, relatively, follow-up first again wiring layer be formed at the back side of basic unit 120；At this
In embodiment, the material of basic unit 120 is silicon, because the thermal conductivity of silicon is preferable, therefore can strengthen the heat dispersion of package substrate.
S102：In Silicon Wafer basic unit the first wiring layer again is formed backwards to the side of pad；Wherein, pad and first connects up again
Layer electrical connection.
Specifically, in an application scenarios, above-mentioned preparation method also includes：Silicon Wafer basic unit is provided with pad side
Form the second wiring layer again, second again wiring layer be formed on pad and electrically connect pad, i.e., in basic unit as shown in Figure 2
The second wiring layer again is formed on 120 positive pad 100, the first wiring layer again is formed at the back side of basic unit 120.
Due to Silicon Wafer basic unit, electric conductivity itself is poor, therefore to reach pad and the first mesh that wiring layer electrically connects again
, in one embodiment, include setting the state of Silicon Wafer basic unit to make it have weldering before formation first again wiring layer
The side of disk is located at lower section；Silicon hole is formed in the position back to pad of Silicon Wafer basic unit.Referring to Fig. 3, Silicon Wafer basic unit
20 have face-down, pair using the mode of plasma etching in Silicon Wafer basic unit 20 back to the side of pad 22 of pad 22
Answer the position of pad 22 to form silicon hole 24, in other embodiments, also other modes can be used to form silicon hole or using it
His mode by pad with first again wiring layer electrically connect；In an application scenarios, side a and the Silicon Wafer basic unit of silicon hole 24
Angle between a 20 side b is 60-80 ° (for example, 60 °, 70 °, 80 ° etc.), and the depth-to-width ratio of silicon hole 24 is less than 10:1, i.e.,
H/d ＜ 10 (for example, h/d=0.5,2,5,8,9 etc.).
Below, will be described in further detail with several specific embodiments with regard to above-mentioned method for packing.
In one embodiment, referring to Fig. 4, Fig. 4 is the embodiment of preparation method one of package substrate of the present invention
Schematic flow sheet；This method includes：
S201：The Silicon Wafer basic unit for being provided with pad is provided；Specifically, incorporated by reference to Fig. 5 a, in an application scenarios, silicon
Wafer basic unit 30 can be provided directly with pad 32, i.e., the wafer that general Feng Ce factories can directly take；
S202：The side that pad is provided with Silicon Wafer basic unit forms the first passivation layer, and in the corresponding weldering of the first passivation layer
The position of disk sets the first opening；Specifically, incorporated by reference to Fig. 5 b, in one embodiment, first in Silicon Wafer basic unit 30
Surface coats one layer of passivation layer 34, and the first passivation layer 34 is then corresponded to the position of pad 32 by exposure imaging or other means
Put to form the first opening 340 so that pad 32 exposes；In another embodiment, in the first passivation layer 34 back to Silicon Wafer
The surface of basic unit 30 can also form a dielectric layer (not shown), and the position that pad 34 is corresponded on dielectric layer is also equipped with opening (figure
Do not show), to cause pad 32 to expose.
S203：In the first passivation layer the first Seed Layer is formed back to the surface of Silicon Wafer basic unit；Specifically, incorporated by reference to figure
5c, in one embodiment, the material of the first Seed Layer 36 is titanium, aluminium, copper, gold, silver one or more of mixing therein
Thing, the technique for forming the first Seed Layer 36 is sputtering technology or physical gas-phase deposition.
S204：The first mask layer is formed back to the surface of Silicon Wafer basic unit in the first Seed Layer, and in the first mask layer pair
Answer the position of pad that the second opening is set；Specifically, incorporated by reference to Fig. 5 d, the material of the first mask layer 38 is photoresist, silica,
Silicon nitride, amorphous carbon one or more therein, in the present embodiment, the material of the first mask layer 38 is photoresist, is utilized
Photoetching process forms the second opening 380 through the first mask layer 38 in the first mask layer 38, and the second opening 380 is located at pad
32 tops.
S205：The second wiring layer again is formed in the second opening；Specifically, Fig. 5 e are referred to, in one embodiment, profit
The second wiring layer 31 again are formed in the second opening 380 with electroplating technology, and the material of the second wiring layer 31 again is copper or other conjunctions
Suitable metal.In the present embodiment second again wiring layer 31 height less than second opening 380 depth, in other embodiment party
In formula second again wiring layer 31 height can also with second opening 380 depth it is identical.
S206：Remove the first mask layer and second the first Seed Layer beyond wiring layer again；Specifically, figure is referred to
5f, in one embodiment, the first mask layer 38 is removed using photoetching process, the first Seed Layer 36 exposed；Then
The first Seed Layer of part 36 exposed is removed using wet-etching technology or dry etch process, is only retained positioned at the second cloth again
First Seed Layer 36 of the lower section of line layer 31；Wherein, wiring layer 31 electrically connects again for pad 32, the first Seed Layer 36, second；
S207：Silicon Wafer basic unit is ground back to the side of pad, make it that it is pre- that the thickness of Silicon Wafer basic unit is less than or equal to
Determine thickness；Specifically, Fig. 6 a are referred to, in an application scenarios, the Silicon Wafer for the wafer typically directly taken from Feng Ce factories
The thickness of basic unit 30 is larger, therefore in the present embodiment, it is necessary to which the side back to pad 32 of Silicon Wafer basic unit 30 is ground
Mill, to cause its thickness to be less than or equal to predetermined thickness, such as predetermined thickness is 100um, the thickness of Silicon Wafer basic unit 30 after grinding
For 50,60,80um etc..
S208：The side that the state of setting Silicon Wafer basic unit makes it have pad is located at lower section, in the back of the body of Silicon Wafer basic unit
Silicon hole is formed to the position of pad；Specifically, reference can be made to Fig. 6 b, form in mode above-described embodiment of silicon hole 40 and carried
And it will not be repeated here.
S209：The 3rd mask layer is formed back to the side of pad in Silicon Wafer basic unit, and pad is corresponded in the 3rd mask layer
Position formed the 5th opening；Specifically, Fig. 6 c are referred to, the material of the 3rd mask layer 42 is photoresist, silica, nitridation
Silicon, amorphous carbon one or more therein, in the present embodiment, the material of the 3rd mask layer 42 is photoresist, utilizes photoetching
Technique forms the 5th opening 420 through the 3rd mask layer 42 in the 3rd mask layer 42, to cause pad 32 to expose.
S210：In the 3rd mask layer the third sublayer is formed back to the surface of Silicon Wafer basic unit；Specifically, figure is referred to
6d, in one embodiment, the material of the third sublayer 44 is titanium, aluminium, copper, gold, silver one or more of mixing therein
Thing, the technique for forming the third sublayer 44 are sputtering technology or physical gas-phase deposition.
S211:The 4th mask layer is formed back to the surface of Silicon Wafer basic unit in the third sublayer, and on the 4th mask layer
Form the 6th opening；Specifically, refer to Fig. 6 e, the material of the 4th mask layer 46 is photoresist, silica, silicon nitride, without fixed
Shape carbon one or more therein, in the present embodiment, the material of the 4th mask layer 46 is photoresist, using photoetching process
The 6th opening 460 through the 4th mask layer 46 is formed in four mask layers 46.
S212：The first wiring layer again is formed in the 6th opening；Specifically, Fig. 6 f are referred to, in one embodiment,
Form the first wiring layer 48 again in the 6th opening 460 using electroplating technology, first again wiring layer 48 material for copper or other
Metal.In Fig. 6 f first again wiring layer 48 fill up the 6th opening 460, in other embodiments, first wiring layer 48 also can be again
One layer is paved with 6th opening 460, its thickness can be designed according to actual conditions, and this is not limited by the present invention.
S213：Remove the 4th mask layer and first the third sublayer beyond wiring layer again；Specifically, the step with it is upper
It is similar to state S206, its structure can refer to Fig. 6 g, wherein, first wiring layer 48, the third sublayer 44 electrically connect with pad 32 again.
S214：First again wiring layer back to the surface of Silicon Wafer basic unit, the first barrier layer is set, and on the first barrier layer
It is upper to form the 7th opening；Specifically, Fig. 6 h are referred to, the material on the first barrier layer 41 has insulation characterisitic, in an embodiment party
In formula, the 7th opening 410 is formed on the first barrier layer 41 using the mode of photoetching or other etchings.
In the second embodiment, referring to Fig. 7, Fig. 7 is another embodiment of preparation method of package substrate of the present invention
Schematic flow sheet, the main distinction of this method and one embodiment is, there is provided package substrate includes：In Silicon Wafer basic unit
Reinforcing plate is bonded back to the side of pad, its idiographic flow is as follows：
S301：The Silicon Wafer basic unit for being provided with pad is provided, and is bonded and strengthens back to the side of pad in Silicon Wafer basic unit
Plate；Specifically, reference can be made to Fig. 8 a, can select thickness to be less than or equal to the silicon wafer physa of predetermined thickness when starting according to the actual requirements
Layer 50, for example, when predetermined thickness be 100um, can directly select thickness be 50,60,80um etc. Silicon Wafer basic unit 50；It is anti-
Only in subsequent preparation process Silicon Wafer basic unit 50 insufficient strength, in the present embodiment, in Silicon Wafer basic unit 50 back to pad
52 side fitting reinforcing plate 54, the material of reinforcing plate 54 can be glass, metal, silicon chip etc., reinforcing plate 54 and silicon wafer physa
It can be fixed between layer 50 by a two-sided glued membrane fitting.
S302-S306 is identical with S202-S206 in above-described embodiment, will not be repeated here, and its structural representation can be found in
Fig. 8 b-8f.
S307：Remove reinforcing plate；Specifically, as illustrated in fig.8g, in one embodiment, reinforcing plate 54 and silicon wafer physa
Layer 50 can directly tear two-sided glued membrane off, and then remove the purpose of reinforcing plate 54 by a two-sided glue-film stickup.
S308-S314 is identical with S208-S214 steps in above-described embodiment, and its structure can be found in Fig. 6 b-6h.
In the 3rd embodiment, referring to Fig. 9, Fig. 9 is another embodiment of preparation method of package substrate of the present invention
Schematic flow sheet, the main distinction of this method and one embodiment is that the side that Silicon Wafer basic unit has pad can be entered
Row repeatedly wiring, i.e., second again wiring layer at least re-form wiring layer again and again back to the side of Silicon Wafer basic unit, in this implementation
In example, Silicon Wafer basic unit has the side of pad including wiring layer, its idiographic flow are as follows twice：
S401-S406 is identical with S201-S206 in above-described embodiment, will not be repeated here, and its structure can be found in Fig. 5 a-
5f。
S407：Second again wiring layer form the first dielectric layer back to the surface of Silicon Wafer basic unit, and in the first dielectric layer
It is upper that 3rd opening is set；Specifically, Figure 10 a are referred to, in one embodiment, the material of the first dielectric layer 60 is photoetching
Glue, after second again one layer of photoresist of surface coating of wiring layer 31, formed using the technique of photoetching on the first dielectric layer 60
3rd opening 600.
S408：In the first dielectric layer second of sublayer is formed back to the surface of Silicon Wafer basic unit；Specifically, figure is referred to
10b, in one embodiment, it can be formed using sputtering technology in the first dielectric layer 60 back to the surface of Silicon Wafer basic unit 30
Second of sublayer 62, the material of second of sublayer 62 is the metals such as copper, titanium.
S409：The second mask layer is formed back to the surface of Silicon Wafer basic unit in second of sublayer, and is set in the second mask layer
Put the 4th opening；Specifically, Figure 10 c are referred to, in one embodiment, the material of the second mask layer 64 is photoresist, profit
The 4th opening 640 is formed with the technique of photoetching.
S410：The 3rd wiring layer again is formed in the 4th opening；Specifically, Figure 10 d are referred to, the work of plating can be utilized
Skill forms the 3rd wiring layer 66 again in the 4th opening 640, and the material of the 3rd wiring layer 66 again can be the metals such as copper；Figure 10 d
In the 3rd again wiring layer 66 fill up it is whole 4th opening 640, in other embodiments, the 3rd again wiring layer 66 also can only the 4th
One layer is paved with opening 640, its thickness can be set according to actual conditions.
S411：Remove the second mask layer and the 3rd second of sublayer beyond wiring layer again；Specifically, figure is referred to
10e, after the second mask layer 64 is removed, then second of the sublayer 62 exposed is etched away；Wherein, second again wiring layer 31,
Wiring layer 66 electrically connects second of sublayer the 62, the 3rd again.
S412-S419 is identical with S207-S214 in above-described embodiment, will not be repeated here, and its structure can be found in Figure 10 f-
Shown in 10m.
Above-mentioned only signal provides three specific embodiments, is connected up again as long as being related to Silicon Wafer basic unit and having back to pad side
Fan-out package method within protection scope of the present invention.
Figure 11 is referred to, Figure 11 is the structural representation of the embodiment of package substrate one of the present invention, and the package substrate includes：
Silicon Wafer basic unit 70, pad 72 and first wiring layer 74 again, pad 72 are arranged at the side of Silicon Wafer basic unit 70, the first wiring layer again
74 are arranged at the opposite side of Silicon Wafer basic unit 70, wherein, wiring layer 74 electrically connects pad 72 and first again.
In an application scenarios, the thickness of Silicon Wafer basic unit 70 is less than or equal to predetermined thickness, such as predetermined thickness is
100um, the thickness of Silicon Wafer basic unit 70 can be 50,70,80um etc..Silicon Wafer basic unit 70 can be provided directly with pad 72, example
The wafer that can be directly taken as Feng Ce factories；The thickness of the Silicon Wafer basic unit for the wafer directly taken may directly be less than etc.
In predetermined thickness, it is also possible to more than predetermined thickness, when the thickness of Silicon Wafer basic unit 70 of wafer exceedes predetermined thickness, it is necessary to silicon
The back side of wafer basic unit 70 is ground, to cause the thickness of the Silicon Wafer basic unit in package substrate provided by the present invention to be less than
Equal to predetermined thickness.
In another application scenarios, because the electric conductivity of Silicon Wafer basic unit 70 is poor, it is located at Silicon Wafer basic unit to realize
Wiring layer 74 electrically connects the pad 72 and first of 70 opposite sides again, is set in above-mentioned Silicon Wafer basic unit 70 back to the side of pad 72
Put silicon hole 76, and the position of the position correspondence pad 72 of silicon hole 76, with cause first again wiring layer 74 pass through silicon hole 76
Electrically connected with pad 72.
In another application scenarios, please continue to refer to Figure 11, above-mentioned package substrate also includes the second wiring layer 78 again, the
Two again wiring layer 78 be arranged on pad 72 and electrically connect pad 72.
Below, several specific embodiments will be described further to the structure of package substrate provided by the present invention.
Please continue to refer to Figure 11, in one embodiment, Silicon Wafer basic unit 70 is back to the side of pad 72 except including the
Again and again outside wiring layer 74, the package substrate also includes：3rd mask layer 71, Silicon Wafer basic unit 70 is arranged at back to the one of pad 72
Side and first is again between wiring layer 74, and the position of corresponding pad 72 is provided with the 5th opening (not indicating)；The third sublayer 73,
The 3rd mask layer 71 and first is arranged at again between wiring layer 74；Wherein, first wiring layer 74, the third sublayer 73, pad again
72 electrical connections；First barrier layer 75, be arranged at first again wiring layer 74 back to the side of Silicon Wafer basic unit 70, and first stop
The 7th opening (not indicating) is formed on layer 75.Silicon Wafer basic unit 70 is provided with the side of pad 72 except including the second wiring layer 78 again
Outside, the package substrate also includes：First passivation layer 77, the side of pad 72 and second for being arranged at Silicon Wafer basic unit 70 connect up again
Between layer 78, and the position of the corresponding pad 72 of the first passivation layer 77 is provided with the first opening (not indicating)；First Seed Layer 79, if
The first passivation layer 77 and second is placed in again between wiring layer 78；Wherein, pad 72, the first Seed Layer 79, second wiring layer 78 again
Electrical connection.
Figure 12 is referred to, Figure 12 is the structural representation of the another embodiment of package substrate of the present invention；In the present embodiment,
The difference of the package substrate and package substrate in figure 11 above is, in Silicon Wafer basic unit the side of pad can be set to carry out multiple
Connect up again, exemplified by the side to be provided with pad in Silicon Wafer basic unit connect up twice, i.e., second again wiring layer 80 back to silicon
The side of wafer basic unit 82 also includes the 3rd wiring layer 84 again.Specifically, the package substrate and identical structure in above-mentioned Figure 11
It will not be repeated here, package substrate also includes in the present embodiment：First dielectric layer 86, it is arranged at the second wiring layer 80 and the 3rd again
The 3rd opening (not indicating) is provided with again between wiring layer 84, and on the first dielectric layer 86；Second of sublayer 88, is arranged at first
Dielectric layer 86 and the 3rd is again between wiring layer 84；Wherein, the second wiring layer 80, second of sublayer the 88, the 3rd wiring layer 84 again again
Electrical connection.
In other embodiments, or other structures form package substrate, this is not limited by the present invention.Above-mentioned institute
Any package substrate provided can be used in the encapsulating structures such as fan-shaped encapsulation.
Sum it up, the situation of prior art is different from, pad in the preparation method of package substrate of the present invention
With first again wiring layer respectively be located at Silicon Wafer basic unit both sides, pad with first again wiring layer electrically connect；On the one hand, it is of the invention
The pad of the package substrate provided and first again wiring layer be located at the opposite sides of glass-base, two-sided have weldering subsequently to provide
The fan-out package structure of spherical structure provides technical support；Another aspect, package substrate provided by the present invention are well prepared in advance
The package substrate is attached by wiring layer again, later stage with chip, and this method is done chip than first and connected up again on chip again
Method wiring layer again line width and line-spacing it is narrower.
Embodiments of the present invention are the foregoing is only, are not intended to limit the scope of the invention, it is every to utilize this
The equivalent structure or equivalent flow conversion that description of the invention and accompanying drawing content are made, or directly or indirectly it is used in other correlations
Technical field, it is included within the scope of the present invention.
Claims (14)
1. a kind of preparation method of package substrate, it is characterised in that methods described includes：
Silicon Wafer basic unit is provided, Silicon Wafer basic unit side is provided with pad；
The first wiring layer again is formed backwards to the side of the pad in Silicon Wafer basic unit, wherein, the pad and described first is again
Wiring layer electrically connects.
2. according to the method for claim 1, it is characterised in that methods described also includes：It is provided with the glass-base
The pad side forms the second wiring layer again, wherein, described second again wiring layer electrically connected with the pad.
3. according to the method for claim 2, it is characterised in that wiring layer includes before again for the formation described first：
Set the state of the Silicon Wafer basic unit to make it have the side of the pad and be located at lower section；
Silicon hole is formed in the position back to the pad of the Silicon Wafer basic unit.
4. according to the method for claim 3, it is characterised in that
It is described to include before the position back to the pad of the Silicon Wafer basic unit forms silicon hole：Grind the silicon wafer
Physa layer is back to the side of the pad, to cause the thickness of the Silicon Wafer basic unit to be less than or equal to predetermined thickness.
5. according to the method for claim 3, it is characterised in that
The offer Silicon Wafer basic unit includes：In the Silicon Wafer basic unit reinforcing plate is bonded back to the side of the pad；
It is described to include before the position back to the pad of the Silicon Wafer basic unit forms silicon hole：Remove the reinforcement
Plate.
6. according to the method for claim 2, it is characterised in that described that the Silicon Wafer basic unit is provided with the pad one
Side forms the described second wiring layer again, including：
The side that the pad is provided with the Silicon Wafer basic unit forms the first passivation layer, and corresponding in first passivation layer
The position of the pad sets the first opening；
In first passivation layer the first Seed Layer is formed back to the surface of the Silicon Wafer basic unit；
The first mask layer is formed back to the surface of the Silicon Wafer basic unit in first Seed Layer, and in first mask layer
The position of the corresponding pad sets the second opening；
The described second wiring layer again is formed in the described second opening；
Remove first mask layer and described second the first Seed Layer beyond wiring layer again；
Wherein, wiring layer electrically connects again for the pad, first Seed Layer, described second.
7. according to the method for claim 6, it is characterised in that described to form the described second cloth again in the Silicon Wafer basic unit
After line layer, including：Described second again wiring layer at least re-form wiring layer again and again back to the side of the Silicon Wafer basic unit；
Described second again wiring layer at least re-form again and again wiring layer back to the side of the Silicon Wafer basic unit and include：
Described second again wiring layer form the first dielectric layer back to the surface of the Silicon Wafer basic unit, and in first dielectric
3rd opening is set on layer；
In first dielectric layer second of sublayer is formed back to the surface of the Silicon Wafer basic unit；
The second mask layer is formed back to the surface of the Silicon Wafer basic unit in second of sublayer, and in second mask layer
4th opening is set；
The 3rd wiring layer again is formed in the described 4th opening；
Remove second mask layer and the described 3rd second of sublayer beyond wiring layer again；
Wherein, the described second wiring layer electrical connection again of wiring layer, second of sublayer, the described 3rd again.
8. according to the method for claim 1, it is characterised in that the side shape in the Silicon Wafer basic unit backwards to the pad
Into described first again wiring layer include：
The 3rd mask layer is formed back to the side of the pad in the Silicon Wafer basic unit, and institute is corresponded in the 3rd mask layer
The position for stating pad forms the 5th opening；
In the 3rd mask layer the third sublayer is formed back to the surface of the Silicon Wafer basic unit；
The 4th mask layer is formed back to the surface of the Silicon Wafer basic unit in the third described sublayer, and in the 4th mask layer
It is upper to form the 6th opening；
The described first wiring layer again is formed in the described 6th opening；
Remove the 4th mask layer and described first the third sublayer beyond wiring layer again；Wherein, the described first cloth again
Line layer, the third described sublayer electrically connect with the pad；
Described first again wiring layer back to the Silicon Wafer basic unit surface set the first barrier layer, and described first stop
The 7th opening is formed on layer.
9. a kind of package substrate, it is characterised in that the package substrate includes：
The wiring layer again of Silicon Wafer basic unit, pad and first, wherein, the pad is arranged at Silicon Wafer basic unit side, described
First again wiring layer be arranged at the opposite side of the Silicon Wafer basic unit, the pad and described first again wiring layer electrically connect.
10. package substrate according to claim 9, it is characterised in that
The package substrate also includes the second wiring layer again, described second again wiring layer be arranged on the pad and electrically connect
The pad.
11. package substrate according to claim 9, it is characterised in that
The thickness of the Silicon Wafer basic unit is less than or equal to predetermined thickness；The Silicon Wafer basic unit is formed back to the side of the pad
Have silicon hole, the position of pad described in the position correspondence of the silicon hole, with cause described first again wiring layer pass through the silicon
Through hole electrically connects with the pad.
12. package substrate according to claim 9, it is characterised in that remove the side of the pad of the Silicon Wafer basic unit
Including second, wiring layer, the package substrate also include again：
First passivation layer, the pad side and described second of the Silicon Wafer basic unit is arranged at again between wiring layer, and institute
State the first passivation layer and correspond to the position of the pad formed with the first opening；
First Seed Layer, first passivation layer and described second is arranged at again between wiring layer；
Wherein, wiring layer electrically connects again for the pad, first Seed Layer, described second.
13. package substrate according to claim 12, it is characterised in that the side of the pad of the Silicon Wafer basic unit
In addition to including second again wiring layer, described second again wiring layer also connected up again including the 3rd back to the side of the Silicon Wafer basic unit
Layer, the package substrate further comprise：
First dielectric layer, it is arranged at the described second wiring layer and the described 3rd again between wiring layer, and first dielectric layer again
On formed with the 3rd opening；
Second of sublayer, first dielectric layer and the described 3rd is arranged at again between wiring layer；
Wherein, the described second wiring layer electrical connection again of wiring layer, second of sublayer, the described 3rd again.
14. package substrate according to claim 9, it is characterised in that the Silicon Wafer basic unit is back to the one of the pad
Except including first, wiring layer, the package substrate also include again for side：
3rd mask layer, the Silicon Wafer basic unit is arranged at back to the side of the pad and described first again between wiring layer,
And the position of the corresponding pad is formed with the 5th opening；
The third sublayer, the 3rd mask layer and described first is arranged at again between wiring layer；Wherein, first again wiring layer,
The third described sublayer, pad electrical connection；
First barrier layer, being arranged at described first, wiring layer is back to the side of the Silicon Wafer basic unit again, and described first stops
Formed with the 7th opening on layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710740315.3A CN107527823A (en) | 2017-08-24 | 2017-08-24 | The preparation method and package substrate of a kind of package substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710740315.3A CN107527823A (en) | 2017-08-24 | 2017-08-24 | The preparation method and package substrate of a kind of package substrate |
Publications (1)
| Publication Number | Publication Date |
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| CN107527823A true CN107527823A (en) | 2017-12-29 |
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| CN201710740315.3A Pending CN107527823A (en) | 2017-08-24 | 2017-08-24 | The preparation method and package substrate of a kind of package substrate |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20130210198A1 (en) * | 2012-02-10 | 2013-08-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Process for forming semiconductor structure |
| CN103258803A (en) * | 2012-02-15 | 2013-08-21 | 日月光半导体制造股份有限公司 | Semiconductor device and method for manufacturing same |
| CN103606542A (en) * | 2013-11-30 | 2014-02-26 | 华进半导体封装先导技术研发中心有限公司 | TSV metal interconnection structure and manufacturing method thereof |
| CN105470235A (en) * | 2014-08-12 | 2016-04-06 | 矽品精密工业股份有限公司 | Interposer and method of manufacturing the same |
| US20170229380A1 (en) * | 2016-02-08 | 2017-08-10 | Mitsubishi Electric Corporation | Semiconductor device |
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2017
- 2017-08-24 CN CN201710740315.3A patent/CN107527823A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20130210198A1 (en) * | 2012-02-10 | 2013-08-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Process for forming semiconductor structure |
| CN103258803A (en) * | 2012-02-15 | 2013-08-21 | 日月光半导体制造股份有限公司 | Semiconductor device and method for manufacturing same |
| CN103606542A (en) * | 2013-11-30 | 2014-02-26 | 华进半导体封装先导技术研发中心有限公司 | TSV metal interconnection structure and manufacturing method thereof |
| CN105470235A (en) * | 2014-08-12 | 2016-04-06 | 矽品精密工业股份有限公司 | Interposer and method of manufacturing the same |
| US20170229380A1 (en) * | 2016-02-08 | 2017-08-10 | Mitsubishi Electric Corporation | Semiconductor device |
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Application publication date: 20171229 |