CN107526695A - NVMe configuration spaces implementation method and device - Google Patents
NVMe configuration spaces implementation method and device Download PDFInfo
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- CN107526695A CN107526695A CN201610443715.3A CN201610443715A CN107526695A CN 107526695 A CN107526695 A CN 107526695A CN 201610443715 A CN201610443715 A CN 201610443715A CN 107526695 A CN107526695 A CN 107526695A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
Abstract
Provide NVMe configuration spaces implementation method and device.The method of the access NMVe controller registers of offer, including：Identification accesses the access request of the storage space of PCIe device；Determine that the access request accesses NVMe controller registers according to the address of the access request, wherein NVMe controllers register includes first kind register, doorbell register and/or equipment vendor's special register, and wherein first kind register occupies the preset range in memory register space；If the access request accesses first kind register, generate register access message and register access message is sent to CPU, wherein the register access message includes controller register address.
Description
Technical field
The present invention relates to NVMe controllers, in particular it relates to controller register (the Cont roller in NVMe agreements
Registers)。
Background technology
Controller register (the Controller Register, referring also to " NVM Express defined in NVMe agreements
Revision 1.2 " (calling NVMe agreements in the following text) the 3rd chapter, on November 3rd, 2014).NVMe controllers are being realized based on PCIe protocol
When, NVMe controller registers are mapped to the storage space (Memory Space) of PCIe device.In NVMe agreements,
PCIe registers MLBAR and MUBAR (register BAR0 and BAR1 in PCIe protocol) is defined for providing NVMe controllers
The storage space (herein referred to as memory register space) of register.
Except PCIe protocol, NVMe agreements can be realized based on other bus protocols.In bus protocol, equipment provides can quilt
The storage space (Memory Space, or memory register space) that other bus physicals access, and NVMe is controlled
Device register mappings are to storage space.So as to access NVMe controller registers, be stored by being accessed in bus protocol
Device space is realized.
Main frame (Host) or other bus physicals are able to access that controller register according to NVMe agreements, if but should also follow
Dry constraint.For example, Host can not simultaneously access equipment two or more controller registers；Retained register is posted
The bit being retained in storage is read-only, is being read out return 0.
Controller register includes the register of different purposes.Referring to Fig. 1, control register is illustrated in storage space
In layout.According to NVMe agreements, using PCIe protocol as bus protocol exemplified by, in the preceding 4K of the storage space of PCIe device
The register (being referred to as attribute/control register in the disclosure) that byte (address realm 0-0x0FFF) provides is used to describe controller
Base attribute, such as controller ability, version, command queue base address, or for providing the control port to controller.
Start the doorbell register (Doorbell registers) of storage command queue in the 0x1000 addresses of storage space, posted in doorbell
Special (Vendor Specific) information of storage space storage device business after storage.
Controller register has a polytype (Type), such as the version definition of NVMe agreements 1.2 read-only type (RO),
Read-write type (RW), RW1S types and RW1C types.In other versions of NVMe agreements, it is also possible to define other controllers
Register type.RW1S types are meant that the register is readable writeable, when being written into, mean step-by-step to certain one writing
The mask of interrupt vector is set, and writes " 0 " and does not act on then；When being read, the mask value of current interrupt vector (rather than post
The value of storage) read.RW1C types are meant that the register is readable writeable, in write-in, mean to certain one writing
The mask of bit clear interrupt vector, and write " 0 " and do not act on then；When being read, the mask value of current interrupt vector (and
The value of non-register) read.
The content of the invention
However, NVMe agreements do not define how to realize controller register in the controller.The visit of controller register
The mode of asking is not limited to the read/write operation of register, and for retained register, the register of specific type, it is special to have
Access mode.NVMe agreements are developing rapidly, and current controller register implementations need meet the needs of agreement evolution.
According to the first aspect of the invention, there is provided first according to a first aspect of the present invention accesses the deposit of NMVe controllers
The method of device, including：Identification accesses the access request of the storage space of PCIe device；It is true according to the address of the access request
The fixed access request accesses NVMe controller registers, and wherein NVMe controllers register includes first kind register, doorbell
Register and/or equipment vendor's special register, wherein first kind register occupy the preset range in memory register space；If
The access request accesses first kind register, generates register access message and register access message is sent into CPU, its
Described in register access message include controller register address.
The method that first according to the first aspect of the invention accesses NMVe controller registers, there is provided according to the present invention
The method that the second of first aspect accesses NMVe controller registers, in addition to：If the access request accesses doorbell register,
According to the address of the access request, the memory of the PCIe device is accessed.
The method that first or second according to the first aspect of the invention accesses NMVe controller registers, there is provided according to
The method that the 3rd of first aspect present invention accesses NMVe controller registers, in addition to：The CPU is in response to receiving register
Message is accessed, the controller register address according to the register access message identifies the class of accessed first kind register
Type, and according to NVMe protocol definitions the type first kind register access mode, handle the register access and disappear
Breath.
First according to the first aspect of the invention to the 3rd access NMVe controller registers method, there is provided according to
The method that the 4th of first aspect present invention accesses NMVe controller registers, in addition to, if the access request access equipment
Business's special register, according to the address of the access request, access the memory of the PCIe device.
The method that first to fourth according to the first aspect of the invention accesses NMVe controller registers, there is provided according to
The method that the 5th of first aspect present invention accesses NMVe controller registers, the wherein storage space of PCIe device are specified
Address realm is mapped to the address space of the memory of PCIe device.
First according to the first aspect of the invention to the 5th access NMVe controller registers method, there is provided according to
The method that the 6th of first aspect present invention accesses NMVe controller registers, wherein the CPU is according to having different memory
Multiple register access message of space address, access the identical address of the memory of the PCIe device.
First according to the first aspect of the invention to the 6th access NMVe controller registers method, there is provided according to
The method that the 6th of seventh aspect present invention accesses NMVe controller registers, in addition to：The CPU is by the register access
The result of message is sent to the sender of the access request.
The method that first according to the first aspect of the invention accesses NMVe controller registers, there is provided according to the present invention
The method that the 8th of first aspect accesses NMVe controller registers, wherein the register access message also includes accessing class
Type, access type instruction will be read out or write to controller register.
According to the second aspect of the invention, there is provided first according to a second aspect of the present invention accesses the deposit of NMVe controllers
The method of device, including：Identification accesses the access request of memory register (Memory Registers)；Please according to the access
The address asked determines that the access request accesses NVMe controller registers；Generation NVMe controller register access message simultaneously will
NVMe controller register access message is sent to CPU, wherein the NVMe controllers register access message includes controller
Register space address.
The method that first according to the second aspect of the invention accesses NMVe controller registers, there is provided according to the present invention
The method that the second of second aspect accesses NMVe controller registers, the CPU visit in response to receiving NVMe controllers register
Message is asked, the NVMe that the controller register space Address Recognition according to the NVMe controllers register access message is accessed
The type of controller register, and according to NVMe protocol definitions the type NVMe controller registers access mode,
Handle the NVMe controllers register access message.
The method that first or second according to the second aspect of the invention accesses NMVe controller registers, there is provided according to
The method that the 3rd of second aspect of the present invention accesses NMVe controller registers, in addition to：If the access request accesses doorbell
Register, according to the access request, access relative with the controller register space address of the access request in memory
The region answered, without sending NVMe controller register access message to the CPU.
The method that first or second according to the second aspect of the invention accesses NMVe controller registers, there is provided according to
The method that the 4th of second aspect of the present invention accesses NMVe controller registers, in addition to：The CPU is in response to receiving NVMe controls
Device register access message processed, the controller register space Address Recognition according to the NVMe controllers register access message
Doorbell register is accessed, according to the controller register space addressed memory.
According to the third aspect of the invention we, there is provided first according to a third aspect of the present invention accesses the deposit of NMVe controllers
The method of device, including：Identification accesses the access request of memory register (Memory Registers)；Please according to the access
The address asked determines that the access request accesses NVMe controller registers, and wherein NVMe controllers register is posted including the first kind
Storage, doorbell register and/or equipment vendor's special register, wherein first kind register occupy the finger in memory register space
Determine address realm；If the access request accesses first kind register, generate register access message and register access disappears
Breath is sent to CPU, wherein the register access message includes controller register address.
According to the fourth aspect of the invention, there is provided the first NVMe controllers according to a fourth aspect of the present invention, including：System
System bus access part, controller register access part, CPU and memory；System bus access component is coupled in outside
Bus simultaneously generates the request of controller register access, the control in response to the storage space access request from system bus
The request of device register access includes first memory address and access type；The controller register access unit response is in receipts
Asked to controller register access, determine that the controller register access request accesses according to the first memory address
First kind register, generation register access information and sending give the CPU；The CPU disappears in response to receiving register access
Breath, the NVMe controller registers that the second memory Address Recognition according to the register access message is accessed, and foundation
The access mode of the NVMe controllers register of NVMe protocol definitions, handles the register access message.
The first NVMe controllers according to the fourth aspect of the invention, there is provided according to a fourth aspect of the present invention second
NVMe controllers, wherein the controller register access part determines that the controller is posted according to the first memory address
Storage access request accesses doorbell register, accesses in the memory with the region that the first memory address is corresponding,
Without accessing message to the CPU transmitter registers.
First according to the fourth aspect of the invention or the 2nd NVMe controller, there is provided according to a fourth aspect of the present invention
3rd NVMe controllers, wherein the result of the register access message is sent to the storage space by the CPU
The sender of access request.
First according to the fourth aspect of the invention is to the 3rd NVMe controllers, there is provided according to a fourth aspect of the present invention
4th NVMe controllers, wherein the controller register access part determines the control according to the first memory address
The request of device register access accesses the first kind register of NVMe controller registers, and generation register access information and sending is given
The CPU；Preceding 4KB of the address realm that wherein first kind register occupies in controller register space.
First according to the fourth aspect of the invention is to the 3rd NVMe controllers, there is provided according to a fourth aspect of the present invention
5th NVMe controllers, wherein multiple second memory addresses of the CPU according to multiple register access message, described in access
The identical address of memory.
First according to the fourth aspect of the invention is to the 5th NVMe controllers, there is provided according to a fourth aspect of the present invention
6th NVMe controllers, wherein the system bus access component is PCIe controller.
According to the fifth aspect of the invention, there is provided the first NVMe controllers according to a fifth aspect of the present invention, including：System
System bus access part, CPU and memory；System bus access component is coupled in external bus, in response to total from system
The storage space access request of line accesses NVMe controller registers, generates NVMe controller register access information and sendings
To the CPU；The CPU is in response to receiving NVMe controller register access message, according to the NVMe controllers register
The NVMe controller registers that the controller storage Address Recognition that accessing message includes is accessed, and according to NVMe protocol definitions
The NVMe controllers register access mode, handle the NVMe controllers register access message.
The first NVMe controllers according to the fifth aspect of the invention, there is provided according to a sixth aspect of the present invention second
NVMe controllers, wherein the system bus access component accesses doorbell register in response to storage space access request, deposit
Memory space access request accesses the memory, without generating NVMe controller register access message.
Brief description of the drawings
When being read together with accompanying drawing, by reference to the detailed description of illustrative embodiment, will be best understood below
The present invention and preferable use pattern and its further objects and advantages, wherein accompanying drawing include：
Fig. 1 illustrates layout of the control register in storage space；
Fig. 2 shows the circuit system block diagram of NVMe controllers according to embodiments of the present invention；
Fig. 3 shows the circuit system block diagram of the NVMe controllers according to further embodiment of this invention；And
Fig. 4 shows the circuit system block diagram of the NVMe controllers according to still another embodiment of the present invention.
Embodiment
Fig. 2 shows the circuit system block diagram of NVMe controllers according to embodiments of the present invention.NVMe controllers include
PCIe PHY modules 210, system bus access modules 220, controller register access module 230, memory 240 and CPU
Subsystem 260.Controller register access module 230 and the equal accessible storage device 240 of the subsystem of cpu subsystem 260.Memory
It is middle to store doorbell (Doorbell) register, special (the Vend or Specific) register of equipment vendor and in controller
The message queue of message is exchanged between register access module 240 and cpu subsystem 260.
Main frame (host) is coupled to equipment by PCIe PHY modules 210.NVMe controllers include PCIe PHY modules
210 and it is coupled to the system bus access modules 220 of PCIe PHY modules 210.PCIe PHY modules 210 are used to handle PCIe
Underlying protocol (such as physical layer).System bus access modules 220 be used for handle PCIe upper-layer protocols (for example, data link layer and/
Or transaction layer).The storage space (memory space) for the access equipment that system bus access modules 220 also send main frame
The request of specific region be converted into including access type, storage space address, and/or to access data (empty for memory
Between read request, include access data；For storage space write request, including access data) controller register access
Request, and it is transmitted to controller register access module 230.Alternatively, system bus access modules 220 are in controller register
The address format (for example, shortening address length) different from storage space address can be used in access request, with more effectively
Indicate accessed controller register.
Controller register access module 230, determine that the request of controller register access will according to storage space address
Access attribute/control register, doorbell register or equipment vendor's special register.Visited for different types of controller register
Ask that request provides different processing modes.
In the release protocols of NVMe 1.2, PCIe registers MLBAR and MUBAR defines to be posted for providing NVMe controllers
The storage space of storage, and the low 4KB of the address space is used for attribute/control register (referring to Fig. 1).
When doorbell register to be accessed or equipment vendor's special register, controller register access module 230 is according to depositing
Access request is write the corresponding storage location in same storage space address of memory 240 or from storage by memory space address
Read in the corresponding storage location in the same storage space address of device data and by system bus access modules 220 (and
PCIe PHY 210) return to main frame.
When access attribute/control register is wanted in the request of controller register access, controller register access module 230
Generate register access message, and the message queue that register access message is inserted in memory.In cpu subsystem 260
One or more CPU have found in the message queue of memory 240 during pending processing message, message to be taken out, it is determined that to access
Attribute/control register and access type, register access message is handled, and will access result it is total by system
Line access modules 230 return to main frame.Cpu subsystem 260 will access disappearing in result insertion memory 240 in one example
Queue is ceased, controller register access module 230 is taken out from message queue accesses result, and passes through system bus access modules
220 return to main frame.
In this way, realize to the various controller register in NVMe agreements, and for controller register not
The realizations such as same type, access constraints are effectively handled.And after NVMe protocol updates, it can be transported by changing in cpu subsystem
Capable program is efficiently adapted to the modification of the access to controller register introduced in new edition agreement.
It is discussed in detail according to an embodiment of the invention with the example of the access of some controller registers below.
(1) main frame read/write submits queue tail pointer doorbell register
As an example, queue tail pointer doorbell register is submitted there are 32 bits, wherein 31:16 bits are retained and are read-only
Type, and 15:00 bit is read-write type.
When host request reads complete 32 of the submission queue doorbell register that PCIe memory space address is 0x1000h
When, system bus module 220 generates the controller register access request for including address 0x1000h and read access type, concurrently
Give controller register access module 230.
Controller register access module 230 identified based on address 0x1000h accessed be submit queue tail pointer
Doorbell register, the submission queue tail pointer corresponding to address 0x1000h is read from the doorbell register memory block of memory 240
Value is simultaneously sent to main frame by system bus access modules 220.In another example, without storage pair in memory 240
Should be in the 31 of address 0x1000h submission queue tail pointer:16 bits, and only store and submit the 15 of queue tail pointer:00 bit,
To save memory space, and by controller register access module 230 when reading submission queue tail pointer, in high position filling 16
Bit 0, to meet NVMe agreements regulation.
When host request writes complete 32 of the submission queue doorbell register that PCIe memory space address is 0x1000h
When, system bus access modules 220 generate the controller deposit for including address 0x1000h, data to be written and write access type
Device access request, and it is sent to controller register access module 230.
Controller register access module 230 identified based on address 0x1000h accessed be submit queue tail pointer
Doorbell register, the doorbell register memory block write-in to memory 240 correspond to address 0x1000h submission queue tail pointer
Value.In another example, correspond to the 31 of address 0x1000h submission queue tail pointer without storage in memory 240:
16 bits, and only write to memory 240 and submit the 15 of queue tail pointer:00 bit, to save memory space.
(2) main frame read/write CAP registers
0x00h-0x07h address realms in PCIe memory space are CAP registers, for indicating NVMe controllers
Ability, 64 bits of CAP registers are read-only type.
When host request reads the CAP registers that PCIe memory space address is 0x00h, system bus access modules
220 generations include address 0x00h, the byte of length 8 and read access type controller register access request, and are sent to control
Device register access module 230.
Controller register access module 230 identifies that accessed is attribute/control register based on address 0x00h,
Generate register access message, and the message queue that register access message is inserted in memory 240.Disappear in register access
Breath includes indicating the information of address 0x00h, the byte of length 8 and read access type.
It is pointed out that the address 0x00h indicated in register access message can ask with controller register access
Address (0x00h) in asking is identical or different in form.For example, the address in the request of controller register access can be PCIe
Storage space address.Address in register access message can also be PCIe memory space address.Controller register
It is mapped to the part in PCIe memory space.In another example, the address in the request of controller register access can
To be PCIe memory space address, and the address indicated in register access message be exclusively used in describe controller register or
The address of attribute/control register.Deposited so as to which the address indicated in register access message can be less than controller in size
Address in device access request is (for example, the address indicated in register access message is from the low of PCIe memory space address
Position).
CPU determines the CAP registers to be accessed when handling message queue, according to address 0x00h, and will be deposited with CAP
64 bit informations of instruction NVMe controller abilities are sent to main frame by system bus access modules 220 corresponding to device.As
64 bit informations of instruction NVMe controller abilities corresponding with CAP registers are write memory 240 by another example, CPU
In message queue.Controller register access module 230 detects that CPU have updated message queue, is posted being updated with CAP
64 bit informations of instruction NVMe controller abilities are sent to main frame by system bus access modules 220 corresponding to storage.
When host request writes the CAP registers that PCIe memory space address is 0x00h, system bus access modules
220 generations include address 0x00h, the controller register access request of 8 byte datas to be write and write access type, concurrently
Give controller register access module 230.
Controller register access module 230 identifies that accessed is attribute/control register based on address 0x00h,
Generate register access message, and the message queue that register access message is inserted in memory 240.Disappear in register access
Breath includes indicating address 0x00h, 8 byte datas to be write and write access type information.
For CPU260 when handling message queue, what foundation address 0x00h determined to be accessed is CAP registers, and is accessed
Type is write-in.CPU260 has found that CAP registers are read-only types, then ignores the message.Alternatively, CPU 260 is generated different
Normal message, and main frame is sent to by system bus access modules 220, to indicate host implementation to the non-of controller register
Method operates.
(3) main frame read/write is retained (Reserved) register
The 0x18h-0x1Bh address realms in PCIe memory space, it is retained in the version of NVMe agreements 1.2.
When host request reads the register that PCIe memory space address is 0x18h, system bus access modules 220 are given birth to
Into the controller register access request including address 0x18h and read access type, and it is sent to controller register access mould
Block 230.
Controller register access module 230 identifies that accessed is attribute/control register based on address 0x18h,
Generate register access message, and the message queue that register access message is inserted in memory 240.Disappear in register access
Breath includes indicating the information of address 0x18h and read access type.
For CPU 260 when handling message queue, what foundation address 0x18h determined to be accessed is retained register, and
The access result of full 0 is sent to main frame by system bus access modules 220.As another example, CPU is by the visit of full 0
Ask the message queue in result write-in memory 240.Controller register access module 230 detects that CPU have updated message team
Row, main frame is sent to by the access result for the full 0 being updated by system bus access modules 220.
When host request writes the register that PCIe memory space address is 0x18h, system bus access modules 220 are given birth to
Into the controller register access request including address 0x18h, the data to be write and write access type, and it is sent to controller
Register access module 230.
Controller register access module 230 identifies that accessed is attribute/control register based on address 0x18h,
Generate register access message, and the message queue that register access message is inserted in memory 240.Disappear in register access
Breath includes indicating address 0x18h, the data to be write and write access type information.
For CPU 260 when handling message queue, what foundation address 0x18h determined to be accessed is retained register, and
And access type is write-in, then ignores the message.Alternatively, CPU 260 generates unexpected message, and is accessed by system bus
Module 220 is sent to main frame, to indicate illegal operation of the host implementation to controller register.
(4) main frame read/write INTMS registers
The 0x0Ch-0x0Fh address realms in PCIe memory space are INTMS registers.INTMS registers are used to set
Interrupt mask, and there is special access type (RW1S).When INTMS registers are written into, if INTMS registers is a certain
Bit is write " 1 ", interruption corresponding to the bit is shielded.When INTMS registers are read, the value of reading indicates current interruption
Mask.
When host request reads the register that PCIe memory space address is 0x0Ch, system bus access modules 220 are given birth to
Into the controller register access request including address 0x0Ch and read access type, and it is sent to controller register access mould
Block 230.
Controller register access module 230 identifies that accessed is attribute/control register based on address 0x0Ch,
Generate register access message, and the message queue that register access message is inserted in memory 240.Disappear in register access
Breath includes indicating the information of address 0x0Ch and read access type.
What CPU 260 determined to be accessed when handling message queue, according to address 0x0Ch is INTMS registers, CPU
260 obtain the interrupt mask of Current interrupt vector, will by corresponding bit set of the interruption shielded in INTMS registers
Corresponding bit reset of the interruption not shielded in INTMS registers, and result is passed through into system bus access modules 220
It is sent to main frame.The message team for writing the access result of INTMS registers in memory 240 as another example, CPU
Row.Controller register access module 230 detects that CPU have updated message queue, by the access for the INTMS registers being updated
As a result it is sent to main frame by system bus access modules 220.
When 0x0001 write-in PCIe memory space address is 0x0Ch register by host request, system bus is visited
Ask module generation and include address 0x0Ch, the controller register access request of the data 0x0001 to be write and write access type,
And it is sent to controller register access module 230.
Controller register access module 230 identifies that accessed is attribute/control register based on address 0x0Ch,
Generate register access message, and the message queue that register access message is inserted in memory 240.Disappear in register access
Breath includes indicating address 0x0Ch, the data 0x0001 to be write and write access type information.
For CPU 260 when handling message queue, what foundation address 0x0Ch determined to be accessed is INTMS registers, and is visited
It is write-in to ask type.CPU 260 is according to numerical value 0x0001h to be written, by interruption masking corresponding with INTMS lowest order.
Because attribute/control register in NVMe controller registers has a variety of implications, form, access control rule
(read-only/only writing/is retained) and control action, in an embodiment of the present invention, controller register 230 are identified to category
The access of property/control register, and register access message is sent to CPU 260, handled by CPU 260 to attribute/control
The access of register.In further example, when there are multiple reservation registers of different memory address to be read, CPU
260 provide identical value (0) as response, thus single storage location can be provided in memory 240 and is posted to store reservation
The response of storage, and respond the access to the reservation register with different memory address with the response.Another
In individual example, multiple NVMe controllers are provided in NVMe equipment, each NVMe controllers have respective controller register, respectively
Some controller registers of individual NVMe controllers can have identical value (such as CAP registers).The accessible storages of CPU 260
The single position of device 240 responds access of the main frame to the controller register of multiple NVMe controllers.
In another embodiment in accordance with the invention, by the system bus access modules 220 in Fig. 2 and controller register
Access modules 230 integrate (also referred to as system bus access modules).Be integrated with controller register access module is
The PCIe memory space address for the memory access request that system bus access module identification main frame is sent, for access attribute/
The memory access request of control register, register access message is generated, and be sent to CPU, processing register is passed through by CPU
Message is accessed to respond the attribute of main frame/control register access request.And sent in system bus access modules identification main frame
Memory access request access doorbell register and/or during equipment vendor's special register, the corresponding doorbell for accessing memory is posted
Storage memory block and/or equipment vendor's special register memory block.
Fig. 3 shows the circuit system block diagram of the NVMe controllers according to further embodiment of this invention.
Main frame (host) is coupled to equipment by PCIe PHY 310.NVMe controllers include PCIe PHY 310 and
It is coupled to PCIe PHY 310 system bus access modules 320.System bus access modules 320 set the access that main frame is sent
The request of standby storage space is converted into including access type, storage space address, and/or accesses data (for storage
Device space read request, do not include accessing data；For storage space write request, including access data) controller register
Access request, and it is transmitted to controller register access module 330.
Controller register access module 330, determine that the request of controller register access will according to storage space address
Access attribute/control register, doorbell register or equipment vendor's special register.
When doorbell register to be accessed or equipment vendor's special register, controller register access module 330 is according to depositing
Access request is write the corresponding storage location in same storage space address of memory 340 or from storage by memory space address
Data are read in the corresponding storage location in the same storage space address of device 340 and are returned by system bus access modules 320
Back to main frame.
When wanting access attribute/control register, controller register access module 330 generates register access message,
And register access message is sent to CPU 360 by message queue 365.Message queue 365 is message distribution circuit.Control
Device register access module 330 is by message queue 365 by register access messaging to CPU 360.In message queue 365
When having message to consign to CPU360, interrupt signal can be produced to CPU, instruction CPU 360 handles the message in message 365.Make
For another example, the polling message queues 365 of CPU 360, disappearing for CPU 360 is delivered in queue 365 to find and obtain
Breath.
One or more of cpu subsystem 360 CPU takes out message from message queue 365, it is determined that the attribute to be accessed/
Control register and access type, and return to main frame by system bus access modules 320 by result is accessed.
And visited for the other kinds of controller register access outside attribute/control register, controller register
Ask in the direct access to memory 340 of module 330.
In this way, the access to the various controller register in NVMe agreements is realized according to an embodiment of the invention,
And the realizations such as different type, access constraints for controller register are effectively handled.And after NVMe protocol updates, lead to
The program run is crossed in modification cpu subsystem 360 to be efficiently adapted to the visit to controller register introduced in new edition agreement
The modification asked.
In addition to NVMe controllers are realized on PCIe protocol, NVMe controllers can also be realized in other agreements.
Through being based on the communication protocols such as Ethernet (Ethernet), FC (Fibre Channel optical fiber is sensible), IB (InfiniBand) in exploitation
The NVMe controllers of view, also in the NVMe controllers of transport layer protocol of the exploitation based on such as RDMA.In these NVMe controllers
In realize embodiments of the invention.By identifying to the reference address of storage space, identify that to be accessed is to be mapped to deposit
The controller register of memory space.And by controller register access module (Fig. 2, controller register access module 230,
Or Fig. 3, controller register access module 330) access of attribute/control register is sent to CPU by message queue,
Access to attribute/control register is handled by CPU, and for doorbell register and/or equipment vendor's special register, depositing
Mapping one by one to doorbell register and/or equipment vendor's special register is provided in reservoir, and by controller register access mould
Block access memory responds the access to doorbell register and/or equipment vendor's special register., will be right in another example
The access of doorbell register and/or equipment vendor's special register is sent to CPU also by message queue, is handled by CPU to this
The access of a little controller registers.
Fig. 4 shows the circuit system block diagram of the NVMe controllers according to still another embodiment of the present invention.In Fig. 4 example
In son, node (Node) is linked together by network.Node can be main frame, server, NVMe equipment etc..External node
NVMe equipment according to embodiments of the present invention is coupled to by physical layer block (for example, Ethernet PHY 410).At agreement
The Treated Base agreement of module 420 (for example, IP layers) is managed, and NVMe controls will be sent to the access request of NVMe controller registers
Device register access module 430 processed.To the access requests of NVMe controller registers with including access type, storage space
Location, and/or access data (for read request, do not include accessing data；For write request, including access data).
Controller register access module 430, determine that the request of controller register access will according to storage space address
Access attribute/control register, doorbell register or equipment vendor's special register.
When doorbell register to be accessed or equipment vendor's special register, controller register access module 430 will access
Request write-in memory 440 reads the section that data and being returned to by protocol process module 420 send request from memory 440
Point.
When wanting access attribute/control register, controller register access module 430 generates attribute/control register
Message is accessed, and attribute/control register is accessed into message and is sent to message queue 465.One or more of cpu subsystem
CPU takes out message from message queue 465, it is determined that the attribute/control register and access type to be accessed, and result will be accessed
The node for sending request is returned to by protocol process module 420.In another example, message is stored in memory 440
Queue, cpu subsystem 460 obtain message-queue entry from memory 440.
Although the example of present invention reference is described, it is intended merely to the purpose explained rather than the limit to the present invention
System, the change to embodiment, increase and/or deletion can be made without departing from the scope of the present invention.
It is involved by these embodiments, from the description above and in the field that benefits of the teaching that is presented in associated accompanying drawing
Technical staff will be recognized that many modifications of the invention recorded here and other embodiment.It should therefore be understood that this hair
It is bright to be not limited to disclosed embodiment, it is intended to include modification and other embodiment in the scope of the appended claims
It is interior.Although employing specific term herein, them are used only on general significance and describing significance and not is
The purpose of limitation and use.
Claims (10)
1. a kind of method of access NMVe controller registers, including：
Identification accesses the access request of the storage space of PCIe device；
Determine that the access request accesses NVMe controller registers, wherein NVMe controllers according to the address of the access request
Register includes first kind register, doorbell register and/or equipment vendor's special register, and wherein first kind register, which occupies, deposits
The preset range in memory register space；
If the access request accesses first kind register, generate register access message and be sent to register access message
CPU, wherein the register access message includes controller register address.
2. the method according to claim 11, in addition to：
If the access request accesses doorbell register, according to the address of the access request, depositing for the PCIe device is accessed
Reservoir.
3. according to the method described in one of claim 1-2, in addition to：
The CPU is in response to receiving register access message, the controller register address according to the register access message
The type of the accessed first kind register of identification, and according to NVMe protocol definitions the type first kind register visit
Mode is asked, handles the register access message.
4. a kind of method of access NMVe controller registers, including：
Identification accesses the access request of memory register (Memory Registers)；
Determine that the access request accesses NVMe controller registers according to the address of the access request；
NVMe controller register access message is simultaneously sent to CPU by generation NVMe controller register access message, wherein institute
Stating NVMe controller register access message includes controller register space address.
5. the method according to claim 11, in addition to：
The CPU disappears in response to receiving NVMe controller register access message according to the NVMe controllers register access
The type for the NVMe controller registers that the controller register space Address Recognition of breath is accessed, and according to NVMe protocol definitions
The type NVMe controller registers access mode, handle the NVMe controllers register access message.
6. according to the method described in one of claim 4-5, in addition to：
If the access request accesses doorbell register, according to the access request, access in memory with the access request
The corresponding region in controller register space address, without sending NVMe controller register access message to the CPU.
7. a kind of NVMe controllers, including：System bus access component, controller register access part, CPU and storage
Device；
System bus access component is coupled in external bus and given birth in response to the storage space access request from system bus
Asked into controller register access, the controller register access request includes first memory address and access type；
The controller register access unit response is in receiving the request of controller register access, according to the first memory address
Determine that the controller register access request accesses first kind register, generation register access information and sending is to described
CPU；
The CPU in response to receiving register access message, know by the second memory address according to the register access message
Other accessed NVMe controller registers, and the access side of the NVMe controllers register according to NVMe protocol definitions
Formula, handle the register access message.
8. NVMe controllers according to claim 7, wherein
The controller register access part determines that the controller register access please according to the first memory address
Access doorbell register is sought, is accessed in the memory with the region that the first memory address is corresponding, without to described
CPU transmitter registers access message.
9. the NVMe controllers according to one of claim 7-8, wherein
The controller register access part determines that the controller register access please according to the first memory address
The first kind register for accessing NVMe controller registers is sought, generation register access information and sending gives the CPU；Wherein
Preset range of the address realm that a kind of register occupies in controller register space.
10. a kind of NVMe controllers, including：System bus access component, CPU and memory；
System bus access component is coupled in external bus, is accessed in response to the storage space access request from system bus
NVMe controller registers, generation NVMe controller register access information and sending give the CPU；
The CPU disappears in response to receiving NVMe controller register access message according to the NVMe controllers register access
The controller register address that ceasing includes identifies the first accessed NVMe controller registers, and according to NVMe protocol definitions
The access mode of the first NVMe controller registers, handle the NVMe controllers register access message.
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