CN107507617B - System and method for realizing DSD audio hard solution - Google Patents
System and method for realizing DSD audio hard solution Download PDFInfo
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Abstract
The invention discloses a system and a method for realizing DSD audio hard solution, wherein the system comprises: the application processor module is used for acquiring and analyzing original audio data, and sending data bus addresses and data parameters and audio data in analysis results to the audio processing module through a data bus; the data parameters comprise data sampling rate, bit number, code stream, whether the format is DSD format, DSD format and the mode that the back-end digital-to-analog conversion module needs to support; the audio processing module reads data parameters and audio data according to the data bus address, decodes the audio data according to the data parameters, and sends the decoded audio data to the digital-to-analog conversion module; the digital-to-analog conversion module is used for converting the decoded audio data into analog audio signals and outputting the analog audio signals; the asynchronous dual-crystal oscillator clock is used for outputting a clock signal to the audio processing module. The invention realizes the DSD audio playing supporting all specifications, realizes the accurate playing of the full sampling rate and achieves good sound effect.
Description
Technical Field
The invention relates to the technical field of audio decoding, in particular to a system and a method for realizing DSD audio hard decoding.
Background
With the rapid development of electronic information technology, music is inseparable in people's life, and people have higher and higher requirements for tone quality. Currently, a commonly used music playing method is to decode various audio formats into PCM (Pulse-Code Modulation) for playing, but in order to obtain better sound quality, sony and philips have developed DSD (Direct Stream Digital) format audio in 1996, which is implemented based on PDM (Pulse-density Modulation) Pulse density Modulation, and an analog audio signal is represented by density, and the PDM has a precision of 1bit per sampling, so that a more excellent sound effect can be provided, and the DSD has very small quantization noise and a very high signal-to-noise ratio, so that the quality is relatively stable.
There are three methods for implementing DSD audio in the prior art: one is to realize the playing of the DSD audio by a USB xmos mode, but xmos has large power consumption, large volume and high cost, is not suitable for a portable HiFi player, and needs to realize the transmission of the DSD through a USB interface, and many MCUs have few USB interfaces and are not strong in universality; the second method adopts standard I2S (Inter-IC Sound) bus (also called as integrated circuit built-in audio bus) to transmit audio data, which decodes DSD audio into PCM data through a processor and sends the PCM data to a digital-to-analog converter for playing, because the PCM data is converted into PCM data, the advantage of direct bit stream digital data cannot be exerted, and adopts MCU for decoding, which has high requirements on MCU performance and generally can only support decoding in DSD128 format at the highest, DSD256 and DSD512 cannot decode, and cannot play native DSD audio; the third is that, by means of a dop (DSD over PCM), the MCU packs and encapsulates the DSD data, which is disguised as PCM data of the I2S standard for transmission, and then the back-end DAC decodes the DSD data for playing, although this method does not perform format conversion from DSD to PCM, because the MCU does not support data transmission of a DSD audio stream higher than the sampling rate (2.8224MHz), only DSD64, 2.8224MHz and DSD128, and 2.8224MHz 32bit, higher DSD music playing with a DSD256 sampling rate of 11.2896MHz and a DSD512 sampling rate of 22.5792MHz cannot be supported, and a DSD Native (Native DSD) mode cannot be supported, which can support DSD incompletion and higher DSD audio playing and Native DSD mode cannot be supported.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a system and a method for realizing DSD audio hard solution, which can support DSD audio playing of all specifications and support full sampling rate.
In order to solve the technical problems, the invention adopts the following technical scheme:
in one aspect, a system for implementing DSD audio hard solution is provided, the system comprising an application processor module, an audio processing module connected to the application processing module via a data bus, a digital-to-analog conversion module, and an asynchronous dual-crystal oscillator clock for providing clock signals to the audio processing module;
the application processor module is used for acquiring and analyzing original audio data and sending data bus addresses and data parameters and audio data in analysis results to the audio processing module; the data parameters comprise data sampling rate, bit number, code stream, whether the data is in DSD format, DSD format and mode that the back-end digital-to-analog conversion module needs to support, and the audio data is DSD native data in DSD format or PCM data in non-DSD format decoded by the application processor module;
the audio processing module reads the data parameters and the audio data according to the data bus address, decodes the audio data according to the data parameters, and sends the decoded audio data to the digital-to-analog conversion module;
and the digital-to-analog conversion module is used for converting the decoded audio data sent by the audio processing module into an analog audio signal and outputting the analog audio signal.
Wherein the parsing the raw audio data comprises: if the original audio data is audio data in a non-DSD format, decoding the original audio data into PCM data, and analyzing the sampling rate, the bit number and the code stream of the PCM data; if the original audio data is audio data in a DSD format, namely DSD original data, the DSD format of the DSD original data is analyzed.
Wherein, the decoding the audio data according to the data parameter and sending the decoded audio data to the digital-to-analog conversion module includes:
if the DSD format in the data parameters is a non-DSD format, namely the audio data is PCM data, sending the PCM data to a digital-to-analog conversion module, and setting the digital-to-analog conversion module according to the sampling rate, the bit number and the code stream in the data parameters;
if the data parameters are in the DSD format or not, namely the audio data are DSD native data, if the mode needing to be supported by the back-end digital-to-analog conversion module is the DSD native mode, transmitting the DSD native data to the digital-to-analog conversion module according to bits; if the mode needing to be supported by the back-end digital-to-analog conversion module is a DoP mode, packaging DSD (digital-to-analog conversion) native data into DoP data according to a DoP protocol, wherein the DoP data consists of data parameters and DSD native data, and outputting the DoP data to the digital-to-analog conversion module; and if the mode which needs to be supported by the back-end digital-to-analog conversion module is a PCM mode, decoding the DSD native data into PCM data according to a DSD coding mode algorithm, converting the PCM data into a corresponding sampling rate, bit number and code stream according to a DSD format in the data parameters, sending the PCM data, the sampling rate, the bit number and the code stream to the digital-to-analog conversion module, and setting the digital-to-analog conversion module according to the sampling rate and the code stream.
The audio processing module is further used for converting the PCM data, the DSD native data or the DoP data sent to the digital-to-analog conversion module into spdif format and outputting the converted data.
The asynchronous dual-crystal oscillator clock comprises a first crystal oscillator of 22.5792MHz and a second crystal oscillator of 24.576 MHz; or a first crystal oscillator of 45.1584MHz and a second crystal oscillator of 49.152 MHz.
The audio processing module is realized based on an FPGA; the application processor module is connected with the audio processing module through a high-speed data bus.
The sending the data bus address and the data parameter and the audio data in the analysis result to the audio processing module specifically includes:
packaging the analysis result of the original audio data according to a self-defined data bus transmission protocol format, wherein the data bus transmission protocol format is as follows: data bus address + data parameter + audio data;
transmitting the packaged data to an audio processing module according to a data bus transmission protocol and a data bus address;
the audio processing module reads the data parameter and the audio data according to the data bus address, and the audio processing module comprises: and the audio processing module reads the packaged data according to the data bus address and analyzes the packaged data according to a data bus transmission protocol.
Another aspect provides a method of implementing a DSD audio hard solution, the method including:
the application processor module acquires and analyzes original audio data and sends data bus addresses and data parameters and audio data in analysis results to the audio processing module; the data parameters comprise data sampling rate, bit number, code stream, whether the data is in DSD format, DSD format and mode that the back-end digital-to-analog conversion module needs to support, and the audio data is DSD native data in DSD format or PCM data in non-DSD format decoded by the application processor module;
the audio processing module reads the data parameters and the audio data according to the data bus address, decodes the audio data according to the data parameters, and sends the decoded audio data to the digital-to-analog conversion module;
the digital-to-analog conversion module converts the decoded audio data sent by the audio processing module into an analog audio signal and outputs the analog audio signal;
the application processor module is connected with the audio processing module through a data bus; the clock signal of the audio processing module is provided by an asynchronous double-crystal clock.
Wherein the parsing the raw audio data comprises: if the original audio data is audio data in a non-DSD format, decoding the original audio data into PCM data, and analyzing the sampling rate, the bit number and the code stream of the PCM data; if the original audio data is audio data in a DSD format, namely DSD original data, the DSD format of the DSD original data is analyzed.
Wherein, the decoding the audio data according to the data parameter and sending the decoded audio data to the digital-to-analog conversion module includes:
if the DSD format in the data parameters is a non-DSD format, namely the audio data is PCM data, sending the PCM data to a digital-to-analog conversion module, and setting the digital-to-analog conversion module according to the sampling rate, the bit number and the code stream in the data parameters;
if the data parameters are in the DSD format or not, namely the audio data are DSD native data, if the mode needing to be supported by the back-end digital-to-analog conversion module is the DSD native mode, transmitting the DSD native data to the digital-to-analog conversion module according to bits; if the mode needing to be supported by the back-end digital-to-analog conversion module is a DoP mode, packaging DSD (digital-to-analog conversion) native data into DoP data according to a DoP protocol, wherein the DoP data consists of data parameters and DSD native data, and outputting the DoP data to the digital-to-analog conversion module; and if the mode which needs to be supported by the back-end digital-to-analog conversion module is a PCM mode, decoding the DSD native data into PCM data according to a DSD coding mode algorithm, converting the PCM data into a corresponding sampling rate, bit number and code stream according to a DSD format in the data parameters, sending the PCM data, the sampling rate, the bit number and the code stream to the digital-to-analog conversion module, and setting the digital-to-analog conversion module according to the sampling rate and the code stream.
Compared with the prior art, the invention has the beneficial effects that: the system for realizing DSD audio hard decoding provided by the invention provides a clock signal for the processing module through the asynchronous double-crystal oscillator clock, so that the support of full sampling rate is realized, the clock is more accurate, the effect is better, the data bus is adopted to transmit audio data, the advantage of DSD direct bit stream digital data is exerted, the DSD audio play of all specifications is realized, the accurate play of full sampling rate is realized, and a good sound effect is achieved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the contents of the embodiments of the present invention and the drawings without creative efforts.
Fig. 1 is a block diagram illustrating an embodiment of a system for implementing DSD audio hard decoding according to an embodiment of the present invention.
Fig. 2 is a flowchart of a method of implementing a DSD audio hard solution according to an embodiment of the present invention.
Detailed Description
In order to make the technical problems solved, technical solutions adopted and technical effects achieved by the present invention clearer, the technical solutions of the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
A system for implementing DSD audio hard-decoding according to an embodiment of the present invention is described in further detail below with reference to fig. 1. Please refer to fig. 1, which is a block diagram illustrating an embodiment of a system for implementing DSD audio hard decoding according to an embodiment of the present invention. As shown in fig. 1, in some embodiments the system comprises: the device comprises an application processor module 20, an audio processing module 10 connected with the application processing module 20 through a data bus, a digital-to-analog conversion module 40 and an asynchronous double-crystal oscillator clock 30 for providing clock signals for the audio processing module 10. The application processor module 20 is configured to obtain and analyze original audio data, and send a data bus address and data parameters and audio data in an analysis result to the audio processing module 10; the data parameters comprise data sampling rate, bit number, code stream, whether the data is in DSD format, DSD format and mode supported by a back-end digital-to-analog conversion module, and the audio data is DSD Native (Native DSD) data in DSD format or PCM data in non-DSD format decoded by the application processor module. The audio processing module 10 reads the data parameter and the audio data according to the data bus address, decodes the audio data according to the data parameter, and sends the decoded audio data to the digital-to-analog conversion module 40. The digital-to-analog conversion module 40 is configured to convert the decoded audio data sent by the audio processing module 10 into an analog audio signal and output the analog audio signal, and the digital-to-analog conversion module 40 outputs the analog signal to the power amplifier for playing. The asynchronous dual-crystal oscillator clock 30 is configured to output a clock signal to the audio processing module 10, and the audio processing module 10 collects data according to the clock signal. The application processor module 20 is connected to the audio processing module 10 through a data bus, which includes but is not limited to I2S bus, I2C bus, SPI bus, PCI bus, high-speed GPIO data bus, CAN bus or universal serial bus USB high-number data bus and common data line.
The system for realizing DSD audio hard decoding provided by the invention provides a clock signal for the processing module through the asynchronous double-crystal oscillator clock, so that the support of full sampling rate is realized, the clock is more accurate, the effect is better, the data bus is adopted to transmit audio data, the advantage of DSD direct bit stream digital data is exerted, the DSD audio play of all specifications is realized, the accurate play of full sampling rate is realized, and a good sound effect is achieved.
In some embodiments, the parsing the raw audio data comprises: if the original audio data is audio data in a non-DSD format, decoding the original audio data into PCM data, and analyzing the sampling rate, the bit number and the code stream of the PCM data; if the original audio data is audio data in a DSD format, namely DSD original data, the DSD format of the DSD original data is analyzed.
In some embodiments, the decoding the audio data according to the data parameter, and sending the decoded audio data to the digital-to-analog conversion module includes:
if the DSD format in the data parameters is a non-DSD format, namely the audio data is PCM data, sending the PCM data to a digital-to-analog conversion module, and setting the digital-to-analog conversion module according to the sampling rate, the bit number and the code stream in the data parameters;
if the data parameters are in the DSD format or not, namely the audio data are DSD native data, if the mode needing to be supported by the back-end digital-to-analog conversion module is the DSD native mode, transmitting the DSD native data to the digital-to-analog conversion module according to bits; if the mode needing to be supported by the back-end digital-to-analog conversion module is a DoP mode, packaging DSD (digital-to-analog conversion) native data into DoP data according to a DoP protocol, wherein the DoP data consists of data parameters and DSD native data, and outputting the DoP data to the digital-to-analog conversion module; and if the mode which needs to be supported by the back-end digital-to-analog conversion module is a PCM mode, decoding the DSD native data into PCM data according to a DSD coding mode algorithm, converting the PCM data into a corresponding sampling rate, bit number and code stream according to a DSD format in the data parameters, sending the PCM data, the sampling rate, the bit number and the code stream to the digital-to-analog conversion module, and setting the digital-to-analog conversion module according to the sampling rate and the code stream. Therefore, no matter the DSD format is a PCM mode, a DoP mode or a DSD native mode, the system can play, returns the advantage of processing DSD direct bit stream digital data, and can obtain better sound quality. In some embodiments, the audio processing module is further configured to convert PCM data, DSD native data, or DoP data sent to the digital-to-analog conversion module into spdif format and output through the spdif interface 50.
In some embodiments, the sending the data bus address and the data parameter and the audio data in the analysis result to the audio processing module specifically includes: packaging the analysis result of the original audio data according to a self-defined data bus transmission protocol format, wherein the data bus transmission protocol format is as follows: data bus address + data parameter + audio data; the packed data is transmitted to the audio processing module 10 according to the data bus transmission protocol and the data bus address, the data parameter and the audio data are packed first and then transmitted to the audio processing module 10 for decoding processing, so that the data are not easy to lose, and the audio data are actual audio data and comprise DSD (digital signal detector) native data in a DSD format or PCM (pulse code modulation) data in a non-DSD format decoded by the application processor module. In some embodiments, the audio processing module 10 reads the data parameter and the audio data according to the data bus address includes: the audio processing module 10 reads the packaged data according to the data bus address, and analyzes the packaged data according to a data bus transmission protocol. The audio processing module 10 receives the packaged data and the data bus address sent by the application processor module 20, reads the packaged data according to the data bus address, analyzes the packaged data according to a data bus transmission protocol, decodes the audio data according to parameters in the data parameters, and sends the decoded audio data to the digital-to-analog conversion module 40. The audio data decoded by the digital-to-analog conversion module 40 is converted into an analog audio signal and output to the power amplifier for playing.
The DSD format includes DSD64, DSD128, DSD256 and DSD512, the modes which the back end digital-to-analog conversion module needs to support include DSD mode, DoP mode and PCM mode, and the data bus transmission protocol is self-defined, can be modified and adjusted, is very flexible, convenient and expandable, and the transmitted data not only supports PCM data but also supports DSD native data, thus achieving the purpose of supporting full-format DSD hard solution. The system for realizing DSD audio hard solution provided by the invention provides a clock signal for an audio processing module through an asynchronous double-crystal oscillator clock, and the format of a data bus transmission protocol is as follows: data bus address + data parameter + audio data has realized the support of full sampling rate, and the clock is more accurate, and the effect is better, and adopts data bus to carry out audio data's transmission, has given play to the advantage of the direct bit stream digital data of DSD, has realized the DSD audio playback of supporting all specifications, has realized the accurate broadcast of full sampling rate, has reached fine sound effect.
In some embodiments, the data bus transmission protocol format is specifically: 8bit data bus address +8bit data parameter + audio data; wherein, the 8-bit data bus address is a 16-system data bus physical address used for writing data to the application processor module; the parameters of the 8-bit data parameters include: the sampling rate, the bit number and the code stream of the data, whether the data is in a DSD format or not, and the mode which needs to be supported by a rear-end digital-to-analog conversion module; the audio data is actual audio data comprising DSD native data in DSD format or PCM data in non-DSD format decoded by the application processor module. In some embodiments, the asynchronous dual crystal clock 30 comprises a first crystal 301 of 22.5792MHz and a second crystal 302 of 24.576 MHz; or a first crystal oscillator 301 of 45.1584MHz and a second crystal oscillator 302 of 49.152 MHz. Wherein, the first crystal oscillators 301 of 22.5792MHz and 45.1584MHz are used for sampling the audio frequency of audio formats of 44.1KHz, 88.2KHz, 176.4KHz and 352.8KHz, and the second crystal oscillators 302 of 24.576MHz and 49.152MHz are used for sampling the audio frequency of audio formats of 48KHz, 96KHz, 192KHz and 384KHz, thereby realizing the support of full sampling rate, more accurate clock and better effect.
In some embodiments, the audio processing module is implemented based on a Field-Programmable Gate Array (FPGA), and the FPGA audio processing module decodes the audio data, so that the audio processing module has low cost, high running speed, lower power consumption, and small size. In some embodiments, the application processor module 20 is coupled to the audio processing module 10 via a high speed data bus, and the audio processing module 10 is coupled to the digital to analog conversion module 40 via an I2S bus. The data bus is adopted to transmit the data in various formats of the DSD to the audio processing module 10, the audio processing module 10 analyzes a data bus transmission protocol to process the data, the cost is low, the size is small, the power consumption is lower, and the problems of high cost, large size and high power consumption in other modes are solved.
The system for realizing the DSD audio hard decoding provided by the embodiment of the invention can be applied to all products which have requirements on tone quality and need to support the playing of the DSD format, in particular to portable HiFi player products, including but not limited to portable players, desktop HiFi players, digital playing products, music fever mobile phones and other products.
The system for realizing DSD audio hard decoding provided by the embodiment of the invention realizes music playing in DSD64, DSD128, DSD256 and DSD512 high-code stream DSD formats, supports all DSD modes including playing in PCM mode, DoP mode and DSD native mode, gives play to the advantages of DSD direct bit stream digital data, obtains better sound quality and achieves more excellent sound effect improvement; the performance requirement of the application processor is not high through the self-defined data bus transmission protocol, so that the method is suitable for mainstream application processors or upper computers, and is higher in universality and flexibility, more practical, simple to implement, flexible in protocol modification and higher in application expansibility; the data bus is adopted to transmit the data in various formats of the DSD to the audio processing module realized based on the FPGA, and the audio processing module analyzes a data bus transmission protocol to process the data, so that the cost is low, the size is small, the power consumption is lower, and the problems of high cost, large size and high power consumption in other modes are solved; the asynchronous dual-crystal oscillator clock is adopted, the support of audio full sampling rates of 32Khz, 44.1KHz, 88.2KHz, 176.4KHz, 352.8KHz, 48KHz, 96KHz, 192KHz and 384KHz is realized, the clock is more accurate, the effect is better, the data playing of a DSD format is supported, the transmission and the playing of other PCM formats are also supported, and the best effect is achieved.
Please refer to fig. 2, which is a flowchart illustrating a method for implementing DSD audio hard decoding according to an embodiment of the present invention. The embodiment of the method is implemented based on the embodiment of the system, and reference is made to the embodiment of the system for non-detailed contents in the embodiment of the method. As shown in fig. 2, the method includes steps S101 to S103, and the specific contents are as follows:
step S101: the application processor module acquires and analyzes original audio data and sends data bus addresses and data parameters and audio data in analysis results to the audio processing module; the data parameters comprise data sampling rate, bit number, code stream, whether the data is in DSD format, DSD format and mode that the back-end digital-to-analog conversion module needs to support, and the audio data is DSD native data in DSD format or PCM data in non-DSD format decoded by the application processor module.
In some embodiments, the parsing the raw audio data comprises: if the original audio data is audio data in a non-DSD format, decoding the original audio data into PCM data, and analyzing the sampling rate, the bit number and the code stream of the PCM data; if the original audio data is audio data in a DSD format, namely DSD original data, the DSD format of the DSD original data is analyzed.
In some embodiments, the sending the data bus address and the data parameter and the audio data in the analysis result to the audio processing module specifically includes: packaging the analysis result of the original audio data according to a self-defined data bus transmission protocol format, wherein the data bus transmission protocol format is as follows: data bus address + data parameter + audio data; and transmitting the packaged data to the audio processing module according to the data bus transmission protocol and the data bus address. In some embodiments, the data bus transfer protocol format is specifically: 8bit data bus address +8bit data parameter + audio data; wherein, the 8-bit data bus address is a 16-system data bus physical address used for writing data to the application processor module; the parameters of the 8-bit data parameters include: the sampling rate, the bit number and the code stream of the data, whether the data is in a DSD format or not, and the mode which needs to be supported by a rear-end digital-to-analog conversion module; the audio data is actual audio data comprising DSD native data in DSD format or PCM data in non-DSD format decoded by the application processor module. In some embodiments, the asynchronous crystal clock comprises a first crystal oscillator of 22.5792MHz and a second crystal oscillator of 24.576 MHz; or a first crystal oscillator of 45.1584MHz and a second crystal oscillator of 49.152 MHz. Wherein, the first crystal oscillator of 22.5792MHz and 45.1584MHz is used for sampling the audio frequency of audio frequency format of 44.1KHz, 88.2KHz, 176.4KHz and 352.8KHz, the second crystal oscillator of 24.576MHz and 49.152MHz is used for sampling the audio frequency of audio frequency format of 48KHz, 96KHz, 192KHz and 384KHz, thereby realizing the support to the full sampling rate, the clock is more accurate, and the effect is better.
Step S102: the audio processing module reads the data parameters and the audio data according to the data bus address, decodes the audio data according to the data parameters, and sends the decoded audio data to the digital-to-analog conversion module; wherein, the clock signal of the audio processing module is provided by an asynchronous dual-crystal clock.
In some embodiments, the audio processing module reading the data parameter and the audio data according to the data bus address comprises: and the audio processing module reads the packaged data according to the data bus address and analyzes the packaged data according to a data bus transmission protocol.
In some embodiments, the decoding the audio data according to the data parameter, and sending the decoded audio data to the digital-to-analog conversion module includes:
if the DSD format in the data parameters is a non-DSD format, namely the audio data is PCM data, sending the PCM data to a digital-to-analog conversion module, and setting the digital-to-analog conversion module according to the sampling rate, the bit number and the code stream in the data parameters;
if the data parameters are in the DSD format or not, namely the audio data are DSD native data, if the mode needing to be supported by the back-end digital-to-analog conversion module is the DSD native mode, transmitting the DSD native data to the digital-to-analog conversion module according to bits; if the mode needing to be supported by the back-end digital-to-analog conversion module is a DoP mode, packaging DSD (digital-to-analog conversion) native data into DoP data according to a DoP protocol, wherein the DoP data consists of data parameters and DSD native data, and outputting the DoP data to the digital-to-analog conversion module; and if the mode which needs to be supported by the back-end digital-to-analog conversion module is a PCM mode, decoding the DSD native data into PCM data according to a DSD coding mode algorithm, converting the PCM data into a corresponding sampling rate, bit number and code stream according to a DSD format in the data parameters, sending the PCM data, the sampling rate, the bit number and the code stream to the digital-to-analog conversion module, and setting the digital-to-analog conversion module according to the sampling rate and the code stream.
In some embodiments, the audio processing module is implemented based on a Field-Programmable Gate Array (FPGA), and the FPGA audio processing module decodes the audio data, so that the audio processing module has low cost, high running speed, lower power consumption, and small size.
Step S103: the digital-to-analog conversion module converts the decoded audio data sent by the audio processing module into an analog audio signal and outputs the analog audio signal to the power amplifier for playing.
In this embodiment, the application processor module is connected with the audio processing module through a data bus; the clock signal of the audio processing module is provided by an asynchronous double-crystal clock. As a preferred embodiment, the application processor module is connected with the audio processing module through a high-speed data bus, and the audio processing module is connected with the digital-to-analog conversion module through an I2S bus. The data bus is adopted to transmit the data in various formats of the DSD to the audio processing module, and the audio processing module analyzes a data bus transmission protocol to process the data, so that the cost is low, the size is small, and the power consumption is lower.
In summary, the method for implementing DSD audio hard decoding provided by this embodiment provides a clock signal for the audio processing module through the asynchronous dual-crystal oscillator clock, so that support of a full sampling rate is achieved, the clock is more accurate, and the effect is better.
The technical principle of the present invention is described above in connection with specific embodiments. The description is made for the purpose of illustrating the principles of the invention and should not be construed in any way as limiting the scope of the invention. Based on the explanations herein, those skilled in the art will be able to conceive of other embodiments of the present invention without inventive effort, which would fall within the scope of the present invention.
Claims (10)
1. A system for realizing DSD audio hard solution is characterized by comprising an application processor module, an audio processing module connected with the application processor module through a data bus, a digital-to-analog conversion module and an asynchronous double-crystal oscillator clock for providing clock signals for the audio processing module;
the application processor module is used for acquiring and analyzing original audio data and sending data bus addresses and data parameters and audio data in analysis results to the audio processing module; the data parameters comprise data sampling rate, bit number, code stream, whether the data is in DSD format, DSD format and mode that the back-end digital-to-analog conversion module needs to support, and the audio data is DSD native data in DSD format or PCM data in non-DSD format decoded by the application processor module;
the audio processing module reads the data parameters and the audio data according to the data bus address, decodes the audio data according to the data parameters, and sends the decoded audio data to the digital-to-analog conversion module;
and the digital-to-analog conversion module is used for converting the decoded audio data sent by the audio processing module into an analog audio signal and outputting the analog audio signal.
2. The system of claim 1, wherein parsing the raw audio data comprises: if the original audio data is audio data in a non-DSD format, decoding the original audio data into PCM data, and analyzing the sampling rate, the bit number and the code stream of the PCM data; if the original audio data is audio data in a DSD format, namely DSD original data, the DSD format of the DSD original data is analyzed.
3. The system of claim 2, wherein the decoding the audio data according to the data parameter and sending the decoded audio data to the digital-to-analog conversion module comprises:
if the DSD format in the data parameters is a non-DSD format, namely the audio data is PCM data, sending the PCM data to a digital-to-analog conversion module, and setting the digital-to-analog conversion module according to the sampling rate, the bit number and the code stream in the data parameters;
if the data parameters are in the DSD format or not, namely the audio data are DSD native data, if the mode needing to be supported by the back-end digital-to-analog conversion module is the DSD native mode, transmitting the DSD native data to the digital-to-analog conversion module according to bits; if the mode needing to be supported by the back-end digital-to-analog conversion module is a DoP mode, packaging DSD (digital-to-analog conversion) native data into DoP data according to a DoP protocol, wherein the DoP data consists of data parameters and DSD native data, and outputting the DoP data to the digital-to-analog conversion module; and if the mode which needs to be supported by the back-end digital-to-analog conversion module is a PCM mode, decoding the DSD native data into PCM data according to a DSD coding mode algorithm, converting the PCM data into a corresponding sampling rate, bit number and code stream according to a DSD format in the data parameters, sending the PCM data, the sampling rate, the bit number and the code stream to the digital-to-analog conversion module, and setting the digital-to-analog conversion module according to the sampling rate and the code stream.
4. The system of claim 3, wherein the audio processing module is further configured to convert PCM data, DSD native data, or DoP data sent to the digital-to-analog conversion module into spdif format output.
5. The system for implementing DSD audio hard decoding of claim 1, wherein the asynchronous dual crystal clock comprises a first crystal oscillator of 22.5792MHz and a second crystal oscillator of 24.576 MHz; or a first crystal oscillator of 45.1584MHz and a second crystal oscillator of 49.152 MHz.
6. The system for implementing DSD audio hard solution according to claim 1, wherein said audio processing module is implemented based on FPGA; the application processor module is connected with the audio processing module through a high-speed data bus.
7. A system for implementing DSD audio hard solution according to claim 1, wherein:
the sending the data bus address and the data parameter and the audio data in the analysis result to the audio processing module specifically includes:
packaging the analysis result of the original audio data according to a self-defined data bus transmission protocol format, wherein the data bus transmission protocol format is as follows: data bus address + data parameter + audio data;
transmitting the packaged data to an audio processing module according to a data bus transmission protocol and a data bus address;
the audio processing module reads the data parameter and the audio data according to the data bus address, and the audio processing module comprises: and the audio processing module reads the packaged data according to the data bus address and analyzes the packaged data according to a data bus transmission protocol.
8. A method of implementing a DSD audio hard solution, the method comprising:
the application processor module acquires and analyzes original audio data and sends data bus addresses and data parameters and audio data in analysis results to the audio processing module; the data parameters comprise data sampling rate, bit number, code stream, whether the data is in DSD format, DSD format and mode that the back-end digital-to-analog conversion module needs to support, and the audio data is DSD native data in DSD format or PCM data in non-DSD format decoded by the application processor module;
the audio processing module reads the data parameters and the audio data according to the data bus address, decodes the audio data according to the data parameters, and sends the decoded audio data to the digital-to-analog conversion module;
the digital-to-analog conversion module converts the decoded audio data sent by the audio processing module into an analog audio signal and outputs the analog audio signal;
the application processor module is connected with the audio processing module through a data bus; the clock signal of the audio processing module is provided by an asynchronous double-crystal clock.
9. The method of claim 8, wherein parsing the raw audio data comprises: if the original audio data is audio data in a non-DSD format, decoding the original audio data into PCM data, and analyzing the sampling rate, the bit number and the code stream of the PCM data; if the original audio data is audio data in a DSD format, namely DSD original data, the DSD format of the DSD original data is analyzed.
10. The method of claim 9, wherein the decoding the audio data according to the data parameter and sending the decoded audio data to a digital-to-analog conversion module comprises:
if the DSD format in the data parameters is a non-DSD format, namely the audio data is PCM data, sending the PCM data to a digital-to-analog conversion module, and setting the digital-to-analog conversion module according to the sampling rate, the bit number and the code stream in the data parameters;
if the data parameters are in the DSD format or not, namely the audio data are DSD native data, if the mode needing to be supported by the back-end digital-to-analog conversion module is the DSD native mode, transmitting the DSD native data to the digital-to-analog conversion module according to bits; if the mode needing to be supported by the back-end digital-to-analog conversion module is a DoP mode, packaging DSD (digital-to-analog conversion) native data into DoP data according to a DoP protocol, wherein the DoP data consists of data parameters and DSD native data, and outputting the DoP data to the digital-to-analog conversion module; and if the mode which needs to be supported by the back-end digital-to-analog conversion module is a PCM mode, decoding the DSD native data into PCM data according to a DSD coding mode algorithm, converting the PCM data into a corresponding sampling rate, bit number and code stream according to a DSD format in the data parameters, sending the PCM data, the sampling rate, the bit number and the code stream to the digital-to-analog conversion module, and setting the digital-to-analog conversion module according to the sampling rate and the code stream.
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| CN113763971A (en) * | 2021-09-07 | 2021-12-07 | 广州飞傲电子科技有限公司 | Audio decoding control method and device and audio decoding control equipment |
| CN113744746B (en) * | 2021-09-07 | 2023-08-08 | 广州飞傲电子科技有限公司 | Audio data conversion playing method and device and audio player |
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