CN107493080A - Low internal resistance Buffer output circuit - Google Patents
Low internal resistance Buffer output circuit Download PDFInfo
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- CN107493080A CN107493080A CN201710778383.9A CN201710778383A CN107493080A CN 107493080 A CN107493080 A CN 107493080A CN 201710778383 A CN201710778383 A CN 201710778383A CN 107493080 A CN107493080 A CN 107493080A
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- Prior art keywords
- resistance
- source
- power amplifier
- stable pressure
- amplifier tube
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/32—Modifications of amplifiers to reduce non-linear distortion
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/56—Modifications of input or output impedances, not otherwise provided for
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/181—Low frequency amplifiers, e.g. audio preamplifiers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
- H03F3/211—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only using a combination of several amplifiers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/03—Indexing scheme relating to amplifiers the amplifier being designed for audio applications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/234—Indexing scheme relating to amplifiers the input amplifying stage being one or more operational amplifiers
Abstract
The invention provides a kind of low internal resistance Buffer output circuit, including：Four source of stable pressure, an operational amplifier, four power amplifier tubes, five resistance；The both ends of first resistor connect the first source of stable pressure and the first power amplifier tube respectively；The both ends of second resistance connect the second source of stable pressure and the second power amplifier tube respectively；The both ends of 3rd resistor connect the 3rd source of stable pressure and the 3rd power amplifier tube respectively；The both ends of 4th resistance connect the 4th source of stable pressure and the 4th power amplifier tube respectively；The normal phase input end of first, second source of stable pressure and operational amplifier is connected with signal input part respectively；Output end of three, the 4th source of stable pressure respectively with the first operational amplifier is connected；Firstth, the three, the 4th and second power amplifier tube be sequentially connected；The shared end connection signal output part of three, the 4th power amplifier tubes, the 5th resistance is connected between signal output part and the inverting input of the first operational amplifier.The circuit has a high resistant input, low-resistance output, the advantages of low distortion.
Description
Technical field
The present invention relates to buffer circuit technical field, more particularly, to low internal resistance Buffer output circuit.
Background technology
In power amplifier field, output internal resistance is one of important indicator for testing power amplifier properties.Especially sound
Frequency power amplifier, it directly represent its quality to loudspeaker driving force.The internal resistance of audio-frequency power amplifier is lower, is driven
The transient response of loudspeaker is better, and the damped coefficient of power amplifier is higher.But traditional circuit design, pass through gain circuitry
Amount of negative feedback improves damped coefficient, reduces equivalent output internal resistance, but when damped coefficient is more than certain value, due to deep negative
The stability of feedback needs, and causes the rising edge settling time of signal long because of the presence of weakening electric capacity on the contrary, has dragged slowly letter
Number transient response, so as to also cause loudspeaker response speed have dropped.Can be solved to a certain extent using output buffering
This problem, or but conventional buffer circuit power is small, or internal resistance is too big, be able to can also be tieed up in 50W even more than 2000W
Hold that audio-frequency power amplifier of the damped coefficient more than 800 is actually rare, damped coefficient more than 2000 is even more the current world
Top index, it is very expensive.
The content of the invention
In view of the above-mentioned deficiencies in the prior art, it is an object of the present invention to provide a kind of low internal resistance Buffer output circuit so that work(
Putting no longer needs to obtain low internal resistance high-damping from gain circuitry, it is not required that the design of complex and expensive.Delay in high-power
Rush in circuit, the high performance operational amplifier chip of low pressure or circuit are matched with the mode of partial pressure, with high-tension circuit together work
Make, while obtain high-power and high-performance, so as on the premise of more inexpensive so that damped coefficient reaches more than 10000.
Specifically, the invention provides a kind of low internal resistance Buffer output circuit, including：It is first source of stable pressure (VS1), second steady
Potential source (VS2), the 3rd source of stable pressure (VS3), the 4th source of stable pressure (VS4), the first operational amplifier (OP1), the first power amplifier tube
(Q1), the second power amplifier tube (Q2), the 3rd power amplifier tube (Q3), the 4th power amplifier tube (Q4), first resistor (R1),
Two resistance (R2), 3rd resistor (R3), the 4th resistance (R4) and the 5th resistance (R5).
The both ends of the first resistor (R1) connect first source of stable pressure (VS1) and first power amplifier tube respectively
(Q1)；The both ends of the second resistance (R2) connect second source of stable pressure (VS2) and second power amplifier tube respectively
(Q2)；The both ends of the 3rd resistor (R3) connect the 3rd source of stable pressure (VS3) and the 3rd power amplifier tube respectively
(Q3)；The both ends of 4th resistance (R4) connect the 4th source of stable pressure (VS4) and the 4th power amplifier tube respectively
(Q4)。
First source of stable pressure (VS1), second source of stable pressure (VS2) and first operational amplifier (OP1) are just
Phase input is connected with signal input part respectively；3rd source of stable pressure (VS3) and the 4th source of stable pressure (VS4) respectively with institute
State the output end connection of the first operational amplifier (OP1)；First power amplifier tube (Q1), the 3rd power amplifier tube
(Q3), the 4th power amplifier tube (Q4) and second power amplifier tube (Q2) are sequentially connected；3rd power amplification
Pipe (Q3) connects signal output part, the signal output part and first computing with the shared end of the 4th power amplifier tube (Q4)
The 5th resistance (R5) is connected between the inverting input of amplifier (OP1).
As the further improvement of above-mentioned technical proposal, the low internal resistance Buffer output circuit also includes：6th resistance
(R6) and the 7th resistance (R7), it is connected to the 3rd power after the 6th resistance (R6) and the 7th resistance (R7) series connection
Between amplifier tube (Q3) and the 4th power amplifier tube (Q4).
As the further improvement of above-mentioned technical proposal, the low internal resistance Buffer output circuit also includes：8th resistance
(R8) first computing is connected to after and the first electric capacity (C1), the 8th resistance (R8) and first electric capacity (C1) are in parallel
Between the output end and inverting input of amplifier (OP1).
As the further improvement of above-mentioned technical proposal, the low internal resistance Buffer output circuit also includes：9th resistance
(R9), the 9th resistance (R9) be connected to first operational amplifier (OP1) inverting input and outer counter feed point it
Between.
As the further improvement of above-mentioned technical proposal, the low internal resistance Buffer output circuit also includes：Second computing is put
Big device (OP2), second operational amplifier (OP2) are connected to first operational amplifier (OP1) and the 3rd voltage stabilizing
Between source (VS3)；The normal phase input end of second operational amplifier (OP2) connects first operational amplifier (OP1)
Output end, the inverting input of second operational amplifier (OP2) connect the output of second operational amplifier (OP2)
End, the output end of second operational amplifier (OP2) are all connected with the 3rd source of stable pressure (VS3) and the 4th source of stable pressure
(VS4)。
As the further improvement of above-mentioned technical proposal, the low internal resistance Buffer output circuit also includes：First diode
(D1) and the second diode (D2), it is connected to letter after first diode (D1) and second diode (D2) parallel connected in reverse phase
The inverting input of number input and the first operational amplifier (OP1).
As the further improvement of above-mentioned technical proposal, the low internal resistance Buffer output circuit also includes：Tenth resistance
(R10) first electricity is connected to after and the second electric capacity (C2), the tenth resistance (R10) and second electric capacity (C2) are in parallel
Hinder shared end and the second resistance (R2) and second source of stable pressure (VS2) of (R1) and first source of stable pressure (VS1)
Share between holding.
As the further improvement of above-mentioned technical proposal, the low internal resistance Buffer output circuit also includes：11st resistance
(R11) and the 12nd resistance (R12), the 11st resistance (R11) and the 6th resistance (R6) are in parallel, the 12nd electricity
Hinder (R12) and the 7th resistance (R7) is in parallel.
As the further improvement of above-mentioned technical proposal, the low internal resistance Buffer output circuit also includes：5th power is put
Big pipe (Q5), the 6th power amplifier tube (Q6), the 13rd resistance (R13) and the 14th resistance (R14)；5th power amplification
Pipe (Q5) and the 13rd resistance (R13) are used to extend the power of first power amplifier tube (Q1), the 6th work(
Rate amplifier tube (Q6) and the 14th resistance (R14) are used to extend the power of second power amplifier tube (Q2).
As the further improvement of above-mentioned technical proposal, first source of stable pressure (VS1) and second source of stable pressure (VS2)
Using the combination of constant-current source, triode, voltage-regulator diode and electric capacity, the 3rd source of stable pressure (VS3) and the 4th voltage stabilizing
Source (VS4) is using the combination of constant-current source, resistance, diode and electric capacity.
Using technical scheme provided by the invention, compared with existing known technology, at least have the advantages that：Pole
The earth improves the performance of Buffer output, high resistant input, low-resistance output, low distortion.By the circuit of the present invention, from small-power
Operational amplifier can large-power occasions obtain and low-power device equally accurately export, make high-power, high-performance and
High accuracy is realized simultaneously.
Brief description of the drawings
In order to illustrate the technical solution of the embodiments of the present invention more clearly, below by embodiment it is required use it is attached
Figure is briefly described, it will be appreciated that the following drawings illustrate only certain embodiments of the present invention, therefore be not construed as pair
The restriction of scope, for those of ordinary skill in the art, on the premise of not paying creative work, can also be according to this
A little accompanying drawings obtain other related accompanying drawings.
Fig. 1 is the circuit theory diagrams for the low internal resistance Buffer output circuit that the embodiment of the present invention 1 proposes.
Fig. 2 is the circuit theory diagrams for the low internal resistance Buffer output circuit that the embodiment of the present invention 2 proposes.
Fig. 3 is the circuit theory diagrams for the low internal resistance Buffer output circuit that the embodiment of the present invention 3 proposes.
Embodiment
Hereinafter, the various embodiments of the disclosure will be described more fully.The disclosure can have various embodiments, and
It can adjust and change wherein.It should be understood, however, that：It is limited to specific reality disclosed herein in the absence of by disclosure protection domain
The intention of example is applied, but the disclosure should be interpreted as covering all in the spirit and scope for the various embodiments for falling into the disclosure
Adjustment, equivalent and/or alternative.
Hereinafter, disclosed in the term " comprising " that can be used in the various embodiments of the disclosure or " may include " instruction
Function, operation or the presence of element, and do not limit the increase of one or more functions, operation or element.In addition, such as exist
Used in the various embodiments of the disclosure, term " comprising ", " having " and its cognate are meant only to represent special characteristic, number
Word, step, operation, the combination of element, component or foregoing item, and be understood not to exclude first one or more other
Feature, numeral, step, operation, element, component or foregoing item combination presence or one or more features of increase, numeral,
Step, operation, element, component or foregoing item combination possibility.
The statement (" first ", " second " etc.) used in the various embodiments of the disclosure can be modified in various implementations
Various element in example, but respective sets can not be limited into element.For example, presented above be not intended to limit the suitable of the element
Sequence and/or importance.The purpose presented above for being only used for differentiating an element and other elements.For example, the first user fills
Put and indicate different user device with second user device, although the two is all user's set.For example, each of the disclosure is not being departed from
In the case of the scope of kind embodiment, the first element is referred to alternatively as the second element, and similarly, the second element is also referred to as first
Element.
It should be noted that：, can be by the first composition member if an element ' attach ' to another element by description
Part is directly connected to the second element, and " connection " the 3rd can be formed between the first element and the second element
Element.On the contrary, when an element " being directly connected to " is arrived into another element, it will be appreciated that be in the first element
And second be not present the 3rd element between element.
The term used in the various embodiments of the disclosure is only used for describing the purpose of specific embodiment and not anticipated
In the various embodiments of the limitation disclosure.Unless otherwise defined, be otherwise used herein all terms (including technical term and
Scientific terminology) there is the implication identical being generally understood that with the various embodiment one skilled in the art of the disclosure to contain
Justice.The term (term such as limited in the dictionary typically used) be to be interpreted as have with correlative technology field
Situational meaning identical implication and the implication with Utopian implication or overly formal will be not construed as, unless at this
It is clearly defined in disclosed various embodiments.
Embodiment 1
As shown in figure 1, a kind of low internal resistance Buffer output circuit, including：First source of stable pressure VS1, the second source of stable pressure VS2,
Three source of stable pressure VS3, the 4th source of stable pressure VS4, the first operational amplifier OP1, the first power amplifier tube Q1, the second power amplifier tube
Q2, the 3rd power amplifier tube Q3, the 4th power amplifier tube Q4, first resistor R1, second resistance R2,3rd resistor R3, the 4th electricity
Hinder R4 and the 5th resistance R5.
First resistor R1 both ends connect the first source of stable pressure VS1 and the first power amplifier tube Q1 respectively；Second resistance R2's
Both ends connect the second source of stable pressure VS2 and the second power amplifier tube Q2 respectively；3rd resistor R3 both ends connect the 3rd voltage stabilizing respectively
Source VS3 and the 3rd power amplifier tube Q3；4th resistance R4 both ends connect the 4th source of stable pressure VS4 and the 4th power amplifier tube respectively
Q4；First source of stable pressure VS1, the second source of stable pressure VS2 and the first operational amplifier OP1 normal phase input end respectively with signal input part
IN connections；The output end of 3rd source of stable pressure VS3 and the 4th source of stable pressure VS4 respectively with the first operational amplifier OP1 is connected；First work(
Rate amplifier tube Q1, the 3rd power amplifier tube Q3, the 4th power amplifier tube Q4 and the second power amplifier tube Q2 are sequentially connected；3rd work(
Rate amplifier tube Q3 and the 4th power amplifier tube Q4 shared end connect signal output part OUT, signal output part OUT and the first computing
The 5th resistance R5 is connected between amplifier OP1 inverting input.
First operational amplifier OP1 can be integrated operational amplifier or have the amplification electricity of positive anti-phase input
Road or equal function element.
In the present embodiment, the first power amplifier tube Q1, the second power amplifier tube Q2, the 3rd power amplifier tube Q3, the 4th
Power amplifier tube Q4 selects FET.Specifically, the first power amplifier tube Q1 and the 3rd power amplifier tube Q3 are N-MOS
FET, the second power amplifier tube Q2 and the 4th power amplifier tube Q4 are P-MOS FETs.First power amplifier tube Q1
Drain electrode connection VCC, the first power amplifier tube Q1 source electrode connects the 3rd power amplifier tube Q3 drain electrode, the 3rd power amplifier tube
Q3 source electrode connects the 4th power amplifier tube Q4 source electrode, and the 4th power amplifier tube Q4 drain electrode connects the second power amplifier tube Q2
Source electrode, the second power amplifier tube Q2 drain electrode connection VSS.First resistor R1 both ends connect the first power amplifier tube Q1's respectively
The positive pole of grid and the first source of stable pressure VS1, second resistance R2 both ends connect the second power amplifier tube Q2 grid and second respectively
Source of stable pressure VS2 negative pole, 3rd resistor R3 both ends connect the 3rd power amplifier tube Q3 grid and the 3rd source of stable pressure VS3 respectively
Positive pole, the 4th resistance R4 both ends connect the 4th power amplifier tube Q4 grid and the 4th source of stable pressure VS4 negative pole respectively.First is steady
Normal phase input end of potential source VS1 negative pole and the second source of stable pressure VS2 positive pole with the first operational amplifier OP1 is connected, and the 3rd
Output end of source of stable pressure VS3 negative pole and the 4th source of stable pressure the VS4 positive pole with the first operational amplifier OP1 is connected, the first fortune
Two feeder ears for calculating amplifier OP1 connect the first power amplifier tube Q1 source electrode and the second power amplifier tube Q2 source respectively
Pole.3rd power amplifier tube Q3 source electrode and the 4th power amplifier tube Q4 source electrode are all connected with signal output part OUT.
First power amplifier tube Q1 and the second power amplifier tube Q2 is partial pressure power tube, the 3rd power amplifier tube Q3 and the 4th
Power amplifier tube Q4 is power output pipe.Under high-power occasion, Q1 and Q2 will undertake most voltage and power
Dissipate.Except Q1 and Q2, circuit other elements are all operated under conditions of relatively low pressure.
Because VS1 and VS2 are constant pressure source, the cut-in voltage of power amplifier tube is also relative constancy, therefore first transports
The supply voltage for calculating amplifier OP1 is VS1+VS2-Vgs (Q1)-Vgs (Q2), is a metastable value, is VS1 and VS2
A suitable magnitude of voltage is selected, the first operational amplifier OP1 cans work in safe voltage.
In other embodiments, the first power amplifier tube Q1, the second power amplifier tube Q2, the 3rd power amplifier tube Q3,
Four power amplifier tube Q4 can have the semiconductor power pipe of amplification from triode, IGBT etc..
5th resistance R5 is internal feedback resistance, and signal is fed back to the first operational amplifier OP1 inverting input.By
Outstanding performance is usually constructed with operational amplifier, therefore signal input part IN and signal output part OUT voltage will height one
Cause, final output impedance is also very low, and signal input part IN passes through the first source of stable pressure VS1, the second source of stable pressure VS2, the first electricity
Resistance R1, second resistance R2 drive the first power amplifier tube Q1 and the second power amplifier tube Q2, signal input part IN to be connected on the simultaneously
One operational amplifier OP1 normal phase input end, due to being all high impedance input, therefore distortion is very small.
Embodiment 2
As shown in Fig. 2 the present embodiment adds the 6th resistance R6 and the 7th resistance R7 on the basis of embodiment 1, the 6th
It is connected to after resistance R6 and the 7th resistance R7 series connection between the 3rd power amplifier tube Q3 and the 4th power amplifier tube Q4.Put in power
During big pipe job insecurity, increase the 6th resistance R6 and the 7th resistance R7 can improve the stability of circuit.
The present embodiment adds the 8th resistance R8 and the first electric capacity C1, the 8th resistance R8 and on the basis of embodiment 1
It is connected to after one electric capacity C1 parallel connections between the first operational amplifier OP1 output end and inverting input.8th resistance R8 and
One electric capacity C1 is the first operational amplifier OP1 direct negative feedback network, plays a part of stable Working Condition of Interpretative Version.
The present embodiment adds the 9th resistance R9 on the basis of embodiment 1, and the 9th resistance R9 is connected to the first computing and put
Between big device OP1 inverting input and outer counter feed point EX-FB.9th resistance R9 is external feedback resistance, can according to should
With scene, external loading circuit is connected to, further reduces output internal resistance.
Embodiment 3
As shown in figure 3, the present embodiment has been done further on the basis of embodiment 1 or embodiment 2 for constant pressure source
Bright, the first source of stable pressure is made up of constant-current source IS1, triode Q7, voltage-regulator diode D3 and electric capacity C3, and the second source of stable pressure is by constant-current source
IS2, triode Q8, voltage-regulator diode D4 and electric capacity C4 compositions, the 3rd source of stable pressure is by constant-current source IS3, resistance R15, diode D5
Formed with electric capacity C5, the 4th source of stable pressure is made up of constant-current source IS4, resistance R16, diode D6 and electric capacity C6.Specifically, Q7 is
NPN type triode, Q8 are PNP type triode.
The present embodiment adds the second operational amplifier OP2 on the basis of embodiment 1 or embodiment 2, and the second computing is put
Big device OP2 is connected between the first operational amplifier OP1 and the 3rd source of stable pressure and the common port of the 4th source of stable pressure；Second computing is put
Big device OP2 normal phase input end connects the first operational amplifier OP1 output end, the second operational amplifier OP2 anti-phase input
The second operational amplifier OP2 of end connection output end, the second operational amplifier OP2 output end are all connected with the 3rd source of stable pressure and the
Four source of stable pressure.Increase by the second operational amplifier OP2 as buffering, further enhancing the first operational amplifier OP1 to output branch
The driving force on road.
The present embodiment adds the first diode D1 and the second diode D2 on the basis of embodiment 1 or embodiment 2, the
The anti-phase of signal input part IN and the first operational amplifier OP1 is connected to after one diode D1 and the second diode D2 parallel connected in reverse phase
Input.First diode D1 and the second diode D2 are used for position limitation protection.
The present embodiment adds the tenth resistance R10 and the second electric capacity C2 on the basis of embodiment 1 or embodiment 2, and the tenth
The shared end of first resistor R1 and the first source of stable pressure and second resistance R2 and the are connected to after resistance R10 and the second electric capacity C2 parallel connections
Two source of stable pressure are shared between end.Tenth resistance R10 and the second electric capacity C2 is used for further burning voltage.
The present embodiment adds the 11st resistance R11 and the 12nd resistance R12, the 11st electricity on the basis of embodiment 2
It is in parallel to hinder R11 and the 6th resistance R6, the 12nd resistance R12 and the 7th resistance R7 are in parallel, for extended power.
The present embodiment adds the 5th power amplifier tube Q5 and the 13rd resistance on the basis of embodiment 1 or embodiment 2
R13, the 6th power amplifier tube Q6 and the 14th resistance R14；5th power amplifier tube Q5 and the 13rd resistance R13 is used to extend the
One power amplifier tube Q1 power, the 6th power amplifier tube Q6 and the 14th resistance R14 are used to extend the second power amplifier tube Q2
Power.Similarly, also corresponding resistance in parallel can be used to extend the 3rd power amplifier tube Q3 and the 4th with power amplifier tube respectively
Power amplifier tube Q4 power.
It will be appreciated by those skilled in the art that accompanying drawing is a schematic diagram for being preferable to carry out scene, module in accompanying drawing or
Flow is not necessarily implemented necessary to the present invention.
The invention described above sequence number is for illustration only, does not represent the quality of implement scene.Disclosed above is only the present invention
Several specific implementation scenes, still, the present invention is not limited to this, and the changes that any person skilled in the art can think of is all
Protection scope of the present invention should be fallen into.
Claims (10)
- A kind of 1. low internal resistance Buffer output circuit, it is characterised in that including：First source of stable pressure (VS1), the second source of stable pressure (VS2), 3rd source of stable pressure (VS3), the 4th source of stable pressure (VS4), the first operational amplifier (OP1), the first power amplifier tube (Q1), the second work( Rate amplifier tube (Q2), the 3rd power amplifier tube (Q3), the 4th power amplifier tube (Q4), first resistor (R1), second resistance (R2), 3rd resistor (R3), the 4th resistance (R4) and the 5th resistance (R5)；The both ends of the first resistor (R1) connect first source of stable pressure (VS1) and first power amplifier tube respectively (Q1)；The both ends of the second resistance (R2) connect second source of stable pressure (VS2) and second power amplifier tube respectively (Q2)；The both ends of the 3rd resistor (R3) connect the 3rd source of stable pressure (VS3) and the 3rd power amplifier tube respectively (Q3)；The both ends of 4th resistance (R4) connect the 4th source of stable pressure (VS4) and the 4th power amplifier tube respectively (Q4)；The positive of first source of stable pressure (VS1), second source of stable pressure (VS2) and first operational amplifier (OP1) is defeated Enter end to be connected with signal input part respectively；3rd source of stable pressure (VS3) and the 4th source of stable pressure (VS4) are respectively with described The output end connection of one operational amplifier (OP1)；First power amplifier tube (Q1), the 3rd power amplifier tube (Q3), 4th power amplifier tube (Q4) and second power amplifier tube (Q2) are sequentially connected；3rd power amplifier tube (Q3) Signal output part, the signal output part and first operational amplifier are connected with the shared end of the 4th power amplifier tube (Q4) (OP1) the 5th resistance (R5) is connected between inverting input.
- 2. low internal resistance Buffer output circuit according to claim 1, it is characterised in that the low internal resistance Buffer output circuit Also include：Connect after 6th resistance (R6) and the 7th resistance (R7), the 6th resistance (R6) and the 7th resistance (R7) series connection It is connected between the 3rd power amplifier tube (Q3) and the 4th power amplifier tube (Q4).
- 3. low internal resistance Buffer output circuit according to claim 1, it is characterised in that the low internal resistance Buffer output circuit Also include：Connect after 8th resistance (R8) and the first electric capacity (C1), the 8th resistance (R8) and first electric capacity (C1) are in parallel It is connected between output end and the inverting input of first operational amplifier (OP1).
- 4. low internal resistance Buffer output circuit according to claim 1, it is characterised in that the low internal resistance Buffer output circuit Also include：9th resistance (R9), the 9th resistance (R9) are connected to the inverting input of first operational amplifier (OP1) Between outer counter feed point.
- 5. low internal resistance Buffer output circuit according to claim 1, it is characterised in that the low internal resistance Buffer output circuit Also include：Second operational amplifier (OP2), second operational amplifier (OP2) are connected to first operational amplifier (OP1) between the 3rd source of stable pressure (VS3)；The normal phase input end connection described the of second operational amplifier (OP2) The output end of one operational amplifier (OP1), the inverting input of second operational amplifier (OP2) connect second computing The output end of amplifier (OP2), the output end of second operational amplifier (OP2) are all connected with the 3rd source of stable pressure (VS3) With the 4th source of stable pressure (VS4).
- 6. low internal resistance Buffer output circuit according to claim 1, it is characterised in that the low internal resistance Buffer output circuit Also include：First diode (D1) and the second diode (D2), first diode (D1) and second diode (D2) The inverting input of signal input part and the first operational amplifier (OP1) is connected to after parallel connected in reverse phase.
- 7. low internal resistance Buffer output circuit according to claim 1, it is characterised in that the low internal resistance Buffer output circuit Also include：After tenth resistance (R10) and the second electric capacity (C2), the tenth resistance (R10) and second electric capacity (C2) are in parallel It is connected to the shared end of the first resistor (R1) and first source of stable pressure (VS1) and the second resistance (R2) and described the Between the shared end of two source of stable pressure (VS2).
- 8. low internal resistance Buffer output circuit according to claim 2, it is characterised in that the low internal resistance Buffer output circuit Also include：11st resistance (R11) and the 12nd resistance (R12), the 11st resistance (R11) and the 6th resistance (R6) Parallel connection, the 12nd resistance (R12) and the 7th resistance (R7) are in parallel.
- 9. low internal resistance Buffer output circuit according to claim 1, it is characterised in that the low internal resistance Buffer output circuit Also include：5th power amplifier tube (Q5), the 6th power amplifier tube (Q6), the 13rd resistance (R13) and the 14th resistance (R14)；5th power amplifier tube (Q5) and the 13rd resistance (R13) are used to extend first power amplifier tube (Q1) power, the 6th power amplifier tube (Q6) and the 14th resistance (R14) are used to extend second power The power of amplifier tube (Q2).
- 10. low internal resistance Buffer output circuit according to claim 1, it is characterised in that first source of stable pressure (VS1) and Second source of stable pressure (VS2) is using the combination of constant-current source, triode, voltage-regulator diode and electric capacity, the 3rd source of stable pressure (VS3) and the 4th source of stable pressure (VS4) is using the combination of constant-current source, resistance, diode and electric capacity.
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|---|---|---|---|
| CN201710778383.9A CN107493080A (en) | 2017-09-01 | 2017-09-01 | Low internal resistance Buffer output circuit |
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| CN201710778383.9A CN107493080A (en) | 2017-09-01 | 2017-09-01 | Low internal resistance Buffer output circuit |
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| CN107493080A true CN107493080A (en) | 2017-12-19 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108055012A (en) * | 2017-12-28 | 2018-05-18 | 广州时艺音响科技有限公司 | Audio-frequency power amplifier |
| CN108235186A (en) * | 2017-12-29 | 2018-06-29 | 广州时艺音响科技有限公司 | Feedback output loud speaker and feedback output adjusting method |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3536306A1 (en) * | 1985-10-11 | 1987-04-16 | Dieter Flemm | Electronic current stabilizing amplifier |
| WO2008112041A2 (en) * | 2007-03-13 | 2008-09-18 | Astec International Limited | Power supply providing ultrafast modulation of output voltage |
| CN102386867A (en) * | 2010-06-14 | 2012-03-21 | 哈曼国际工业有限公司 | High efficiency audio amplifier system |
| CN204009652U (en) * | 2014-07-18 | 2014-12-10 | 周国文 | The low pressure difference linearity source of stable pressure of Digital Analog Hybrid Circuits |
| CN204908245U (en) * | 2015-07-30 | 2015-12-30 | 重庆市小榄电器有限公司 | Warning bracelet |
| CN105577125A (en) * | 2016-02-23 | 2016-05-11 | 广州时艺音响科技有限公司 | Control device for DC output potential of power amplifier |
| CN205430043U (en) * | 2016-03-21 | 2016-08-03 | 广州时艺音响科技有限公司 | Parallelly connected direct current voltage stabilizing circuit of low corrugated of low internal resistance |
-
2017
- 2017-09-01 CN CN201710778383.9A patent/CN107493080A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3536306A1 (en) * | 1985-10-11 | 1987-04-16 | Dieter Flemm | Electronic current stabilizing amplifier |
| WO2008112041A2 (en) * | 2007-03-13 | 2008-09-18 | Astec International Limited | Power supply providing ultrafast modulation of output voltage |
| CN102386867A (en) * | 2010-06-14 | 2012-03-21 | 哈曼国际工业有限公司 | High efficiency audio amplifier system |
| CN204009652U (en) * | 2014-07-18 | 2014-12-10 | 周国文 | The low pressure difference linearity source of stable pressure of Digital Analog Hybrid Circuits |
| CN204908245U (en) * | 2015-07-30 | 2015-12-30 | 重庆市小榄电器有限公司 | Warning bracelet |
| CN105577125A (en) * | 2016-02-23 | 2016-05-11 | 广州时艺音响科技有限公司 | Control device for DC output potential of power amplifier |
| CN205430043U (en) * | 2016-03-21 | 2016-08-03 | 广州时艺音响科技有限公司 | Parallelly connected direct current voltage stabilizing circuit of low corrugated of low internal resistance |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108055012A (en) * | 2017-12-28 | 2018-05-18 | 广州时艺音响科技有限公司 | Audio-frequency power amplifier |
| CN108055012B (en) * | 2017-12-28 | 2021-04-23 | 广州时艺音响科技有限公司 | Audio power amplifier |
| CN108235186A (en) * | 2017-12-29 | 2018-06-29 | 广州时艺音响科技有限公司 | Feedback output loud speaker and feedback output adjusting method |
| CN108235186B (en) * | 2017-12-29 | 2021-08-06 | 广州时艺音响科技有限公司 | Feedback output speaker and feedback output adjusting method |
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Application publication date: 20171219 |