CN107492395A - Conditional access chip, its built-in self-test circuit and method of testing - Google Patents
Conditional access chip, its built-in self-test circuit and method of testing Download PDFInfo
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- CN107492395A CN107492395A CN201610406032.0A CN201610406032A CN107492395A CN 107492395 A CN107492395 A CN 107492395A CN 201610406032 A CN201610406032 A CN 201610406032A CN 107492395 A CN107492395 A CN 107492395A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/14—Implementation of control logic, e.g. test mode decoders
- G11C29/16—Implementation of control logic, e.g. test mode decoders using microprogrammed units, e.g. state machines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
- G11C29/40—Response verification devices using compression techniques
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/46—Test trigger logic
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C2029/1206—Location of test circuitry on chip or wafer
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C2029/4402—Internal storage of test result, quality data, chip identification, repair information
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Abstract
The present invention relates to a kind of self-test circuit for being built into conditional access chip, conditional access chip decrypts a video-audio data using multiple logic units, and the self-test circuit includes：One storage element, for storing a test data and a comparison data；And a control unit, those logic units are coupled, are used for：Those logic units are controlled to receive a clock pulse to carry out a test；The test data is read from the storage element；The test data is inputted into the one scan chain that those logic units are formed according to the clock pulse；And an output data of the scan chain is compared with the comparison data to obtain a test result.
Description
Technical field
The present invention is to access (conditional access, CA) chip on conditional, is deposited especially with respect to conditional
Test circuit and method of testing in the chip of coring piece.
Background technology
Conditional access is often used to guard digit content, and it is protected to decrypt by key is stored in functional chip
Data.In general, in order to protect key, can be in the topmost metal layer of the semiconductor structure of implementation conditional access chip
An active shield layer (active shield) is made, when chip is broken into (such as by focused ion beam (Focus Ion
Beams, FIB) attack), the active shield layer is likely to be destroyed, therefore chip can be by checking the active shield layer
State come confirm key whether safety.
However, because the active shield layer is made in the surface of chip, is easily known and dodged by intentionally personage；Again
Person, attack may be from the side of chip rather than surface.Although so a variety of be likely to cause the active shield layer to keep
It is as excellent as before, but the situation that internal key has been stolen occurs.It is therefore necessary to propose that better method carrys out guarantee condition formula
Access the data safety of chip.
The content of the invention
In view of the deficiency of prior art, it is an object of the present invention to provide a kind of conditional access chip it is built-in from
My test circuit and method of testing, to improve the security of conditional access chip.
The present invention discloses a kind of self-test circuit for being built into conditional access chip, conditional access chip profit
A video-audio data is decrypted with multiple logic units, the self-test circuit includes：One storage element, for storing a test data
An and comparison data；And a control unit, those logic units are coupled, are used for：Those logic units are controlled to receive a clock pulse
To carry out a test；The test data is read from the storage element；The test data is inputted into those logic lists according to the clock pulse
The one scan chain that member is formed；And an output data of the scan chain is compared with the comparison data to obtain a test result.
The present invention separately discloses a kind of selftest method of conditional access chip, and conditional access chip utilizes multiple
Logic unit decrypts a video-audio data, and comprising for storing a storage element of a test data and a comparison data, is somebody's turn to do
Selftest method includes：Those logic units are controlled to receive a clock pulse to carry out a test；The survey is read from the storage element
Try data；The test data is inputted into the one scan chain that those logic units are formed according to the clock pulse；And compare the scanning
One output data of chain is with the comparison data to obtain a test result.
Conditional access chip, its built-in self-test circuit and the method for testing of the present invention is directly to the logic in chip
Unit and logic circuit are tested, can be certain by test data is pre-stored in into chip internal to improve the security of test
Know whether chip is destroyed.Compared to known technology, the present invention improves the security of conditional access chip and is easy to real
Make.
Feature, implementation and effect for the present invention, accompanying drawing is hereby coordinated to make embodiment detailed description as follows.
Brief description of the drawings
Fig. 1 is the partial circuit diagram for the embodiment that conditional of the present invention accesses chip；
Fig. 2 is that the conditional of the present invention accesses the flow chart of chip selftest method；
Fig. 3 is the detailed process of Fig. 2 steps S250 testing scanning chain；
The connection diagram of the logic unit of Fig. 4 present invention；And
Fig. 5 is the schematic diagram of another logic unit in scan chain of the invention.
Symbol description
110 scan chains
120 control units
130 storage elements
140th, 165,420,510 multiplexer
150 oscillating circuits
170 decompression circuits
180 compressor circuits
400th, 500 logic unit
410 triggers
450 logic circuits
S210~S280 steps
Embodiment
The announcement dew content of the present invention includes conditional access chip, its built-in self-test circuit and method of testing.Should
Apparatus and method can be applied to the receiving terminal of box on DVB-T or machine, be embodied as it is possible under the premise of, the art tool
Usually intellectual can select equivalent element or step to realize the present invention, Yi Jiben according to the disclosure of this specification
The embodiment that the implementation of invention is chatted after being not limited to.
The conditional access chip of the present invention is operable in mode of operation and test pattern.In mode of operation, the condition
Formula access chip execution in general function (such as the chip application in DVB-T, then its general utility functions is the audio-visual number of decryption
According to)；And in test pattern, the logic unit that conditional access chip internal forms each functional module is concatenated into scan chain
(scan chain), and whether destroyed with detection chip by scan chain input test data.The test number of the present invention
Chip internal is all pre-stored according to corresponding test result.Fig. 1 is the office of an embodiment of conditional access chip of the present invention
Portion's circuit diagram.In addition to forming scan chain 110-1~110-N logic unit, remaining circuit can be considered as condition in Fig. 1
Formula accesses the built-in self-test circuit of chip.It is used for storing above-mentioned test data and corresponding survey in storage element 130
Test result, control unit 120 are coupled to storage element 130, for read test data Test_in and corresponding test knot
Fruit, test data Test_in inputted into scan chain 110-1~110-N (N is positive integer) and the output knot by scan chain 110
Test result corresponding with this fruit Test_out compares, to confirm whether chip is destroyed.In one embodiment, control
Unit 120 processed may, for example, be micro-control unit or microprocessor, reach by the flow or algorithm that perform Fig. 2 and Fig. 3
Its function, and storage element 130 can be micro-control unit or the built-in read-only storage of microprocessor.
Fig. 2 be the present invention conditional access chip selftest method flow chart, please refer to Fig. 1 and Fig. 2 with
Understand the details of operation of the present invention.Test first carries out the initialization (step S210) of system when starting, such as resets scan chain
Logic unit, the counter for resetting control unit and buffer etc..After completing initialization, control unit 120 is by chip institute evidence
Test clock pulse (step S220) is switched to by system clock with the clock pulse of running, that is, chip is switched to survey from mode of operation
Die trial formula.More particularly, when chip performs general utility functions in mode of operation, its each functional module may be with different works
Respective task is performed as clock pulse, these work time pulses are for example produced using the system clock of chip via phase-locked loop；
And in test pattern, all logic units are operated with identical test clock pulse.As shown in figure 1, control unit 120 by
The selecting system clock pulse CLK_sys of multiplexer 140 or test clock pulse CLK_test are controlled to be used as scanning by control signal Ctrl
Chain 110-1~110-N work time pulse CLK.In the present embodiment, when control signal Ctrl switches to enable by disabled (also
Can be conversely) represent chip test pattern entered by mode of operation, now multiplexer 140 by work time pulse CLK by system clock
CLK_sys switches to test clock pulse CLK_test.In one embodiment, clock pulse CLK_test is tested by being built into chip internal
Oscillating circuit 150 produced by.Safety and reliability when being advantageous in that lifting test is so designed that, because if test
Clock pulse is provided by chip exterior, then tests clock pulse and be easily tampered, cause test result manipulated.
Fig. 4 is refer to, Fig. 4 is the connection diagram of two logic units in scan chain of the invention.In scan chain except
Outside the logic unit 400 of concatenation, also comprising the logic circuit 450 between continuous two logic units 400.Logic circuit
450 refer to conditional access chip normal operating when, there is provided input signal give a logic unit 400 circuit.Each logic
Unit 400 includes trigger 410 and multiplexer 420.Trigger 410 is acted according to clock pulse CLK, and basis signal RESET is reset
Data stored by it.Input D data source has two, is data SI and data CA respectively, and multiplexer 420 is believed according to control
Number SE determines which kind of data input flip-flops 410, and control signal SE (is not illustrated in Fig. 1) as produced by control unit.Data
SI is the data that previous stage logic unit 400 directly exports in scan chain, in fact, data SI is test data Test_in
Or according to data caused by Test_in.Data CA is then the output of logic circuit 450.The output end Q couplings of trigger 410
The multiplexer 420 of next logic circuit 450 and next logic unit 400.By taking scan chain 110-1 as an example, when control is believed
Number SE controls the multiplexer 420 of all logic units 400 to switch to and receives data SI (step S230), then data SI cans exist
The each logic unit 400 being sequentially transferred in scan chain 110-1 in scan chain 110-1.Similar, scan chain 110-2~
110-N operation is identical with scan chain 110-1.
With continued reference to Fig. 1, scan chain 110-1~110-N output ends are by control multiplexer 165-1~165-N by work
Make output Data_out1~Data_outN switch to test output (step S240), so as to subsequent control unit 120 receive it is whole
Test result Test_out after conjunction is compared with corresponding test result.In following step S250, control
Unit 120 is scanned chain test according to the cycle of test clock pulse.Testing scanning chain proposed by the present invention includes scan chain
(shift) stage of displacement and acquisition (capture) stage, further test detail will illustrate afterwards.After the completion of to be tested,
Control unit 120 makes control signal Ctrl be changed into disabled state from enabled status, therefore multiplexer 165-1~165-N will be swept
Retouch chain 110-1~110-N output by test output switching be work export Data_out1~Data_outN (step S260),
And scan chain 110-1~110-N clock pulse is switched back into system clock CLK_ by multiplexer 140 by test clock pulse CLK_test
Sys (step S280), in addition, control unit 120 controls the multiplexer 420 of all logic units 400 to cut through control signal SE
It is changed to and receives data CA (step S270), so just complete the test of chip, chip can returns in general working condition, each function
Module performs the function of script.
In one embodiment, in order to save the storage area of storage element 130 and reduce control unit 120 with scanning
Pin count between chain 110-1~110-N, test data Test_in are stored in the form of compressing in storage element 130, and
Data are decompressed by decompression circuit 170 before scan chain 110-1~110-N is inputted, and in scan chain 110-1~110-
N output end also by compressor circuit 180 by all test output squeezings into test result Test_out.In an implementation
In example, decompression circuit 170 and compressor circuit 180 are by hardware implementation, and the output pin position number of decompression circuit 170 is equal to and swept
Chain 110-1~110-N number is retouched, but input pin position number is less than scan chain 110-1~110-N number, similarly, compression
The input pin position number of circuit 180 is equal to scan chain 110-1~110-N number, but output pin position number is less than scan chain
110-1~110-N number.DFTMAX compression/decompression circuits can be used to carry out for decompression circuit 170 and compressor circuit 180
Implementation, but it is not subject to the limits.
Fig. 3 is the detailed process of Fig. 2 steps S250 testing scanning chain.When testing scanning chain starts, control unit 120 is first
The read test data (step S252) from storage element 130.The test data of reading can partly or entirely keep in single to control
In buffer (not shown) inside member 120, in order to be rapidly available to scan chain 110-1~110-N in test process.Connect down
Data SI input scan chains (step S254) caused by being decompressed according to test data Test_in.It note that due to this hair
Bright test data can also uncompressed kenel be stored in storage element 130, electricity need not be decompressed in this case
Road 170 and compressor circuit 180, and scan chain can be inputted directly using test data as data SI.The step of please also refer to Fig. 2
S220, due to work time pulse CLK is switched into test clock pulse CLK_test by system clock CLK_sys in a step 220,
Therefore data SI will test clock cycle to one logic unit of front transfer in scan chain 110-1~110-N with one
Speed transmits to scan chain 110-1~110-N output end.
As it was previously stated, the test of scan chain can be subdivided into shift phase and capture the stage.Shift phase is used for utilizing number
All triggers 410 are filled up according to SI, and captures the stage and is then used for the logic tested between all logic unit and logic unit
Whether the running of circuit 450 is correct.In one embodiment, when control signal Ctrl enables, control signal SE is just effective,
It is exactly that the test that current scanline chain is just can control when control signal Ctrl enables is shift phase or captures the stage, another
In embodiment, also control signal SE directly can be used as using control signal Ctrl.Said below by taking a wherein scan chain 110-1 as an example
Bright shift phase and the test for capturing the stage.Assuming that scan chain 110-1 length is 400 logic units, data SI length
Also be 400 bits, then the continuous 400 all midcycle data SI for testing clock pulse CLK_test will between logic unit according to
Sequence is toward front transfer, until all logic units all temporal data SI, so just completes the data input (step of shift phase
S256), in short, shift phase is for making trigger 410 all on scan chain 110-1 is all temporary to have data SI；Then,
All multiplexers 420 choose data CA on control signal SE control scan chains 110-1, and carry out testing clock pulse CLK_test's
The input of a cycle, now trigger 410 all on scan chain 110-1 can all be obtained in response to the data CA each received
One new value is to complete the acquisition (step S257) in acquisition stage.Then, control signal SE is controlled on scan chain 110-1 and owned
Multiplexer 420 choose data SI again, be again introduced into shift phase, therefore in follow-up continuous 400 test clock pulses CLK_
Test all midcycle data SI input scan chain 110-1 again, until all logic units all temporal data SI, can so be incited somebody to action
The new value that all triggers 410 obtain in step S257 sequentially releases scan chain 110-1, and these new values are exactly test knot
Fruit Test_out, so just it is complete again shift phase data input (step S258).It note that secondary shift phase
It is to obtain the value that multiplexer 420 all on scan chain 110-1 newly obtains in the output end of scan chain, and the present invention is
Whether just to judge the logic circuit of multiplexer 420 all on these scan chains 110-1 and its correlation using these new values
Often.In addition, in another embodiment, all multiplexers 420 can also choose number in the stage of acquisition on scan chain 110-1
According to the input for carrying out testing more than clock pulse CLK_test a cycles after CA.In another embodiment, through operating in shifting repeatedly
The position stage continuously can be tested with capturing stage, the self-test circuit of the present invention for different data SI.
In order to save comparison number, control unit 120 can not check test result Test_ in each test clock cycle
Out, but compared again with expected test result after first carrying out computing to test result Test_out.The mode of computing has perhaps
It is more, for example with CRC (Cyclic Redundancy Check, CRC), but it is not limited.Control unit 120
CRC computing persistently then is carried out to new caused test result and existing test result, and with last computing
As a result compared as test result Test_out and with corresponding test result.
In addition, it refer to Fig. 5.Fig. 5 is the schematic diagram of another logic unit 500 in scan chain of the invention.Except patrolling
Collect outside unit 400, the logic unit 500 also includes a multiplexer 510.There is multiplexer 510 one first receiving terminal to receive CA_
O, CA_O are output of the logic circuit under normal use corresponding to the logic unit 500, and the multiplexer 510 also has one the
Two receiving terminals receive CA_P, and CA_P is a default logical signal.Due to many logic lists in whole conditional access chip
Member is relevant with other circuits outside chip, in order to be effectively isolated other circuits outside chip in test phase, in selftest
When, the logic unit 500 receives default logical signal CA_P according to control signal CA_SE, can so be carried in the acquisition stage
For CA_P as data CA, avoid being disturbed by chip exterior.At the end of test, the logic unit is according to control signal
CA_SE control receives CA_O, enabling.
In summary, the present invention forms scan chain by by the logic unit in chip, and directly scan chain is surveyed
Examination.If the key in chip is altered or stolen, it can learn that chip is destroyed by test result, next can make core
Piece stops normal work.Test data used in test process of the present invention is stored in chip internal in advance, rather than by outside defeated
Enter, it can be ensured that the security of test.In addition, it is used as test clock pulse using the oscillating circuit 150 that chip internal is additionally provided
Source, the closure of test system can be improved, avoids test process from being interfered.Furthermore test process of the invention can not
Test result must be checked in each test clock cycle, but be compared again with default data after test result is done into computing,
Help to reduce and compare number to improve testing efficiency.Decompression circuit 170 between scan chain and control unit 120 with
Compressor circuit 180 helps the storage area for reducing storage element 130, and the pin number of control unit 120.
Because the art tool usually intellectual can understand by the disclosure that Fig. 1 and Fig. 4 device is invented
The implementation detail of Fig. 2 and Fig. 3 method invention and change, thus while embodiments of the invention are as described above, but those realities
Apply example to be not used for limiting the present invention, the art tool usually intellectual can be according to the content expressed or implied of the present invention
Change is imposed to the technical characteristic of the present invention, all this kind change may belong to the patent protection category sought by the present invention,
In other words, scope of patent protection of the invention is defined by being defined by tbe claims.
Claims (18)
1. a kind of self-test circuit for being built into conditional access chip, conditional access chip utilizes multiple logic lists
Member one video-audio data of decryption, the self-test circuit include：
One storage element, for storing a test data and a comparison data；And
One control unit, those logic units are coupled, are used for：
Those logic units are controlled to receive a clock pulse to carry out a test；
The test data is read from the storage element；
The test data is inputted into the one scan chain that those logic units are formed according to the clock pulse；And
An output data of the scan chain is compared with the comparison data to obtain a test result.
2. self-test circuit as claimed in claim 1, it is characterised in that the clock pulse is one first clock pulse, when the test knot
Shu Shi, the control unit control those logic units to receive one second clock pulse, and second clock pulse is not equal to first clock pulse.
3. self-test circuit as claimed in claim 1, it is characterised in that also include：
One oscillating circuit, the control unit and those logic units are coupled, for producing the clock pulse.
4. self-test circuit as claimed in claim 1, it is characterised in that the scan chain output to should clock pulse continuous week
Multiple test results of phase, the output data are an operation result of those test results.
5. self-test circuit as claimed in claim 1, it is characterised in that the test bag captures rank containing a shift phase and one
Section, the logic unit in those logic units includes：
One trigger, comprising：
One first input end；
One second input, for receiving the clock pulse；And
One first output end, couple the latter logic unit of the logic unit；And
One multiplexer, comprising：
One the 3rd input, for receiving the test data of the previous logic unit of logic unit output；
One the 4th input, for receiving a normal data；And
One second output end, for exporting the test data to the first input end in the shift phase, and in the acquisition rank
Section exports the normal data to the first input end.
6. self-test circuit as claimed in claim 5, it is characterised in that the normal data is provided by a logic circuit.
7. self-test circuit as claimed in claim 5, it is characterised in that the multiplexer is one first multiplexer, the logic
Unit also includes：
One second multiplexer, comprising：
One the 5th input, for receiving a secure data；
One the 6th input, for receiving a non-secure data；And
One the 3rd output end, for exporting the secure data as the normal data in the acquisition stage, and in the test knot
The non-secure data is exported during beam as the normal data.
8. self-test circuit as claimed in claim 1, it is characterised in that those logic units form multiple scan chains, should
Self-test circuit also includes：
One decompression circuit, for decompressing the test data, the decompression circuit has an at least decompression circuit input
With multiple decompression circuit output ends, at least a decompression circuit input couples the control unit for this, those decompression circuits
Output end couples those scan chains, wherein of the number of the decompression circuit input less than those decompression circuit output ends
Number.
9. self-test circuit as claimed in claim 1, it is characterised in that those logic units form multiple scan chains, should
Self-test circuit also includes：
One compressor circuit, for compressing those output datas of those scan chains, the compressor circuit has an at least compressor circuit
Output end and multiple compressor circuit inputs, at least a compressor circuit output end couples the control unit for this, those compressor circuits
Input couples those scan chains, and the wherein number of the compressor circuit output end is less than the number of those compressor circuit inputs.
10. a kind of selftest method of conditional access chip, the conditional are accessed chip and decrypted using multiple logic units
One video-audio data, and comprising for storing a storage element of a test data and a comparison data, the selftest method
Comprising：
Those logic units are controlled to receive a clock pulse to carry out a test；
The test data is read from the storage element；
The test data is inputted into the one scan chain that those logic units are formed according to the clock pulse；And
An output data of the scan chain is compared with the comparison data to obtain a test result.
11. selftest method as claimed in claim 10, it is characterised in that the clock pulse is one first clock pulse, and this self is surveyed
Method for testing also includes：
At the end of the test, those logic units are controlled to receive one second clock pulse；
Wherein, second clock pulse is not equal to first clock pulse.
12. selftest method as claimed in claim 10, it is characterised in that conditional access chip, which also includes, to be used for producing
One oscillating circuit of the raw clock pulse, and be to access core without reference to the conditional only with reference to the clock pulse when test is carried out
One outside clock pulse of piece.
13. selftest method as claimed in claim 10, it is characterised in that also include：
The scan chain output to should clock pulse continuous cycles multiple test results；
Wherein, the output data is an operation result of those test results.
14. selftest method as claimed in claim 10, it is characterised in that the test bag captures containing a shift phase and one
Stage, the logic unit in those logic units include：
One trigger, comprising：
One first input end；
One second input, for receiving the clock pulse；And
One first output end, couple the latter logic unit of the logic unit；And
One multiplexer, comprising：
One the 3rd input, for receiving the test data of the previous logic unit output of the logic unit；
One the 4th input, for receiving a normal data；And
One second output end, for exporting the test data to the first input end in the shift phase, and in the acquisition rank
Section exports the normal data to the first input end.
15. selftest method as claimed in claim 14, it is characterised in that in the normal data carried by a logic circuit
For.
16. selftest method as claimed in claim 14, it is characterised in that the multiplexer is one first multiplexer, and this is patrolled
Unit is collected also to include：
One second multiplexer, comprising：
One the 5th input, for receiving a secure data；
One the 6th input, for receiving a non-secure data；And
One the 3rd output end, for exporting the secure data as the normal data in the acquisition stage, and in the test knot
The non-secure data is exported during beam as the normal data.
17. selftest method as claimed in claim 10, it is characterised in that those logic units form multiple scan chains,
The test data is a compressed data, and the selftest method also includes：
Before the test data is inputted into those scan chains, the test data is decompressed.
18. selftest method as claimed in claim 10, it is characterised in that those logic units form multiple scan chains,
The test data is a compressed data, and the selftest method also includes：
Before the output data and the preset data are compared, those output datas of those scan chains are compressed.
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| CN201610406032.0A CN107492395B (en) | 2016-06-12 | 2016-06-12 | Conditional access chip, built-in self-test circuit and test method thereof |
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| CN201610406032.0A CN107492395B (en) | 2016-06-12 | 2016-06-12 | Conditional access chip, built-in self-test circuit and test method thereof |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110031752A (en) * | 2018-01-11 | 2019-07-19 | 瑞昱半导体股份有限公司 | Self-test circuit and selftest method applied to comparator |
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