CN107483362A - A kind of method for dispatching message based on shift register - Google Patents
A kind of method for dispatching message based on shift register Download PDFInfo
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- CN107483362A CN107483362A CN201710561661.5A CN201710561661A CN107483362A CN 107483362 A CN107483362 A CN 107483362A CN 201710561661 A CN201710561661 A CN 201710561661A CN 107483362 A CN107483362 A CN 107483362A
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- Prior art keywords
- message
- shift register
- order
- streamline
- scheduling
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/50—Queue scheduling
- H04L47/60—Queue scheduling implementing hierarchical scheduling
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/50—Queue scheduling
- H04L47/58—Changing or combining different scheduling modes, e.g. multimode scheduling
Abstract
The present invention relates to a kind of method for dispatching message based on shift register, it is characterised in that comprises the following steps：Step S1：Determined to need the special packet field compared according to message processing request：Step S2：Determined to need the history message number L compared according to Message processing pipeline organization；Step S3：The series M of shift register is determined according to specific fields and storage resource；Step S4：Order-preserving requirement in stream treatment, the message of no order-preserving requirement between each other is divided into N classes, correspondingly realizes that a shift register treats schedules message to deposit per a kind of message.The message for having order-preserving requirement is placed in same shift register；Specific fields comparison function is performed by additional combinational logic, completes first order scheduling；Step S5：Second level scheduling is carried out in the result of first order scheduling, selects a message to be sent into Message processing streamline.
Description
Technical field
The invention belongs to computer communication technology field, and in particular to a kind of dispatching message side based on shift register
Method.
Background technology
Message is that information carrier is abstracted in computer and the communications field.According to different agreements, system is carried in message
Information required for system.In order to improve the rate of information throughput, generally use streamline mechanism carries out the processing of message.And in streamline
The message of each pipelining-stage there may exist conflict.Streamline must just be suspended when conflicting and producing, before producing conflict
One message is processed finish untill.By taking the processing of multipath server internal memory consistency protocol as an example, when the agreement for entering streamline
When message address is identical with some message address handled, protocol processes streamline must pause, and wait previous report
Text, which is disposed, could carry out the processing of next same address message.
In order to reduce the pause of streamline to greatest extent, often need to carry out cross scheduling to the message for being sent into streamline, make
Must pass through scheduling be sent into streamline a certain specific fields of message queue correlation reduce, reduce pipeline stall frequency and
Duration.
Variety classes message is divided into N classes by prior art according to specific fields, by sorted packet buffer in N number of storage
In device, then streamline is sent into the different message crossbar scheduling of specific fields from memory.Assisted with server memory uniformity
Exemplified by discussing Message processing, each message for preparing to be sent into streamline is classified according to address, sorted message is alternately sent into
Streamline, as shown in Figure 1.
The shortcomings that prior art is：
Firstth, low to memory resource utilization rate, carrying out sorted message according to specific fields needs to be stored in N number of memory
In, once one of memory is full, it is necessary to stop the write-in of such all message, even if other memories still have storage
Space.
Secondth, the order-preserving requirement between variety classes message can not be met.When carrying out message classification, the order of message has been
Through being disturbed, being sent into the order of streamline can not ensure.This is the deficiencies in the prior art part.
Therefore, for drawbacks described above of the prior art, there is provided a kind of dispatching message side based on shift register of design
Method；To solve above-mentioned technical problem, it is necessary.
The content of the invention
It is an object of the present invention in view of the above-mentioned drawbacks of the prior art, providing design one kind is based on shift LD
The method for dispatching message of device, to solve above-mentioned technical problem；To lift memory utilization rate, and meet the guarantor between different messages
Sequence requirement.
To achieve the above object, the present invention provides following technical scheme：
A kind of method for dispatching message based on shift register, it is characterised in that comprise the following steps：
Step S1：Determined to need the special packet field compared according to message processing request：
Step S2：Determined to need the history message number L compared according to Message processing pipeline organization；Wherein pipeline organization is main
Consider protocol processes streamline classification number and data forwarding design.
Step S3：The series M of shift register is determined according to specific fields and storage resource；
Step S4：Order-preserving requirement in stream treatment, the message of no order-preserving requirement between each other is divided into N classes, it is each
Class message correspondingly realizes that a shift register treats schedules message to deposit.The message for having order-preserving requirement is placed on same displacement and posted
In storage.The effect of the shift register is storage message to be scheduled, while performs specific word by additional combinational logic
Section comparison function, complete first order scheduling.The message stored in every grade of register of shift register all carries out special with history message
Determine the comparison of field, due to there is L history message, perform L times altogether relatively.If comparative result is identical to be referred to as hit at first time.Displacement
In register schedules message is treated by the use of 1bit memory spaces as significance bit to identify to whether there is in certain one-level of shift register.
For the shift register of no order-preserving requirement, conduct first order scheduling knot of the selection without hit in needed schedules message
Fruit.For the shift register of order-preserving requirement be present, message sets sequence identification word in a shift register when entering register
Section, it is each message allocation order mark in register.Wherein adjacent can distribute same order mark with out of order message
Know, it is impossible to which the sequence identification of out of order message distribution is also different.By effective message in present shift register near afterbody
Affiliated sequence identification is stored in a mark comparand register, is selected in schedules message is treated without hit and sequence identification
With mark comparand register identical message as first order scheduling result.It is not hit by both the above situation if multiple
Message or all messages are all hit, then selection is sent out near the message of afterbody as first order scheduling result.By selection
Schedules message significance bit zero setting, expression current location are room.It is new when schedules message delivers to shift register when having, displacement
Every one-level of register is all judged itself and all rear class significance bits, if there is room（Including itself being room）,
Then the input of this grade of register is the output of prime（The input of the first order is new message）, otherwise this grade input is defeated for itself
Go out.For the shift register for needing order of addition to identify, the message being newly sent into needs to judge the guarantor between a upper message
Order relation, if can otherwise produce new sequence identification to continue to use old sequence identification if out of order.By sequence identification and message one
Play feeding shift register.
Step S5：Second level scheduling is carried out in the result of first order scheduling, selects a message to be sent into Message processing stream
Waterline.Scheduling mode can be the poll to variety classes message, can be different types of message according to certain condition during poll
Different weights is assigned, also can the message submitting different with history of prioritizing selection critical field.It can stop if necessary to streamline
Schedules message, it is equal to pipeline stall.
Preferably, determine that the special packet field for needing to compare is in the step S1：
The message handled when message carries out pipeline processes, in each level production line is unable to identical field, and according to patrolling
The complexity and timing requirements collected, select the special packet field to be compared.
Preferably, L setting should meet following standard in the step S2：
When the interval that two specific fields identical messages enter streamline is more than or equal to L, streamline is without pausing.
Preferably, in the step S3, the selections of M values according to system memory resources, logical complexity and timing requirements,
And meet above restrictive condition.
The beneficial effects of the present invention are will treat that schedules message is cached into the storage organization based on shift register, lead to
Cross and compare each effectively content of message and scheduled history message in shift register, find out specific fields and history message is special
That determines field correlation minimum treats that schedules message is sent into Message processing streamline, and it is specific to reduce Message processing streamline messages at different levels
The correlation ratio of field is so as to reducing pipeline stall.
In addition, design principle of the present invention is reliable, and it is simple in construction, there is very extensive application prospect.
As can be seen here, the present invention compared with prior art, has prominent substantive distinguishing features and significantly improved, it is implemented
Beneficial effect be also obvious.
Brief description of the drawings
Fig. 1 is prior art schematic diagram.
Fig. 2 is the message crossbar scheduling entire block diagram based on shift register.
Fig. 3 is the shift register storage schematic diagram for having isotonicity requirement.
Fig. 4 is shift register partial structurtes diagram.
Embodiment
Below in conjunction with the accompanying drawings and the present invention will be described in detail by specific embodiment, and following examples are to the present invention
Explanation, and the invention is not limited in implementation below.
Reference picture 2-4 provides specific examples below to the present invention：
Assuming that needing to handle the class messages of A/B/C/D tetra-, streamline is detected in clear text address field and streamline
The message address field of processing will cause pipeline stall when identical, address field is 20.B and C has order-preserving in four class messages
It is required that is, variety classes message need to follow the processing sequence of first in first out, but one species message can be other with reversed order
There is no order-preserving requirement between species message.Accordingly, BC classes message needs to enter same shift register, and A, D class message
Order-preserving requirement need not be considered, different shift registers can be respectively enterd.The digit compared in view of specific fields it is more, it is necessary to
Combinational logic it is more complicated, the maximum clock frequency of system can be influenceed, least-significant byte in address can be chosen as the spy for comparing
Determine field.Assuming that the minimum interval L of streamline requirement is 4, then to record low 8 bit of message address in 4 grades before streamline.
Consider system memory space, the series M of shift register is set to 32.Each shift register is in addition to recorded message, it is also necessary to
One Bits Expanding position identifies whether the message in actual registers is effective, if effectively also referred to as actual registers non-NULL, invalid title
Actual registers are sky.When carrying out first order scheduling, 4 grades of messages is specific before the shift register and streamline of each non-NULL
Field（Address least-significant byte）It is compared, if 4 comparisons are different from, the message is an alternative objects.It is if such
Message more than one, or all messages have the appearance of specific fields identical situation in comparison, then are being shifted according to message
Position in register, by the message submitting near shift register afterbody.Its significance bit zero setting of the message of submitting, mark should
Position is empty.When there is new message generation to need to be sent into shift register, all shift register levels are all to itself and rear class
Effective bit flag judged, if had vacant position, using prime output as the input of oneself, otherwise by the output of itself
Loop back to input.For BC class messages, also need to set sequence identification field in a shift register, enter a message whenever newly
When, first determine whether message species is identical with upper one.If identical, the content of sequence identification field keeps constant, such as
Fruit is different, then the content of sequence identification field is also different, as shown in Figure 2.The shift register of BC classes message has 32 grades in this example,
32 different sequence identifications are at most needed, therefore sequence identification may be configured as 5.Set marker register, its value be near
Sequence identification corresponding to effective message of shift register afterbody, message 2 is posted near displacement in the scene shown in Fig. 2
Effective message of storage tail, so the value of marker register is 10011.For having the message of order-preserving requirement, the corresponding first order
In addition to meeting the different condition of specific fields described above, its sequence identification field must also be posted scheduling result with mark
Content in storage is identical, to ensure the order-preserving requirement between message.Dispatched by the first order, at most there may be 3 effectively
Treat schedules message, second level scheduling can select the result feeding streamline that the first order is dispatched using poll by the way of, also can be excellent
First select the specific fields message different from current pipeline.If if it is necessary, can during currently without satisfactory message
Suspend the scheduling to streamline, to substitute pipeline stall operation.
Disclosed above is only the preferred embodiment of the present invention, but the present invention is not limited to this, any this area
What technical staff can think does not have creative change, and some improvement made without departing from the principles of the present invention and
Retouching, should all be within the scope of the present invention.
Claims (4)
1. a kind of method for dispatching message based on shift register, it is characterised in that comprise the following steps：
Step S1：Determined to need the special packet field compared according to message processing request：
Step S2：Determined to need the history message number L compared according to Message processing pipeline organization；
Step S3：The series M of shift register is determined according to specific fields and storage resource；
Step S4：Order-preserving requirement in stream treatment, the message of no order-preserving requirement between each other is divided into N classes, it is each
Class message correspondingly realizes that a shift register treats schedules message to deposit；The message for having order-preserving requirement is placed on same displacement and posted
In storage；Specific fields comparison function is performed by additional combinational logic, completes first order scheduling；
Step S5：Second level scheduling is carried out in the result of first order scheduling, selects a message to be sent into Message processing streamline.
A kind of 2. method for dispatching message based on shift register according to claim 1, it is characterised in that the step
Determine that the special packet field for needing to compare is in S1：
The message handled when message carries out pipeline processes, in each level production line is unable to identical field, and according to patrolling
The complexity and timing requirements collected, select the special packet field to be compared.
3. a kind of method for dispatching message based on shift register according to claim 1 or 2, it is characterised in that described
L setting should meet following standard in step S2：
When the interval that two specific fields identical messages enter streamline is more than or equal to L, streamline is without pausing.
A kind of 4. method for dispatching message based on shift register according to claim 3, it is characterised in that the step
In S3, the selection of M values meets above restrictive condition according to system memory resources, logical complexity and timing requirements.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114006862A (en) * | 2021-10-29 | 2022-02-01 | 锐捷网络股份有限公司 | Message forwarding method, device and equipment and computer storage medium |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101291194A (en) * | 2008-05-20 | 2008-10-22 | 华为技术有限公司 | Method and system for keeping sequence of report |
| CN101771595A (en) * | 2008-12-29 | 2010-07-07 | 华为技术有限公司 | Method and device for preserving order of message |
| CN102811169A (en) * | 2012-07-24 | 2012-12-05 | 成都卫士通信息产业股份有限公司 | Virtual private network (VPN) implementation method and system for performing multi-core parallel processing by using Hash algorithm |
| US20140185451A1 (en) * | 2012-12-31 | 2014-07-03 | Telefonaktiebolaget L M Ericsson (Publ) | Low pass filter for hierarchical pipelined distributed scheduling traffic manager |
| CN105162725A (en) * | 2015-09-22 | 2015-12-16 | 浪潮(北京)电子信息产业有限公司 | Method and device for preprocessing message addresses in protocol processing pipeline |
-
2017
- 2017-07-11 CN CN201710561661.5A patent/CN107483362A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101291194A (en) * | 2008-05-20 | 2008-10-22 | 华为技术有限公司 | Method and system for keeping sequence of report |
| CN101771595A (en) * | 2008-12-29 | 2010-07-07 | 华为技术有限公司 | Method and device for preserving order of message |
| CN102811169A (en) * | 2012-07-24 | 2012-12-05 | 成都卫士通信息产业股份有限公司 | Virtual private network (VPN) implementation method and system for performing multi-core parallel processing by using Hash algorithm |
| US20140185451A1 (en) * | 2012-12-31 | 2014-07-03 | Telefonaktiebolaget L M Ericsson (Publ) | Low pass filter for hierarchical pipelined distributed scheduling traffic manager |
| CN105162725A (en) * | 2015-09-22 | 2015-12-16 | 浪潮(北京)电子信息产业有限公司 | Method and device for preprocessing message addresses in protocol processing pipeline |
Non-Patent Citations (1)
| Title |
|---|
| 宋宇飞 等: ""基于IP协议的FPGA万兆可靠互联通信设计与实现"", 《上海大学学报（自然科学版）》 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114006862A (en) * | 2021-10-29 | 2022-02-01 | 锐捷网络股份有限公司 | Message forwarding method, device and equipment and computer storage medium |
| CN114006862B (en) * | 2021-10-29 | 2023-10-20 | 锐捷网络股份有限公司 | Message forwarding method, device and equipment and computer storage medium |
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