CN107481752B - Method for refreshing, refresh control circuit and the semiconductor memory of semiconductor memory - Google Patents
Method for refreshing, refresh control circuit and the semiconductor memory of semiconductor memory Download PDFInfo
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- CN107481752B CN107481752B CN201710725168.2A CN201710725168A CN107481752B CN 107481752 B CN107481752 B CN 107481752B CN 201710725168 A CN201710725168 A CN 201710725168A CN 107481752 B CN107481752 B CN 107481752B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40622—Partial refresh of memory arrays
Abstract
The present invention relates to a kind of method for refreshing of semiconductor memory, including：When semiconductor memory initializes, the current state of memory block each in semiconductor memory is set as to prevent the state refreshed；When storage arbitrary row in the block is accessed, then the current state of memory block is reset to the state for allowing to refresh, the refresh operation signal according to input to be allowed to carry out refresh operation to memory block；When storage arbitrary row in the block is not accessed, then the state for keeping memory block is the state of the prevention refreshing of initialization, and refresh operation is carried out to memory block according to the refresh operation signal of input with prevention.The present invention also provides a kind of refresh control circuit and a kind of semiconductor memories including refresh control circuit, have said effect.
Description
Technical field
The present invention relates to semiconductor memory technologies field, more particularly to a kind of method for refreshing of semiconductor memory,
Refresh control circuit and semiconductor memory.
Background technology
There is dynamic random access memory (Dynamic Random Access Memory, DRAM) very low unit to deposit
Cost and very high integration density are stored up, is widely used in computer system, DRAM belongs to volatile memory device, in order to protect
It holds data not lose, needs to carry out refresh operation, joint electron device engineering council (Joint Electron Device
Engineering Council, JEDEC) standard provides that the refresh cycle of DRAM cell is 64ms (being 32ms under high temperature), it is desirable that
Each refresh cycle once refreshes all rows, and to preserve data, if do not refreshed, the information of storage will lose.So
And during refreshing, all rows of all memory blocks in dynamic random access memory are refreshed, cause refreshing frequency more,
The defects of power consumption is big.
Therefore, how reducing refreshing frequency, reducing power consumption is that those skilled in the art are badly in need of technical problems to be solved.
Disclosed above- mentioned information is only used for strengthening the understanding of the background to the present invention in the background technology, therefore it may be wrapped
Containing the information for not being formed as the prior art that those of ordinary skill in the art are known.
Invention content
In view of this, the embodiment of the present invention is desirable to provide a kind of method for refreshing of semiconductor memory, refresh control circuit
And semiconductor memory, at least to solve technical problem in the prior art.
The technical solution of the embodiment of the present invention is achieved in that according to one embodiment of present invention, provides a kind of half
The method for refreshing of conductor memory, including：
When semiconductor memory initializes, the current state of memory block each in the semiconductor memory is set as hindering
The state only refreshed；
When the storage arbitrary row in the block is accessed, then being reset to the current state of the memory block allows to refresh
State, to allow to carry out refresh operation to the memory block according to the refresh operation signal of input；
When the storage arbitrary row in the block is not accessed, then the state for keeping the memory block is initialization
The state for preventing to refresh, the refresh operation signal according to input to be prevented to carry out refresh operation to the memory block.
Preferably, in the method for refreshing of above-mentioned semiconductor memory, the step of above-mentioned prevention Flushing status, includes：
The power-on reset signal inputted when the state storage circuitry of the semiconductor memory is according to initialization will be described each
The current state of memory block is set as the state for preventing to refresh.
Preferably, in the method for refreshing of above-mentioned semiconductor memory, the step of above-mentioned permission Flushing status, includes：
Calling-on signal and institute of the state storage circuitry according to the arbitrary row in the block to the storage of acquisition
Power-on reset signal is stated, output allows refresh signal；
Logic circuit does logic and operation to the permission refresh signal and the refresh operation signal of input, and output is permitted
Perhaps refresh operation signal, the memory block to be allowed to carry out refresh operation to itself according to the permission refresh operation signal.
Preferably, in the method for refreshing of above-mentioned semiconductor memory, when the storage arbitrary row in the block not by
During access, then the state for keeping the memory block is the state of the prevention refreshing of initialization, to prevent the institute according to input
It states refresh operation signal and refresh operation is carried out to the memory block, including：
The state storage circuitry prevents refresh signal according to the power-on reset signal, output；
Logic circuit does logic and operation, output resistance to the refresh operation signal of the prevention refresh signal and input
Only refresh operation signal, the refresh operation signal according to input to be prevented to carry out refresh operation to the memory block.
Preferably, in the method for refreshing of above-mentioned semiconductor memory, the refresh operation include automatic refresh operation or
Person's self refresh operation.
The present invention also provides a kind of refresh control circuits, and applied to the refreshing to semiconductor memory, the semiconductor is deposited
Reservoir has at least one memory block, and the refresh control circuit includes at least one control unit, described control unit and institute
Memory block connection is stated, described control unit is used for when semiconductor memory initializes, will respectively be deposited in the semiconductor memory
The current state of storage block is set as the state for preventing to refresh；When the storage arbitrary row in the block is accessed, then deposited described
The current state of storage block is reset to the state for allowing to refresh, with allow according to the refresh operation signal of input to the memory block into
Row refresh operation；When the storage arbitrary row in the block is not accessed, then the state for keeping the memory block is initial
The state that the prevention changed refreshes, to prevent to carry out refreshing behaviour to the memory block according to the refresh operation signal of input
Make.
Preferably, in above-mentioned refresh control circuit, described control unit includes：
State storage circuitry, for according to the power-on reset signal that inputs during initialization by the current shape of each memory block
State is set as the state for preventing to refresh.
Preferably, in above-mentioned refresh control circuit, the state storage circuitry is additionally operable to be deposited to described according to acquisition
The calling-on signal and the power-on reset signal, output for storing up the arbitrary row in the block allow refresh signal；On described
Reset signal, output prevent refresh signal.
Preferably, in above-mentioned refresh control circuit, described control unit further includes：
Logic circuit, for doing logic and operation to the permission refresh signal and the refresh operation signal of input,
Output allows refresh operation signal, the memory block to be allowed to carry out refreshing behaviour to itself according to the permission refresh operation signal
Make；Logic and operation is done to the prevention refresh signal and the refresh operation signal of input, output prevents refresh operation from believing
Number, the refresh operation signal according to input to be prevented to carry out refresh operation to the memory block.
Preferably, in above-mentioned refresh control circuit, described control unit connects one to one with the memory block.
The present invention also provides a kind of semiconductor memory, including refresh control circuit described in any one of the above embodiments.This hair
It is bright due to using the technology described above, has the following advantages：The current state of memory block is initialized as preventing brush by this programme
New state, later by judging whether storage arbitrary row in the block is accessed, to confirm whether memory block should be refreshed behaviour
Make, when storage arbitrary row in the block is accessed, refresh operation is carried out to the memory block, when the storage arbitrary row in the block
When not accessed, the refresh operation to memory block is prevented, realizes few refreshing frequency, the purpose for saving electric energy, reducing power consumption.
Above-mentioned general introduction is merely to illustrate that the purpose of book, it is not intended to be limited in any way.Except foregoing description
Schematical aspect, except embodiment and feature, by reference to attached drawing and the following detailed description, the present invention is further
Aspect, embodiment and feature will be what is be readily apparent that.
Description of the drawings
In the accompanying drawings, unless specified otherwise herein, otherwise represent the same or similar through the identical reference numeral of multiple attached drawings
Component or element.What these attached drawings were not necessarily to scale.It should be understood that these attached drawings are depicted only according to the present invention
Some disclosed embodiments, and should not serve to limit the scope of the present invention.
Fig. 1 is the method for refreshing flow diagram of semiconductor memory provided in an embodiment of the present invention；
Fig. 2 is refresh control circuit schematic diagram provided in an embodiment of the present invention；
Fig. 3 is semiconductor memory schematic diagram provided in an embodiment of the present invention；
Fig. 4 is refresh control flow chart of the refresh control circuit provided in an embodiment of the present invention to semiconductor memory.
Reference numeral
1- memory block 2- control unit 3- storage units；
21- logic circuit 22- state storage circuitries.
Specific embodiment
Hereinafter, certain exemplary embodiments are simply just described.As one skilled in the art will recognize that
Like that, without departing from the spirit or scope of the present invention, described embodiment can be changed by various different modes.
Therefore, attached drawing and description are considered essentially illustrative rather than restrictive.
In the description of the present invention, it is to be understood that term " center ", " longitudinal direction ", " transverse direction ", " length ", " width
Degree ", " thickness ", " go up ", " under ", " preceding ", " afterwards ", " left side ", " right side ", " vertically ", " level ", " top ", " bottom ", " interior ", " outside ", "
Clockwise ", " counterclockwise ", " axial direction ", " " it is based on orientation shown in the drawings or position to wait the orientation of instructions or position relationship to radial direction
Relationship is put, be for only for ease of the description present invention and simplifies description rather than instruction or implies that signified device or element are necessary
With specific orientation, with specific azimuth configuration and operation, therefore be not considered as limiting the invention.In addition, term "
Be only used for description purpose first ", " second ", and it is not intended that instruction or imply relative importance or it is implicit indicate it is indicated
Technical characteristic quantity.Define " first " as a result, the feature of " second " can express either implicitly include one or
More described features.In the description of the present invention, " multiple " are meant that two or more, unless otherwise clearly specific
Restriction.
In the description of the present invention, it should be noted that unless otherwise clearly defined and limited, term " installation ", " phase
Even ", " connection ", " fixation " should be interpreted broadly, for example, it may be being fixedly connected or being detachably connected or integrally
Connection：Can be mechanically connected or be electrically connected or can mutually communicate；It can be directly connected, it can also be in
Between medium be indirectly connected, can be the interaction relationship of connection inside two elements or two elements.For this field
For those of ordinary skill, the concrete meaning of above-mentioned term in the present invention can be understood as the case may be.
In the present invention unless specifically defined or limited otherwise, fisrt feature second feature its " upper " or it " under "
It can be in direct contact including the first and second features, it is not to be in direct contact but pass through it that can also include the first and second features
Between other characterisation contact.Moreover, fisrt feature second feature " on ", " top " and " above " include first spy
Sign is right over second feature and oblique upper or is merely representative of fisrt feature level height higher than second feature.Fisrt feature exists
Second feature " under ", " lower section " and " following " right over second feature and oblique upper or be merely representative of including fisrt feature
Fisrt feature level height is less than second feature.
Following disclosure provides many different embodiments or example is used for realizing the different structure of the present invention.In order to
Simplify disclosure of the invention, hereinafter the component of specific examples and setting are described.Certainly, they are merely examples, and
And it is not intended to limit the present invention.In addition, the present invention can in different examples repeat reference numerals and/or reference letter,
This repetition is for purposes of simplicity and clarity, itself not indicate between discussed various embodiments and/or setting
Relationship.In addition, the present invention provides various specific techniques and material example, but those of ordinary skill in the art can be with
Recognize the application of other techniques and/or the use of other materials.
In a kind of specific embodiment, a kind of method for refreshing of semiconductor memory is provided, as shown in Figure 1, Figure 2 and Fig. 3
It is shown, including：
Step S1：When semiconductor memory initializes, the current state of memory block each in semiconductor memory is set
For the state for preventing to refresh.
Wherein, as shown in figure 3, containing the larger storage unit 3 of some data storage capacities in semiconductor memory,
The smaller memory block 1 of multiple data storage capacities is contained in storage unit 3 again, each memory block 1 is grasped by initialization
Make, there are many control modes involved in present embodiment, can be to each memory block 1 individually control or simultaneously
Control, in protection domain.Memory block 1 can realize depositing for automatic refresh operation or self refresh operation by control unit 2
Store up block.
Power-on reset signal (Power Up signals) is inputted to refresh control circuit, refresh control circuit output prevents to refresh
To memory block 1, current state is initialized as preventing the state refreshed, memory block 1 according to prevention refresh signal signal by memory block 1
It is initialized under the control of refresh control circuit, prevents outer its refresh operation of bound pair.
Step S21：When the arbitrary row in memory block 1 is accessed, then being reset to the current state of memory block 1 allows to brush
New state, the refresh operation signal according to input to be allowed to carry out refresh operation to memory block 1.
When accessing any one row (row) in a memory block 1, the refresh control circuit of the memory block 1 is set as
Allow to refresh, as inputted Active signals (the Active signals are to be directed in a memory block 1 at least visit order of a line),
Refresh control circuit is generated according to Active signals allows refresh signal, and the refresh control circuit of this memory block 1 is set as
Allow to refresh.If controlling whether to refresh with non-(nand) logic gate using one, after electrification reset, control circuit output
Logic level " 0 ", after allowing refreshing, refresh control circuit output logic level " 1 ".When there is refresh operation signal, (Refresh believes
Number) input when, refresh control circuit allows to refresh according to refresh signal and Refresh signals is allowed to generate new signal
Operation signal carries out refresh operation to memory block 1.
Step S22：When the arbitrary row in memory block 1 is not accessed, then the state for keeping memory block 1 is the resistance of initialization
The state only refreshed, the refresh operation signal according to input to be prevented to carry out refresh operation to memory block 1.
When any one row is all not visited in memory block 1, Active signals are not inputted such as, then memory block 1
Refresh control circuit keeps initializing later state, does not allow to refresh memory block 1.If there is being subsequently directed to this storage
The refresh operation of block 1 such as inputs Refresh signals, can be automatically skipped, so as to achieve the purpose that power saving.
The current state of memory block 1 is initialized as preventing the state refreshed by this programme, later by judging in memory block 1
Arbitrary row whether be accessed, to confirm whether memory block 1 should be refreshed operation, when the arbitrary row in memory block 1 is accessed
When, refresh operation is carried out to the memory block 1, when the arbitrary row in memory block 1 is not accessed, is prevented to memory block 1
Refresh operation, realize few refreshing frequency, save electric energy, reduce power consumption and improve the purpose of system performance.
On the basis of the method for refreshing of semiconductor memory, when semiconductor memory initializes, by semiconductor storage
The current state of each memory block 1 is set as the state for preventing to refresh in device, including：
The state storage circuitry 22 of semiconductor memory is according to the power-on reset signal that inputs during initialization by each memory block 1
Current state be set as prevent refresh state.
Wherein, the input terminal input power-on reset signal of state storage circuitry 22, output terminal connection memory block 1 use state
Storage circuit 22 in storage memory block 1 current state, and according to power-on reset signal initialize memory block 1 current state
For the state for preventing to refresh.
It, then will storage when the arbitrary row in memory block 1 is accessed on the basis of the method for refreshing of semiconductor memory
The current state of block 1 is reset to the state for allowing to refresh, to be refreshed according to the refresh operation signal of input to memory block 1
Operation, including：
State storage circuitry 22 is believed according to the calling-on signal and electrification reset to the arbitrary row in memory block 1 of acquisition
Number, output allows refresh signal；
To the refresh operation signal of refresh signal and input is allowed to do logic and operation, output allows to refresh logic circuit 21
Operation signal, so that memory block 1 carries out refresh operation according to permission refresh operation signal to itself.
Wherein, it inputs in the state storage circuitry 22 in the calling-on signal of arbitrary row such as Active signals to control unit 2,
State storage circuitry 22 combines the calling-on signal such as Active signals of power-on reset signal and arbitrary row, it is handled,
Output allows refresh signal, and the control circuit of this memory block 1 is positioned to allow for refreshing, when there is the input of Refresh signals,
State storage circuitry 22 allows refresh operation signal according to refresh signal and Refresh signals is allowed to generate new signal,
The permission refresh operation signal of generation is sent to memory block 1 by the logic circuit 21 in control circuit, and memory block 1 is refreshed
Operation.
On the basis of the method for refreshing of semiconductor memory, when the arbitrary row in memory block 1 is not accessed, then keep
The state of memory block 1 is the state that the prevention of initialization refreshes, to prevent the refresh operation signal according to input to memory block 1
Refresh operation is carried out, including：
State storage circuitry 22 prevents refresh signal according to power-on reset signal, output；
To the refresh operation signal of refresh signal and input is prevented to do logic and operation, output prevents to refresh logic circuit 21
Operation signal, so that the refresh operation signal according to input is prevented to carry out refresh operation to memory block 1.
Wherein, the calling-on signal such as Active of arbitrary row believes in state storage circuitry 22 is not received to memory block 1
Number when, state storage circuitry 22 still prevents refresh signal from controlling the memory block 1 to keep original init state by output,
Even if state storage circuitry 22 has received the refresh operation signal of input, by with after operation, exporting and refresh operation being prevented to believe
Number to memory block 1, the refresh operation to memory block 1 is prevented.
Further, in the method for refreshing of above-mentioned semiconductor memory, refresh operation include automatic refresh operation or
Self refresh operation.
Wherein, refresh operation includes automatic refresh operation (Auto Refresh, AR) and self refresh operation (Self
Refresh, SR), whether which kind of refreshing mode, does not all need to be external and provides row address information, because this is an inside
It is automatically brought into operation.There are one row address generators (also referred to as refresh counter) in automatic refresh operation, inside semiconductor memory to use
Row address automatically is sequentially generated, due to refreshing is carried out for all memory banks in a line, so without arranging addressing, added
Fast refresh rate.Data of the semiconductor memory under suspend mode low power consumpting state are then realized in self refresh operation to protect
It deposits.It should be noted that embodiment of the present invention includes but not limited to above two mode to the refresh operation of memory block 1, also
Can be it is other in refresh operation, in protection domain.
In another embodiment specific implementation mode, a kind of refresh control circuit is additionally provided, as shown in Fig. 2, applied to half-and-half
The refreshing of conductor memory, semiconductor memory have at least one memory block 1, and the refresh control circuit includes at least one
Control unit 2, control unit 2 are connect with memory block 1, and control unit 2 is used for when semiconductor memory initializes, by semiconductor
The current state of each memory block 1 is set as the state for preventing to refresh in memory；When the arbitrary row in memory block 1 is accessed,
The current state of memory block 1 is then reset to the state for allowing to refresh, to allow the refresh operation signal according to input to storage
Block 1 carries out refresh operation；When the arbitrary row in memory block 1 is not accessed, then the state for keeping memory block 1 is the resistance of initialization
The state only refreshed, the new operation signal according to input to be prevented to carry out refresh operation to memory block 1.It is pointed out that phase
Corresponding to the method for refreshing of above-mentioned semiconductor memory, refresh control circuit can there are many design method, refresh control circuit packets
It includes but is not limited to the embodiment proposed in this programme.
Further, in above-mentioned refresh control circuit, control unit 2 includes：
State storage circuitry, for according to the power-on reset signal that inputs during initialization by the current of each memory block 1
State is set as the state for preventing to refresh.
As shown in Fig. 2, power-on reset signal is input to the R ends of state storage circuitry 2, the S ends of state storage circuitry 22 are simultaneously
There is not any signal to input, then export and prevent in refresh signal to memory block 1, subsequently stored if there is refresh operation signal inputs
Block 1, memory block 1 are equivalent to the closed state that memory block 1 at this time is in initialization according to refresh signal is prevented to prevent to refresh.
Further, in above-mentioned refresh control circuit, the state storage circuitry is additionally operable to according to acquisition to described
The calling-on signal and the power-on reset signal of the arbitrary row in memory block 1, output allow refresh signal；According to described
Power-on reset signal, output prevent refresh signal.
As shown in Fig. 2, power-on reset signal is input to the R ends of state storage circuitry 22, the S ends of state storage circuitry 22 are defeated
Enter the calling-on signal to the arbitrary row in memory block 1, by the logical operation of state storage circuitry 22, output allows refresh signal
Into memory block 1, subsequently if there is refresh operation signal input memory block 1, memory block 1 according to allow refresh signal to itself into
Row refreshes, and is equivalent to memory block 1 at this time and is in unlatching Flushing status.
Further, in above-mentioned refresh control circuit, described control unit 2 further includes：
Logic circuit 21, for doing logical AND fortune to the permission refresh signal and the refresh operation signal of input
It calculates, output allows refresh operation signal, the memory block 1 to be allowed to be brushed according to the permission refresh operation signal to itself
New operation；Logic and operation is done to the refresh operation signal of the prevention refresh signal and input, output prevents to refresh behaviour
Make signal, the refresh operation signal according to input to be prevented to carry out refresh operation to the memory block 1.
If there is refresh operation signal inputs memory block 1, memory block 1 is equivalent to according to refresh signal is prevented to prevent to refresh
Memory block 1 is in the closed state of initialization at this time；And subsequently if there is refresh operation signal inputs memory block 1, memory block 1
According to refresh signal is allowed to refresh itself, it is equivalent to memory block 1 at this time and is in unlatching Flushing status, open refresh operation
It is also realized with the operation for closing refreshing by logic circuit 21, there are two input terminal, first input ends for the tool of logic circuit 21
It is connect with the output terminal of state storage circuitry 22, for inputting refresh operation signal, output terminal connects the second input terminal with memory block
It connects.For logic circuit 21 to the refresh operation signal of refresh signal and input is allowed to do logic and operation, output allows refresh operation
Signal, so that memory block carries out refresh operation according to permission refresh operation signal to itself；Or, logic circuit 21 is to preventing to refresh
Signal and the refresh operation signal of input do logic and operation, and output prevents refresh operation signal, to prevent according to input
The refresh operation signal carries out refresh operation to the memory block.
Further, in above-mentioned refresh control circuit, control unit 2 connects one to one with memory block 1.
Wherein, including multiple memory blocks 1 in a memory Bank, each memory block 1 is connect with control unit 2,
The control of unit 2 is controlled, therefore, control unit 2 is the relationship that connects one to one with memory block 1.It should be pointed out that this
Include but not limited to above-mentioned connection mode in embodiment, can also be to correspond to multiple memory blocks 1 by a control unit 2 to carry out
Control or multiple control units 2 correspond to a memory block 1, in protection domain.
Further, in above-mentioned refresh control circuit, state storage circuitry 22 includes rest-set flip-flop.
Rest-set flip-flop, structure are input, the output terminal interconnection two NAND gates or nor gate, input terminal R with
The output terminal connection of logic circuit 21, input terminal S is for the memory bearing signal such as Active signals of reception input, output terminal
It is connect with the input terminal of logic circuit 21, another input terminal of logic circuit 21 is used to receive Refresh signals, logic circuit 21
Output terminal connect with memory block 1.
The embodiment of the present invention additionally provides a kind of semiconductor memory, as shown in figure 3, including brush described in any one of the above embodiments
New control circuit.
The refreshing for including the storage unit 3 of storage data in semiconductor memory and being connect with the storage unit 3
Control circuit contains the memory block 1 being connect with the control unit 2 in refresh control circuit in storage unit 3, to memory block 1
Refresh process be to occur inside semiconductor memory.
As shown in figure 4, refresh control circuit is to the refresh control flow of semiconductor memory：To semiconductor memory into
Row power on operation, the power-on reset signal of formation are transmitted to refresh control circuit, and refresh control circuit is according to power-on reset signal
Control unit is reset to and forbids Flushing status, while this memory block being correspondingly connected with control unit is also reset as forbidding refreshing
State prevents the refresh operation of outer this memory block of bound pair, when receiving in the other memory blocks of opening the instruction of certain a line or any
Other instructions do not influence refresh control circuit holding and forbid the state refreshed, when receiving refreshing instruction and address is located at
During this memory block, refresh control circuit performs the step of skipping refresh operation and returning, and reaches and forbids what this memory block was refreshed
Purpose；When receive open the instruction of a certain row address in this memory block when, refresh control circuit is by the current shape of this memory block
State is reset to the state for allowing to refresh, and when receiving refreshing instruction and address is located at this memory block, refresh control circuit performs
Refresh operation and the step of return, achievees the purpose that refresh this memory block.
The above description is merely a specific embodiment, but protection scope of the present invention is not limited thereto, any
Those familiar with the art in the technical scope disclosed by the present invention, can readily occur in its various change or replacement,
These should be covered by the protection scope of the present invention.Therefore, protection scope of the present invention should be with the guarantor of the claim
It protects subject to range.
Claims (5)
1. a kind of method for refreshing of semiconductor memory, which is characterized in that the semiconductor memory has at least one storage
Block, refresh control circuit include at least one control unit, and described control unit is connect with the memory block, described control unit
Including state storage circuitry and logic circuit, the method includes：
When semiconductor memory initializes, the state storage circuitry is according to the power-on reset signal that inputs during initialization by institute
The current state for stating each memory block is set as the state for preventing to refresh；
When the storage arbitrary row in the block is accessed, the state storage circuitry is in the block to the storage according to acquisition
The calling-on signal and power-on reset signal of the arbitrary row, output allow refresh signal；
The logic circuit does logic and operation to the permission refresh signal and the refresh operation signal of input, and output allows to brush
New operation signal, the memory block to be allowed to carry out refresh operation to itself according to the permission refresh operation signal；
When the storage arbitrary row in the block is not accessed, the state storage circuitry is believed according to the electrification reset
Number, output prevents refresh signal；
The logic circuit does logic and operation, output resistance to the refresh operation signal of the prevention refresh signal and input
Only refresh operation signal, the refresh operation signal according to input to be prevented to carry out refresh operation to the memory block.
2. the method for refreshing of semiconductor memory as described in claim 1, which is characterized in that the refresh operation includes automatic
Refresh operation or self refresh operation.
3. a kind of refresh control circuit, applied to the refreshing to semiconductor memory, the semiconductor memory has at least one
A memory block, which is characterized in that the refresh control circuit includes at least one control unit, and described control unit is deposited with described
Block connection is stored up, described control unit includes：
State storage circuitry, the state storage circuitry are used for when semiconductor memory is initialized according to power-on reset signal,
Output prevents refresh signal；And according to the calling-on signal of the acquisition arbitrary row in the block to the storage and described
Power-on reset signal, output allow refresh signal；
Logic circuit, for doing logic and operation to the prevention refresh signal and the refresh operation signal of input, output prevents
Refresh operation signal, the refresh operation signal according to input to be prevented to carry out refresh operation to the memory block；It is and right
Described that refresh signal and the refresh operation signal of input is allowed to do logic and operation, output allows refresh operation signal, with
The memory block is allowed to carry out refresh operation to itself according to the permission refresh operation signal.
4. refresh control circuit as claimed in claim 3, which is characterized in that described control unit and the memory block one are a pair of
It should connect.
5. a kind of semiconductor memory, which is characterized in that including the refresh control circuit described in claim 3.
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| CN201710725168.2A CN107481752B (en) | 2017-08-22 | 2017-08-22 | Method for refreshing, refresh control circuit and the semiconductor memory of semiconductor memory |
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| CN201710725168.2A CN107481752B (en) | 2017-08-22 | 2017-08-22 | Method for refreshing, refresh control circuit and the semiconductor memory of semiconductor memory |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6240032B1 (en) * | 1997-11-27 | 2001-05-29 | Sharp Kabushiki Kaisha | Non-volatile semiconductor memory allowing user to enter various refresh commands |
| CN106601284A (en) * | 2015-10-16 | 2017-04-26 | 爱思开海力士有限公司 | Memory device and system including the same |
-
2017
- 2017-08-22 CN CN201710725168.2A patent/CN107481752B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6240032B1 (en) * | 1997-11-27 | 2001-05-29 | Sharp Kabushiki Kaisha | Non-volatile semiconductor memory allowing user to enter various refresh commands |
| CN106601284A (en) * | 2015-10-16 | 2017-04-26 | 爱思开海力士有限公司 | Memory device and system including the same |
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Effective date of registration: 20180928 Address after: 230000 room 630, Hai Heng mansion 6, Cui Wei Road, Hefei economic and Technological Development Zone, Anhui Patentee after: Changxin Storage Technology Co., Ltd. Address before: 230000 room 526, Hai Heng mansion 6, Cui Wei Road, Hefei economic and Technological Development Zone, Anhui Patentee before: Ever power integrated circuit Co Ltd |