CN107479831A - A kind of OCT volume data method for carrying based on Zynq platforms - Google Patents
A kind of OCT volume data method for carrying based on Zynq platforms Download PDFInfo
- Publication number
- CN107479831A CN107479831A CN201710683556.9A CN201710683556A CN107479831A CN 107479831 A CN107479831 A CN 107479831A CN 201710683556 A CN201710683556 A CN 201710683556A CN 107479831 A CN107479831 A CN 107479831A
- Authority
- CN
- China
- Prior art keywords
- data
- ddr
- zynq
- linux
- oct volume
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
- G06F3/0647—Migration mechanisms
Abstract
A kind of OCT volume data method for carrying based on Zynq platforms, comprises the following steps：For step 1) in Zynq platforms PL parts using programmable logic cells structure data transmission channel, the OCT volume datas for outside transmission to be come in are passed to DDR；Step 2) changes U boot and device tree source code in Zynq platforms PS parts transplanting (SuSE) Linux OS, and it is 400MB to make PS ends DDR；Step 3) is completed to access PL end datas and carry at PS ends using internal memory mapping mechanism and linux system calling interface.The present invention provides a kind of OCT volume data method for carrying being realized on Zynq platforms, can running operating system.
Description
Technical field
The present invention relates to a kind of application technology of Zynq platforms, and in particular to Zynq platform PS (Processing
System, processing system) with PL (Programmable Logic, FPGA) OCT volume data method for carrying.
Background technology
Zynq platforms are first expansible processing platforms of industry that Xilinx companies release, and are a by ARM
Cortex-A9 processors be closely integrated with low-power consumption FPGA together with full programmable system on chip (All
Programmable SoC), it can compile the software programmable ability of processor and powerful control ability and FPGA hardware
Cheng Nengli perfect adaptations, can realize the function of expansible, customizable optimization system, and its application relates generally to video monitoring, vapour
Car driver assistance and industrial automation etc. need high speed processing with calculating the high-end built-in field of performance.
Zynq platforms are made up of PS and PL two parts, and PS parts are integrated with interior using ARM Cortex-A9 processors as core
Memory controller and substantial amounts of peripheral hardware, there is provided comprehensive operating system is supported.PL is based partially on the Series FPGA frameworks of Xilinx 7,
Using 28nm technologies, have the characteristics that low-power consumption, miniaturization, signal handling capacity are powerful, there is provided the programmable money of common hardware
Source, available for subsystem is extended, there is abundant extended capability.Zynq is by ARM Cortex-A9 processors and the systems of Xilinx 7
The design methods that are combined of system FPGA bring increasing substantially in performance, therefore to receive people more and more for Zynq platforms
Concern, its application it is also more and more wider.
OCT (Optical Coherence Tomography, means of optical coherence tomography) be develop in recent years compared with
A kind of fast new Tomography technology, has extensive prospect in biological tissue's In vivo detection and imaging side face.OCT technology utilizes
Near infrared ray and principle of optical interference are imaged to biological tissue, it is possible to achieve to the high-resolution non-intruding layer of biological tissue
Analysis measurement, available for information such as collection human body skin corium pore, fingerprints, at present, OCT technology is in fields such as medical science, industry
Obtain more and more extensive application.And OCT image has high requirement to real-time, therefore to carry out phase using OCT technology
The processor support that development then must have superior performance is closed, traditional single processor such as ARM, DSP or FPGA are difficult to
Meet needs.The Zynq platforms that Xilinx companies release may be programmed due to being integrated with ARM Cortex-A9 processors with low-power consumption
Logic, there is higher performance compared to other uniprocessor platforms, can meet the needs of OCT related applications completely, therefore Zynq is put down
Platform is combined with OCT technology and had great application prospect.
The related development work of OCT technology is carried out in Zynq platforms, to be inevitably related to PS and PL data interactions
The problem of, the method for existing PS and PL data interactions is mostly interacted and realized with PL based on PS ends bare machine ARM, and if not
Operating system is run on ARM, it may be difficult to the powerful control of ARM chips and transaction capabilities are played, so as to be unable to maximum journey
Degree plays the superior function of Zynq platforms.
The content of the invention
In order to overcome prior art can not play the superiority of Cortex-A9 and two kinds of platforms of FPGA simultaneously not
Foot, the present invention propose one kind and are based on Zynq-7000 platforms, while play Cortex-A9 and two kinds of platforms of FPGA
The method that the OCT volume datas by PL to PS of superiority are carried.
The technical solution adopted for the present invention to solve the technical problems is：
A kind of OCT volume data method for carrying based on Zynq platforms, comprises the following steps：
1) PL ends using FIFO (First Input First Output, first in first out) memory, DMA IP kernels with
And the logic unit such as AXI_HP interfaces builds FPGA hardware environment, for the OCT volume datas of collection is incoming shared interior through PL
Deposit；
2) (SuSE) Linux OS is transplanted in PS ends arm processor, DDR is arranged to shared drive in linux system；
3) PL end datas are transferred to PL one end of shared drive using double buffering method by PL ends, and PS ends are mapped using internal memory
Mechanism carries PL end datas and transfers data to host computer to PS ends DDR, and using ICP/IP protocol, completes PL in this way
The data between PS are held to carry.
Further, in the step 1), logic unit includes FIFO memory, DMA IP kernels, AXI (Advanced
EXtensible Interface, level expansion interface) interconnecting interface, AXI_HP0 and AXI_HP1 interfaces, this part design tool
Body includes procedure below：
Taken at zynq platform PL ends using logic units such as FIFO memory, IP kernel DMA, AXI_HP0, AXI_HP1 interfaces
Build data and signal transmission passage, data and signal write from FIFO, after through module transfers such as DMA, AXI_HP to sharing
DDR。
Further, the processing procedure of the step 2) is as follows：
Linux system is transplanted to ARM：BOOT.bin is made, generates device tree, transplants linux kernel, makes Ramdisk
File system.Wherein BOOT.bin includes first stage startup code, and bit stream file and second stage start code.Make
, will in addition, it is necessary to which change device tree source code in source code is arranged to 400MB by DDR spaces when BOOT.bin is with generating device tree
Remaining space gives PL and is used as buffering area, so as to realize memory sharing.
Further, the processing procedure of the step 3) is as follows：
Step A：Two buffering areas 1 and 2 are applied at PL ends in DDR, and two buffer sizes are consistent, and apply for one piece of 1KB
Internal memory is used as signal position, and PL utilizes two buffer states of signal bit identification, represents that buffering area 1 counts if signal place value is 0x01
According to filling up；Represent that the data of buffering area 2 are filled up if signal place value is 0x02.
Step B：PS ends linux system utilizes EMS memory mappings method by the buffering area 1 in the DDR of PL ends, buffering area 2 and signal
Position internal memory is respectively mapped to consumer process space, and such PS ends can access PL end memories.After mapping successfully, under linux
By the state of application program detection signal place value, so that it is determined which block buffer data has been filled up, removed with this determination data
Transport object.
Step C：After mapping successfully, Linux application programs determine which block buffer entered according to signal position state of value
Data are carried, called using write systems wherein data to be write in socket afterwards, be then transferred to using ICP/IP protocol
Host computer is stored and handled.
When Linux application programs carry data, called using write () system and copy PL ends buffer data to
Socket sockets, before this host computer first run TCP server program, should using ICP/IP protocol and slave computer Linux
Established and connected with program, host computer procedure receives the data that slave computer is sent afterwards, completes OCT volume datas from PL through PS ends
Handling process of the linux kernel to host computer.
Beneficial effects of the present invention：
1) Zynq-7000 that the present invention uses is that global first patrols high-performance ARM Cortex-A9 stones with programmable
The chip integrated is collected, OCT data is gathered using FPGA, (SuSE) Linux OS and processing data are run using ARM, can
Cortex-A9 and two kinds of platforms of FPGA superiority are played simultaneously, make whole system being optimal of performance.
2) present invention runs (SuSE) Linux OS in PS, and the OCT bodies to collection are realized using the method for DDR double bufferings
High speed of the data between PL and PS is carried, and functional, and the data interactive method of more existing pure bare machine can more play Zynq
The superior function of platform, there is certain application value.
Brief description of the drawings
Fig. 1 OCT data transmission and the overall structure figure carried between Zynq platforms PS and PL；
Fig. 2 is that PL ends are passed to DDR volume data structural representations；
Fig. 3 is the specific implementation schematic diagram that PS and PL carries out OCT data carrying using Double buffer method；
Fig. 4 is the specific implementation schematic diagram that PS ends were conducted interviews and carried OCT data using internal memory mapping mechanism to PL.
Embodiment
The invention will be further described below in conjunction with the accompanying drawings.
1~Fig. 4 of reference picture, a kind of OCT volume data method for carrying based on Zynq platforms, Zynq platforms include FPGA and
Arm processor, comprise the following steps：
1) OCT volume data transmission channels are built using Xilinx developing instruments vivado
As shown in figure 1, OCT volume data transmission channels are built including programmable logic cells and processing system two parts,
The programmable logic cells include FIFO memory, DMA IP kernels, AXI interconnection architectures and AXI_HP0, AXI_HP1 passage.
The processing system is the ZYNQ7 processor systems comprising ARM Cortex-A9, and processing system operation Linux is grasped
Make system, the carrying of OCT volume datas is carried out by DDR and PL；
The FIFO is the synchronization fifo of AXI stream interfaces, and data-bus width is 16, and less than 16 polishings are 16；
The DMA is the soft core for direct memory access that Xilinx is provided, and need not can located using the soft core
Moving into or taking out of for internal storage data is completed in the case of reason device intervention；
The AXI interconnection architectures are IP kernel for main equipment and slave unit data transfer, and its agreement is AXI protocol, AXI
Agreement essentially describes the data transfer mode between main equipment and slave unit, and agreement has following features：Address/control of bus
System and data channel are separable；Support the data transfer mode not lined up；Simultaneously in burst transfer, it is only necessary to first ground
Location；There is separation read/write data passage simultaneously.AXI protocol provides the systems interconnection passage of high speed, it is ensured that PL with
The speed and quality of PS communications；
AXI-HP0 the and AXI_HP1 interfaces are the high bandwidth interface that PL is connected to DDR, and its data throughput highest can
Up to 1200MB/s.
The OCT volume datas are as shown in Fig. 2 OCT volume datas scan human body hand for the linear array CCD camera based on OCT technology
Refer to gained, scan depths 2mm, volume data contains the light intensity letter of the tissues such as finger epidermis fingerprint, skin corium fingerprint, sweat gland
Breath, handles and is imaged to it using visualization technology.As shown in Fig. 2 Y direction is camera scanning once gained picture number
According to comprising 2048 pixels, every pixel size is 16；Z-direction is a two field picture number of 500 gained of camera transversal scanning
According to size is 500 × 2048 × 16bit；X-direction is the individual data items that camera continuously scans 300 gained, and size is
300 × 500 × 2048 × 16bit, i.e. 585MB.
2) (SuSE) Linux OS is transplanted at PS ends
Transplanting (SuSE) Linux OS comprises the following steps：BOOT.bin is made, generates device tree, makes linux kernel,
Make Ramdisk file system.Wherein BOOT.bin includes first stage startup code, and bit stream file and second stage start
Code.First stage, which starts code and bit stream, to be needed to complete by Xilinx developing instruments vivado and SDK, and the first stage opens
The initialization to PS ends is mainly completed in dynamic code, loading second stage starts the work such as code；Bit stream file is completed to PL
The initialization at end, including the data transmission channel built；Second stage starts code main function as initialization CPU, and will
Operating system is loaded into internal memory.In order to realize that PS and PL shares DDR mechanism, when making BOOT.bin with generation device tree,
Need to change device tree source code in source code and DDR spaces are arranged to 400MB, other remaining space is given into PL is used as buffering
Area, so as to realize memory sharing.Concrete modification method is as follows：
Equipment is changed in the case where BOOT.bin second stage starts code source code arch/arm/dts/zynq-zed.dts paths
Set source code, the memory headroom size that will be set in source code：
Reg=<0x00000000 0x40000000>
It is changed to 400MB:
Reg=<0x00000000 0x19000000>
Device tree source code is changed under the kernel source code arch/arm/dts/zynq-zed.dts paths of generation device tree,
The memory headroom set in source code is revised as 400MB, amending method is same as above.
DDR just divide into two parts by the modification of two steps more than, and a part is used for PS ends operation operating system, another
Part is used as data buffer zone for PL ends.
3) shared drive method and double buffers realize PS and PL data interactions
As shown in accompanying drawing 1 and 3, PL applies for two buffering areas 1 and 2, two buffer sizes by application program in DDR
It is equal, it is all 300MB, and apply for that one piece of 1KB internal memory is used as signal position.When PL transmits OCT volume datas to DDR, first by 300MB
Data transfer to buffering area 1, the data of buffering area 1 fill up after by signal via DMA signals transfer module and AXI interconnection architectures,
AXI_HP1 interface write signals position, signal value 0x01, PS ends are waited to carry data in buffering area 1 afterwards, while PL will in addition
285MB volume datas are transferred to buffering area 2, and signal place value is set to 0x02 by the data of area 2 to be buffered with same method again after filling up,
PS ends are waited to carry.
PS ends linux system application program by the buffering area 1 in the DDR of PL ends, buffering area 2 and is believed using EMS memory mappings method
Number position internal memory is respectively mapped to consumer process space, and records virtual address of each memory field in user's space, such PS ends
The access to PL end memories can be completed by the access to virtual address.After mapping successfully, under linux by using journey
The change of the continuous poll PL end signal bit values of sequence, 300MB therein is carried into buffering area 1 if signal place value is 0x01
OCT volume datas, other 285MB volume datas are carried into buffering area 2 if signal place value is 0x02, are completed in this way to PL
Hold the carrying of OCT volume datas.
4) OCT volume datas are carried to host computer using internal memory mapping mechanism and ICP/IP protocol
This certain applications program divides two parts, first, operating in the client-side program of slave computer, act as carrying PL end DDR
In OCT volume datas to socket sockets；First, operating in the server program under host computer linux system, it act as connecing
The data that slave computer is sent are received, both need to establish first with ICP/IP protocol before being communicated and connect.
As shown in Figure 4, when Linux application programs access PL end DDR, first with system mmap () can be called to carry out internal memory
Mapping, after mapping successfully, linux system can access PL end memories.System application is become by continuous detection signal position
The method of change judges the state of PL ends two buffering areas of DDR, if detecting, signal place value is just removed for 1 or 2 into corresponding buffering area
Transport OCT volume datas therein.
Application program is using under system calling write () carrying PL end buffering area OCT volume datas to Linux after mapping
Can be first by data copy to linux kernel buffering area, now user space application meeting in socket sockets, during this
This buffering area is shared with operating system, such system kernel and user's space avoid the need for carrying out any data copy behaviour
Make, method efficiency of this method compared to mmap ()+memcpy () can be increased substantially.
Data copy can then copy socket buffering areas to, afterwards from socket buffering areas to after kernel buffers
Copy protocol engine to, data finally are uploaded into host computer by gigabit network cable again is stored and handled.Walked more than
The rapid carrying work for just completing the OCT volume datas between the PS and PL of operation (SuSE) Linux OS.
Claims (4)
- A kind of 1. OCT volume data method for carrying based on Zynq platforms, it is characterised in that the Zynq platforms include FPGA and Arm processor, comprise the following steps：Step 1) Zynq platforms PL part using programmable logic cells structure data transmission channel, for by outside transmit into The OCT volume datas come are passed to DDR；Step 2) changes U-boot and device tree source code in Zynq platforms PS parts transplanting (SuSE) Linux OS, makes PS ends DDR is 400MB；Step 3) is completed to access PL end datas and carry at PS ends using internal memory mapping mechanism and linux system calling interface.
- A kind of 2. OCT volume data method for carrying based on Zynq platforms according to claim 1, it is characterised in that：It is described In step 1), the programmable logic cells include FIFO memory, DMA IP kernels, AXI interconnection architectures, AXI_HP0 and AXI_ HP1 interfaces, wherein data fifo bus are 16, and less than 16 polishings are 16 transmission.
- A kind of 3. OCT volume data method for carrying based on Zynq platforms according to claim 1 or 2, it is characterised in that：Institute The processing procedure for stating step 2) is：Transplant Linux4.4 kernels, make Ramdisk file system；U-boot and device tree source code are changed, by what is be provided with DDR memory sizes are set to 400MB, make DDR low address part be used for running operating system and processing control program, high address part Give PL be used for it is data cached, PS and PL shared drive purposes are realized with this.
- A kind of 4. OCT volume data method for carrying based on Zynq platforms according to claim 1 or 2, it is characterised in that：Institute The processing procedure for stating step 3) is：Step A：Two buffering areas 1 and 2 are applied at PL ends in DDR, and two buffer sizes are consistent, and apply for one piece of 1KB internal memory As signal position, PL utilizes two buffer states of signal bit identification, represents that the data of buffering area 1 are filled out if signal place value is 0x01 It is full；Represent that the data of buffering area 2 are filled up if signal place value is 0x02.Step B：PS ends linux system is using EMS memory mappings method by the buffering area 1 in the DDR of PL ends, buffering area 2 and signal position Deposit and be respectively mapped to consumer process space, such PS ends can access PL end memories.After mapping successfully, pass through under linux The state of application program detection signal place value, so that it is determined which block buffer data has been filled up, with the carrying pair of this determination data As.Step C：After mapping successfully, Linux application programs determine to enter which block buffer is carried according to signal position state of value Data, called using write systems wherein data to be write in socket afterwards, be then transferred to using ICP/IP protocol upper Machine is stored and handled.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710683556.9A CN107479831A (en) | 2017-08-11 | 2017-08-11 | A kind of OCT volume data method for carrying based on Zynq platforms |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710683556.9A CN107479831A (en) | 2017-08-11 | 2017-08-11 | A kind of OCT volume data method for carrying based on Zynq platforms |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107479831A true CN107479831A (en) | 2017-12-15 |
Family
ID=60600191
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710683556.9A Pending CN107479831A (en) | 2017-08-11 | 2017-08-11 | A kind of OCT volume data method for carrying based on Zynq platforms |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107479831A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109377549A (en) * | 2018-09-29 | 2019-02-22 | 浙江工业大学 | A kind of real-time processing of OCT finger tip data and three-dimensional visualization method |
| CN109491949A (en) * | 2018-11-27 | 2019-03-19 | 哈尔滨工业大学 | Dynamic reconfigurable frame and method based on Zynq |
| CN110069440A (en) * | 2019-03-11 | 2019-07-30 | 胡友彬 | Meteorological ocean data Processing Algorithm Hardware system and method based on heterogeneous polynuclear |
| CN110244304A (en) * | 2019-04-15 | 2019-09-17 | 浙江工业大学 | A kind of side scan sonar signal processing method based on ZYNQ |
| CN110336928A (en) * | 2019-03-15 | 2019-10-15 | 浙江工业大学 | A kind of OCT spectroscopic acquisition and Transmission system based on ZYNQ |
| CN112104866A (en) * | 2020-08-05 | 2020-12-18 | 成都卓元科技有限公司 | 8K video transmission mode |
| CN113176850A (en) * | 2021-03-12 | 2021-07-27 | 湖南艾科诺维科技有限公司 | Shared storage disk based on SRIO interface and access method thereof |
| WO2021217436A1 (en) * | 2020-04-28 | 2021-11-04 | 深圳市大疆创新科技有限公司 | Infrared data processing method, chip, terminal and system |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20130318275A1 (en) * | 2012-05-22 | 2013-11-28 | Xockets IP, LLC | Offloading of computation for rack level servers and corresponding methods and systems |
| CN103927276A (en) * | 2014-03-14 | 2014-07-16 | 山东大学 | PCM FMC expansion board based on Zynq-7000 and working method of PCM FMC expansion board |
| CN103984586A (en) * | 2014-06-10 | 2014-08-13 | 哈尔滨工业大学 | Interface drive method for EMIF (external memory interface) and FPGA (field programmable gate array) under embedded type Linux system |
| CN106339258A (en) * | 2016-08-10 | 2017-01-18 | 西安诺瓦电子科技有限公司 | Management method and device for shared memory of programmable logic device and microprocessor |
-
2017
- 2017-08-11 CN CN201710683556.9A patent/CN107479831A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20130318275A1 (en) * | 2012-05-22 | 2013-11-28 | Xockets IP, LLC | Offloading of computation for rack level servers and corresponding methods and systems |
| CN103927276A (en) * | 2014-03-14 | 2014-07-16 | 山东大学 | PCM FMC expansion board based on Zynq-7000 and working method of PCM FMC expansion board |
| CN103984586A (en) * | 2014-06-10 | 2014-08-13 | 哈尔滨工业大学 | Interface drive method for EMIF (external memory interface) and FPGA (field programmable gate array) under embedded type Linux system |
| CN106339258A (en) * | 2016-08-10 | 2017-01-18 | 西安诺瓦电子科技有限公司 | Management method and device for shared memory of programmable logic device and microprocessor |
Non-Patent Citations (1)
| Title |
|---|
| 汪本章: "面向XiLinx Zynq-7000的基于暗原色先验理论视频去雾系统实时实现", 《中国优秀硕士学位论文全文数据库 信息科技辑》 * |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109377549A (en) * | 2018-09-29 | 2019-02-22 | 浙江工业大学 | A kind of real-time processing of OCT finger tip data and three-dimensional visualization method |
| CN109491949A (en) * | 2018-11-27 | 2019-03-19 | 哈尔滨工业大学 | Dynamic reconfigurable frame and method based on Zynq |
| CN110069440A (en) * | 2019-03-11 | 2019-07-30 | 胡友彬 | Meteorological ocean data Processing Algorithm Hardware system and method based on heterogeneous polynuclear |
| CN110336928A (en) * | 2019-03-15 | 2019-10-15 | 浙江工业大学 | A kind of OCT spectroscopic acquisition and Transmission system based on ZYNQ |
| CN110244304A (en) * | 2019-04-15 | 2019-09-17 | 浙江工业大学 | A kind of side scan sonar signal processing method based on ZYNQ |
| WO2021217436A1 (en) * | 2020-04-28 | 2021-11-04 | 深圳市大疆创新科技有限公司 | Infrared data processing method, chip, terminal and system |
| CN112104866A (en) * | 2020-08-05 | 2020-12-18 | 成都卓元科技有限公司 | 8K video transmission mode |
| CN113176850A (en) * | 2021-03-12 | 2021-07-27 | 湖南艾科诺维科技有限公司 | Shared storage disk based on SRIO interface and access method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107479831A (en) | A kind of OCT volume data method for carrying based on Zynq platforms | |
| CN108268942B (en) | Configurable accelerator framework | |
| CN109714586B (en) | ZYNQ-based real-time binocular stereoscopic vision software and hardware collaborative design method | |
| JP2021526253A (en) | Deep learning system | |
| TW202004656A (en) | Compute optimization mechanism | |
| US10055807B2 (en) | Hardware architecture for acceleration of computer vision and imaging processing | |
| JP7053713B2 (en) | Low power computer imaging | |
| CN108566357B (en) | Image transmission and control system and method based on ZYNQ-7000 and FreeRTOS | |
| US11768601B2 (en) | System and method for accelerated data processing in SSDS | |
| CN1267826C (en) | On-chip system processor for multimedia | |
| US11194722B2 (en) | Apparatus and method for improved cache utilization and efficiency on a many core processor | |
| EP2472468A1 (en) | Image processing device and image processing method | |
| TW200847060A (en) | Indexes of graphics processing objects in graphics processing unit commands | |
| CN205486304U (en) | Portable realtime graphic object detection of low -power consumption and tracking means | |
| EP3117774A1 (en) | Software-based ultrasound imaging system | |
| EP3806100A1 (en) | Method and device for four-dimensional visualization of medical image | |
| CN103780819B (en) | Intelligent industrial camera | |
| US9508109B2 (en) | Graphics processing | |
| CN115202922A (en) | Packed Error Correction Code (ECC) for compressed data protection | |
| CN102103737A (en) | Image processing system, image processing apparatus, image pickup apparatus and method | |
| CN101567078A (en) | Dual-bus visual processing chip architecture | |
| CN107493419A (en) | A kind of integral miniaturized high-speed realtime graphic acquisition device | |
| CN116429259A (en) | Spectral processing system of fiber bragg grating | |
| Hussain et al. | Pgc: a pattern-based graphics controller | |
| CN109491949A (en) | Dynamic reconfigurable frame and method based on Zynq |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20171215 |