CN107452415B - DQS signal delay control method, circuit and semiconductor memory - Google Patents
DQS signal delay control method, circuit and semiconductor memory Download PDFInfo
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- CN107452415B CN107452415B CN201710851839.XA CN201710851839A CN107452415B CN 107452415 B CN107452415 B CN 107452415B CN 201710851839 A CN201710851839 A CN 201710851839A CN 107452415 B CN107452415 B CN 107452415B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/04—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
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Abstract
The present invention provides a kind of DQS signal delay control circuits, including DQS input circuits, DQ input circuits and transmission line, the input terminal of transmission line is connect with DQS input circuits, the output end of transmission line is connect with DQ input circuits, transmission line includes at least one internal circuit, and when internal circuit is multiple, multiple internal circuits are sequentially connected in the transmission direction of DQS input circuits to DQ input circuits；At least one of internal circuit accesses regulated power supply；Delay control circuit further includes controller, controller is connect with regulated power supply, for detecting the Parameters variation in delay control circuit, and according to Parameters variation and preset stable operating voltage generation strategy, generate stable operating voltage output corresponding with Parameters variation, stable operating voltage output effectively reduces delay time by parametric variations such as internal operating voltages or temperature for being supplied to internal circuit.The present invention also provides a kind of semiconductor memories and DQS signal delay control method.
Description
Technical field
The present invention relates to dynamic RAM technical field, more particularly to a kind of DQS signal delay control circuit also relates to
And the semiconductor memory comprising DQS signal delay control circuit and a kind of DQS signal delay control method.
Background technology
DQS (Data Strobe Signal, data strobe signal) effects are in Double Data Rate dynamic RAM
The critical function that should have in (DDR DRAM, Double Data Rate Dynamic Random Access Memory), it is main
To be used for accurately distinguishing each transmission cycle within a clock cycle, and data are accurately received convenient for recipient.DQS believes
Number it is the synchronizing signal of data, as shown in Figure 1, when data are written, DQS signal is sent to semiconductor storage by main control chip 10
Device 40 is dram chip, makees data synchronization by DQS signal.
In semiconductor memory such as low-power consumption RAM chip (LPDDR4, Low Power Double Data Rate
SDRAM in), in ablation process, DQS signal is with data-signal DQ by the transmission path of approximately the same length with approximately uniform
Speed is sent in LPDDR4, and in LPDDR4, DQS input circuits 30 pass the DQS signal received by a transmission path
It send to DQ input circuits 20, DQ input circuits 20 capture data according to the rising edge of DQS signal and failing edge, and by data
It stores into memory 21, for example, the control DQS of main control chip 10 (0) becomes DQS (1) or DQS (1) and becomes DQS (0), DQS
Signal often changes once, and DQ input circuits 20 are primary according to above-mentioned variation crawl data, and data are stored.
Since the time that DQS signal and DQ signals reach used in LPDDR4 is approximately the same, inside LPDDR4, DQS signal
It also needs to just be sent to DQ input circuits 20 for a period of time, the transmission time difference of DQS and DQ result in DQS signal and DQ signals
It is asynchronous.In order to avoid the above situation, it is common practice to, DQS signal is carried previous time t by main control chip 10DQS2DQIt sends
Into LPDDR4 so that DQS signal can synchronously arrive at DQ input circuits 20 with DQ signals, to improve the crawl of DQ input circuits 20
The accuracy rate of data.
However, delay time tDQS2DQIt is easy to be influenced by factors such as the internal operating voltages of LPDDR4 or operating temperatures, lead
The main control chip 10 of induced semiconductor memory needs the change by constantly detecting the parameters such as internal operating voltages or operating temperature
Change to adjust delay time tDQS2DQ, main control chip 10 is to the parameters change such as the internal operating voltages variation of LPDDR4 or operating temperature
The detection time consumption and energy consumption of change, it is slack-off to eventually lead to writing speed, and by detect semiconductor memory internal operating voltages or
Operating temperature adjusts delay time tDQS2DQMethod can not effectively improve DQ input circuits 20 capture data accuracy rate, because
For delay time tDQS2DQThe accuracy of adjustment is not high.
Therefore, how to reduce delay time tDQS2DQIt is influenced by Parameters variations such as internal operating voltages or operating temperatures, from
And obtain stable delay time tDQS2DQIt is that those skilled in the art are badly in need of technical problems to be solved.
Disclosed above- mentioned information is only used for reinforcing the understanding of the background to the present invention in the background technology, therefore it may be wrapped
Containing the information for not being formed as the prior art that those of ordinary skill in the art are known.
Invention content
In view of this, the embodiment of the present invention is desirable to provide a kind of DQS signal delay control method, circuit and semiconductor storage
Device, at least to solve the technical problems existing in the prior art.
The technical solution of the embodiment of the present invention is achieved in that according to one embodiment of present invention, provides a kind of DQS
Signal delay control circuit, be applied to semiconductor memory, the control circuit include DQS input circuits, DQ input circuits and
Transmission line, the input terminal of the transmission line are connect with the DQS input circuits, and output end connects with the DQ input circuits
It connects, the transmission line includes at least one internal circuit, and when the internal circuit is multiple, multiple internal circuits
It is sequentially connected in the transmission direction of the DQS input circuits to the DQ input circuits；
Wherein, at least one of described internal circuit accesses regulated power supply, and the regulated power supply is used for the institute of access
It states internal circuit and stable operating voltage is provided；
The delay control circuit further includes controller, and the controller is connect with the regulated power supply, the controller
For detecting the Parameters variation in the delay control circuit, and according to the Parameters variation and preset stable operating voltage
Generation strategy, generates stable operating voltage output corresponding with the Parameters variation, and the stable operating voltage of output is used for
It is supplied to the internal circuit.
Preferably, in above-mentioned DQS signal delay control circuit, the Parameters variation in the delay control circuit is described
Temperature change in delay control circuit, the preset stable operating voltage generation strategy are the institute in preset temperature range
Temperature is stated to be positively correlated with the stable operating voltage.
Preferably, in above-mentioned DQS signal delay control circuit, the Parameters variation in the delay control circuit is described
The voltage change of the internal circuit of the regulated power supply, the preset stable operating voltage life are not accessed in delay control circuit
The voltage of internal circuit at strategy not access the regulated power supply is negatively correlated with the stable operating voltage.
Preferably, in above-mentioned DQS signal delay control circuit, the stable operating voltage is V by operating voltagedd1's
The charge pump that internal work power supply or external power supply provide provides.
Preferably, in above-mentioned DQS signal delay control circuit, the stable operating voltage is more than internal work electricity
The voltage V that source providesdd2Or Vddq。
Preferably, in above-mentioned DQS signal delay control circuit, the DQS input circuits and the DQ input circuits
It is V that access, which provides operating voltage,ddqThe internal work power supply.
Preferably, in above-mentioned DQS signal delay control circuit, the internal circuit includes buffer register.
The embodiment of the present invention additionally provides a kind of semiconductor memory, including the DQS signal described in the embodiment of the present invention prolongs
When control circuit.
The embodiment of the present invention additionally provides a kind of DQS signal delay control method, the DQS being applied in semiconductor memory
Signal delay control circuit, in the DQS signal delay control circuit, the biography between DQS input circuits and DQ input circuits
At least one of defeated circuit internal circuit accesses the regulated power supply of semiconductor memory, wherein is deposited when in the transmission line
In multiple internal circuits, multiple internal circuits are suitable in the transmission direction of DQS input circuits to the DQ input circuits
Secondary connection；The control method includes：
The Parameters variation in DQS signal delay control circuit in the semiconductor memory is detected, and according to the parameter
Variation and preset stable operating voltage generation strategy generate stable operating voltage output corresponding with the Parameters variation；
The stable operating voltage output of output is supplied to the internal circuit, so that the DQS signal is described
The variation of delay time in transmission line tends to a stationary value.
Preferably, it in above-mentioned DQS signal delay control method, generates the step of stable operating voltage exports and wraps
It includes：
When detecting the temperature change in the delay control circuit, the preset stable operating voltage generation strategy be
In preset temperature range, the temperature is positively correlated with the stable operating voltage；
According to the temperature change and with the positively related generation strategy of the stable operating voltage, generate corresponding described
Stable operating voltage exports.
Preferably, it in above-mentioned DQS signal delay control method, generates the step of stable operating voltage exports and wraps
It includes：
When detecting the voltage change for the internal circuit for not accessing the regulated power supply in the delay control circuit, institute
State voltage that preset stable operating voltage generation strategy is the internal circuit for not accessing the regulated power supply with it is described steady
Fixed working voltage is negatively correlated；
According to the voltage change for the internal circuit for not accessing the regulated power supply in the delay control circuit and
With the generation strategy of stable operating voltage negative correlation, the corresponding stable operating voltage output is generated.
The embodiment of the present invention due to using the technology described above, has the following advantages：Due to input terminal and DQS input electricity
Road connects, in the transmission line that output end is connect with DQ input circuits, the access of at least one of internal circuit connected in sequence
The regulated power supply of stable operating voltage is provided, compared with the existing technology in, by internal circuit connected in sequence all by partly leading
In body memory internal work power supply provide with the continually changing voltage V of the working environment of semiconductor memorydd2, replace
At the stable operating voltage provided by regulated power supply, to reduce the influence of internal work power supply transmission line delay time, and it is steady
The generation of fixed working voltage is by the Parameters variation in detection delay control circuit, and according to Parameters variation and preset stable work
Make voltage generation strategy, the controller for generating stable operating voltage output corresponding with Parameters variation is controlled, i.e., according to not
The voltage V of disconnected variationdd2It waits Parameters variations to generate stable operating voltage, delay time can be effectively reduced by internal operating voltages
Or the influence of the variation of the parameters such as operating temperature, to obtain stable delay time.
Above-mentioned general introduction is merely to illustrate that the purpose of book, it is not intended to be limited in any way.Except foregoing description
Schematical aspect, except embodiment and feature, by reference to attached drawing and the following detailed description, the present invention is further
Aspect, embodiment and feature, which will be, to be readily apparent that.
Description of the drawings
In the accompanying drawings, unless specified otherwise herein, otherwise run through the identical reference numeral of multiple attached drawings and indicate same or analogous
Component or element.What these attached drawings were not necessarily to scale.It should be understood that these attached drawings are depicted only according to the present invention
Some disclosed embodiments, and should not serve to limit the scope of the present invention.
Fig. 1 is that the DQS signal provided in the prior art is transmitted to the biography of semiconductor memory with DQ signals from main control chip
Defeated schematic diagram.
Fig. 2 is the DQS signal delay control circuit figure that the embodiment of the present invention one provides.
Fig. 3 be it is provided by Embodiment 2 of the present invention include DQS signal delay control circuit organization of semiconductor memory
Schematic diagram.
Fig. 4 is the DQS signal delay control method flow chart that the embodiment of the present invention three provides.
Drawing reference numeral explanation：
10 main control chips；20 DQ input circuits；21 memories；30 DQS input circuits；40 semiconductor memories；50
Transmission line；60 regulated power supplies；70 controllers.
Specific implementation mode
Hereinafter, certain exemplary embodiments are simply just described.As one skilled in the art will recognize that
Like that, without departing from the spirit or scope of the present invention, described embodiment can be changed by various different modes.
Therefore, attached drawing and description are considered essentially illustrative rather than restrictive.
In the description of the present invention, it is to be understood that, term "center", " longitudinal direction ", " transverse direction ", " length ", " width ",
" thickness ", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outside", " up time
The orientation or positional relationship of the instructions such as needle ", " counterclockwise ", " axial direction ", " radial direction ", " circumferential direction " be orientation based on ... shown in the drawings or
Position relationship is merely for convenience of description of the present invention and simplification of the description, and does not indicate or imply the indicated device or element must
There must be specific orientation, with specific azimuth configuration and operation, therefore be not considered as limiting the invention.
In addition, term " first ", " second " are used for description purposes only, it is not understood to indicate or imply relative importance
Or implicitly indicate the quantity of indicated technical characteristic.Define " first " as a result, the feature of " second " can be expressed or
Implicitly include one or more this feature.In the description of the present invention, the meaning of " plurality " is two or more,
Unless otherwise specifically defined.
In the present invention unless specifically defined or limited otherwise, term " installation ", " connected ", " connection ", " fixation " etc.
Term shall be understood in a broad sense, for example, it may be being fixedly connected, may be a detachable connection, or integral；Can be that machinery connects
It connects, can also be electrical connection, can also be communication；It can be directly connected, can also indirectly connected through an intermediary, it can be with
It is the interaction relationship of the connection or two elements inside two elements.For the ordinary skill in the art, may be used
To understand the concrete meaning of above-mentioned term in the present invention as the case may be.
In the present invention unless specifically defined or limited otherwise, fisrt feature the "upper" of second feature or "lower"
It may include that the first and second features are in direct contact, can also not be to be in direct contact but pass through it including the first and second features
Between other characterisation contact.Moreover, fisrt feature second feature " on ", " side " and " above " include fisrt feature
Right over second feature and oblique upper, or it is merely representative of fisrt feature level height and is higher than second feature.Fisrt feature is
Two features " under ", " lower section " and " following " include fisrt feature right over second feature and oblique upper, or be merely representative of
One characteristic level height is less than second feature.
Following disclosure provides many different embodiments or example is used for realizing the different structure of the present invention.In order to
Simplify disclosure of the invention, hereinafter the component of specific examples and setting are described.Certainly, they are merely examples, and
And it is not intended to limit the present invention.In addition, the present invention can in different examples repeat reference numerals and/or reference letter,
This repetition is for purposes of simplicity and clarity, itself not indicate between discussed various embodiments and/or setting
Relationship.In addition, the present invention provides various specific techniques and material example, but those of ordinary skill in the art can be with
Recognize the application of other techniques and/or the use of other materials.
Embodiment one
The DQS signal delay control circuit that the embodiment of the present invention one provides.DQS signal transmission circuit application shown in Fig. 2
In semiconductor memory 40, DQS input circuits 30, DQ input circuits 20 and transmission line 50 are included at least, transmission line 50
Input terminal is connect with DQS input circuits 30, and the output end of transmission line 50 is connect with DQ input circuits 20, and transmission line 50 includes
On from DQS input circuits 30 to 20 direction of DQ input circuits, multiple internal circuits connected in sequence include interior specific to Fig. 2
Portion's circuit 1, internal circuit 2, internal circuit 3 and internal circuit 4；Wherein, at least one of internal circuit accesses regulated power supply
60, regulated power supply 60 is used to provide stable operating voltage to the internal circuit of access；
Delay control circuit further includes controller 70, and controller 70 is connect with regulated power supply 60, and controller 70 is for detecting
Parameters variation in delay control circuit, and according to Parameters variation and preset stable operating voltage generation strategy, generate with
The corresponding stable operating voltage output of Parameters variation, stable operating voltage are exported for being supplied at least one internal circuit.
Specifically, due to DQS signal on transmission line 50 delay time by internal operating voltages Vdd2It influences, Vdd2Variation
Unstable result in the unstable of delay time on transmission line 50, certainly, DQS signal delay time on transmission line 50
It is also influenced by other factors such as temperature changes, unstable due to temperature change results in delay time on transmission line 50
It is unstable.Therefore, to solve the above-mentioned problems, in present embodiment, partial interior circuit such as internal circuit 3, internal circuit 4
It is powered by regulated power supply 60, it should be pointed out that the quantity of internal circuit of access regulated power supply 60 is not specifically limited, can be with
Regulated power supply 60 is accessed for any one or more internal circuits therein, as long as it is steady to meet the access of at least one internal circuit
Voltage source 60, in protection domain；DQS input circuits 30 and DQ input circuits 20 access semiconductor memory 40 and carry
For VddqInternal work power supply, internal circuit 1, internal circuit 2 are by internal work supplies voltages Vdd2。
In present embodiment, controller 70 detects the Parameters variation in the delay control circuit, Parameters variation therein
Include the temperature change generated during the work time inside semiconductor memory 40, and the work with semiconductor memory 40
The continually changing voltage change of environment, including：It is supplied to the voltage V of DQS input circuits 30 and DQ input circuits 20ddqChange
Change, and is supplied to the voltage V of internal circuit 1 and internal circuit 2dd2Variation.
Embodiment two
DQS signal delay control circuit provided by Embodiment 2 of the present invention.DQS signal transmission circuit application shown in Fig. 3
In semiconductor memory 40, DQS input circuits 30, DQ input circuits 20 and transmission line 50 are included at least, transmission line 50
Input terminal is connect with DQS input circuits 30, and the output end of transmission line 50 is connect with DQ input circuits 20, and transmission line 50 includes
On from DQS input circuits 30 to 20 direction of DQ input circuits, multiple internal circuits connected in sequence include interior specific to Fig. 2
Portion's circuit 1, internal circuit 2, internal circuit 3 and internal circuit 4；Wherein, at least one of internal circuit accesses regulated power supply
60, regulated power supply 60 is used to provide stable operating voltage to the internal circuit of access；
Delay control circuit further includes controller 70, and controller 70 is connect with regulated power supply 60, and controller 70 is for detecting
Parameters variation in delay control circuit, and according to Parameters variation and preset stable operating voltage generation strategy, generate with
The corresponding stable operating voltage output of Parameters variation, stable operating voltage are exported for being supplied at least one internal circuit.
Specifically, in present embodiment, internal circuit 1, internal circuit 2, internal circuit 3, internal circuit 4 are by regulated power supply
60 power supplies, DQS input circuits 30 and DQ input circuits 20 access semiconductor memory 40 and provide VddqInternal work power supply,
And to the voltage V that DQS input circuits 30 and DQ input circuits 20 applyddqIt is the working environment with semiconductor memory 40
Constantly variation；
Controller 70 is used to detect the Parameters variation in the delay control circuit, and Parameters variation therein includes partly to lead
The temperature change generated during the work time inside body memory 40, and constantly become with the working environment of semiconductor memory 40
Change the voltage change generated, including：It is supplied to the voltage V of DQS input circuits 30 and DQ input circuits 20ddqVariation.
In above-mentioned two embodiment, according to Parameters variation and preset stable operating voltage generation strategy generates and parameter
Change corresponding stable operating voltage output, stable operating voltage is exported to internal circuit, wherein preset steady operation electricity
Pressure generation strategy is that Parameters variation as described above is preset, such as, it is generally the case that temperature is higher, and DSQ is caused to believe
Transmission speed number in transmission line 50 is slack-off, therefore, in certain temperature range, as temperature increases, adjusts and stablizes work
Make voltage raising, obtains varying with temperature the delay time to tend towards stability；It is supplied to the voltage V of partial interior circuitdd2Or
VddqWhen increase, adjusts stable operating voltage and reduce, ensure that the total voltage of entire transmission line 50 tends towards stability, obtain with voltage
Change the delay time to tend towards stability.
In compared with the existing technology, by internal circuit connected in sequence all by internal work electricity in semiconductor memory 40
Source provide with the continually changing voltage V of the working environment of semiconductor memory 40dd2, it is substituted for and is provided by regulated power supply 60
Stable operating voltage, influenced by delay time with reducing internal work power supply transmission line 50, and stable operating voltage
It generates by the Parameters variation in detection delay control circuit, and plan is generated according to Parameters variation and preset stable operating voltage
Slightly, the controller 70 for generating stable operating voltage output corresponding with Parameters variation is controlled, i.e., according to continually changing electricity
Press Vdd2Or VddqIt waits Parameters variations to generate stable operating voltage, effectively reduces delay time by internal operating voltages or work
The influence of the variation of the parameters such as temperature, to obtain stable delay time.
On the basis of above-mentioned DQS signal delay control circuit, the Parameters variation in delay control circuit is delays time to control
Temperature change in circuit, preset stable operating voltage generation strategy are temperature and steady operation in preset temperature range
Voltage is positively correlated.
Wherein, it in certain temperature range, as temperature increases, adjusts stable operating voltage and increases, accelerate DSQ signals and exist
Transmission speed in transmission line 50 effectively reduces delay time and is acted upon by temperature changes, when to obtain stable delay
Between.
On the basis of above-mentioned DQS signal delay control circuit, the Parameters variation in delay control circuit is delays time to control
The voltage change of the internal circuit of the regulated power supply 60 is not accessed in circuit, preset stable operating voltage generation strategy is not
The voltage for accessing the internal circuit of regulated power supply 60 is negatively correlated with stable operating voltage.
Wherein, the voltage for not accessing the internal circuit of regulated power supply 60 includes：It is supplied to DQS input circuits 30 and DQ defeated
Enter the voltage V of circuit 20ddq, or it is supplied to the voltage V of partial interior circuitdd2, work as Vdd2Or VddqWhen constantly increasing, adjust
Stable operating voltage reduces, and ensures that 50 total voltage of transmission line tends towards stability, effectively reduces delay time by internal operating voltages
The influence of variation, to obtain stable delay time.
Further, in above-mentioned DQS signal delay control circuit, the stable operating voltage is V by operating voltagedd1
Internal work power supply or external power supply provide charge pump provide.
Further, in above-mentioned DQS signal delay control circuit, stable operating voltage is provided more than internal work power supply
Voltage Vdd2Or Vddq。
Wherein, it is V when stable operating voltage is by offer operating voltagedd1Internal work power supply or external power supply provide
Charge pump provide when, and/or output to internal circuit stable operating voltage be more than output to other internal circuits voltage
Vdd2Or VddqWhen, providing higher burning voltage to internal circuit so that the total voltage of overall transfer circuit 50 increases, to
Shorten the delay time of transmission line 50, delay time is shorter, and the variation of delay gets over unobvious and therefore effectively reduces Vdd2Or
Person VddqVariation relative to entire transmission line 50 total voltage influence, and then effectively reduce Vdd2Or VddqVariation pair
The influence of delay time.
Further, in above-mentioned DQS signal delay control circuit, DQS input circuits 30 and DQ input circuits 20 are equal
It is V that access, which provides operating voltage,ddqInternal work power supply.
Further, in above-mentioned DQS signal delay control circuit, internal circuit includes buffer register.
Wherein, buffer register (buffer) can temporarily store the data that main control chip 10 is sent, or for temporary
Shi Cunfang semiconductor memories 40 are sent to the data of main control chip 10, play coordination and cache work main control chip 10 with
The synchronization of data transmission is realized in the effect of the semiconductor memory 40 to work at a slow speed.
It should be pointed out that the V mentioned in the present embodimentdd1、Vdd2、VddqFor according to JEDEC standard JESD209-4 or
The operating voltage for the semiconductor memory 40 that JESD209-4B is defined.
Embodiment three
The embodiment of the present invention three additionally provides a kind of semiconductor memory 40, including described in embodiment as shown in Figure 3 two
DQS signal delay control circuit, details are not described herein again.
Example IV
The embodiment of the present invention four additionally provides a kind of DQS signal delay control method, by above-mentioned DQS signal delays time to control electricity
Road is implemented, in the DQS signal delay control circuit, the transmission line between DQS input circuits 30 and DQ input circuits 20
At least one of internal circuit access semiconductor memory 40 regulated power supply, wherein when in the transmission line exist it is more
When a internal circuit, multiple internal circuits are sequentially connected on DQS input circuits 30 to 20 direction of DQ input circuits；
As shown in figure 4, this method includes：
Step S1：The Parameters variation in DQS signal delay control circuit in semiconductor memory 40 is detected, and according to parameter
Variation and preset stable operating voltage generation strategy generate stable operating voltage output corresponding with Parameters variation；
Step S2：Stable operating voltage output is supplied to internal circuit, so that delay of the DQS signal in transmission line
The variation of time tends to a stationary value.
Further, in above-mentioned DQS signal delay control method, step S1 includes：
When detecting the temperature change in the delay control circuit, the preset stable operating voltage generation strategy be
In preset temperature range, the temperature is positively correlated with the stable operating voltage；
According to the temperature change and the positively related generation strategy of stable operating voltage, corresponding stable operating voltage is generated
Output.
Further, in above-mentioned DQS signal delay control method, step S1 includes：
When detecting the voltage change for the internal circuit for not accessing the regulated power supply 60 in the delay control circuit,
The preset stable operating voltage generation strategy is does not access voltage and the institute of the internal circuit of the regulated power supply 60
Stable operating voltage is stated to be negatively correlated；
According to the voltage change for the internal circuit for not accessing the regulated power supply 60 in the delay control circuit with
The generation strategy of stable operating voltage negative correlation generates corresponding stable operating voltage output.
DQS signal delay control method provided in an embodiment of the present invention can effectively reduce delay time by internal work
The influence of the variation of the parameters such as voltage or operating temperature, to obtain stable delay time.
The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any
Those familiar with the art in the technical scope disclosed by the present invention, can readily occur in its various change or replacement,
These should be covered by the protection scope of the present invention.Therefore, protection scope of the present invention should be with the guarantor of the claim
It protects subject to range.
Claims (14)
1. a kind of DQS signal delay control circuit is applied to semiconductor memory, which is characterized in that the delay control circuit
Including DQS input circuits, DQ input circuits and transmission line, the input terminal of the transmission line connects with the DQS input circuits
It connecing, the output end of the transmission line is connect with the DQ input circuits, and the transmission line includes at least one internal circuit,
And when the internal circuit is multiple, multiple internal circuits are in the DQS input circuits to the DQ input circuits
It is sequentially connected in transmission direction；
At least one of described internal circuit accesses regulated power supply, and the regulated power supply is used for the internal circuit of access
Stable operating voltage is provided；
The delay control circuit further includes controller, and the controller is connect with the regulated power supply, and the controller is used for
The Parameters variation in the delay control circuit is detected, and is generated according to the Parameters variation and preset stable operating voltage
Strategy, generates the output of the stable operating voltage corresponding with the Parameters variation, and the output of the stable operating voltage is used
In being supplied to the internal circuit；
Wherein, the Parameters variation is that the voltage for the internal circuit for not accessing the regulated power supply in the delay control circuit becomes
Change, the preset stable operating voltage generation strategy be the internal circuit for not accessing the regulated power supply voltage with it is described surely
Fixed working voltage is negatively correlated.
2. DQS signal delay control circuit as described in claim 1, which is characterized in that the ginseng in the delay control circuit
Number variation is the variation of the temperature in the delay control circuit, and the preset stable operating voltage generation strategy is default
In temperature range, the temperature is positively correlated with the stable operating voltage.
3. DQS signal delay control circuit as described in claim 1, which is characterized in that the stable operating voltage is by working
Voltage is Vdd1Internal work power supply or external power supply provide charge pump provide.
4. DQS signal delay control circuit as claimed in claim 3, which is characterized in that the stable operating voltage is more than institute
The voltage V of internal work power supply offer is provideddd2Or Vddq, VddqIt is available to the DQS input circuits and DQ input electricity
The voltage on road, Vdd2It is available to the voltage of the part internal circuit.
5. DQS signal delay control circuit as described in claim 1, which is characterized in that the internal circuit includes that buffering is posted
Storage.
6. a kind of DQS signal delay control circuit is applied to semiconductor memory, which is characterized in that the delay control circuit
Including DQS input circuits, DQ input circuits and transmission line, the input terminal of the transmission line connects with the DQS input circuits
It connecing, the output end of the transmission line is connect with the DQ input circuits, and the transmission line includes at least one internal circuit,
And when the internal circuit is multiple, multiple internal circuits are in the DQS input circuits to the DQ input circuits
It is sequentially connected in transmission direction；
At least one of described internal circuit accesses regulated power supply, and the regulated power supply is used for the internal circuit of access
Stable operating voltage is provided；
The delay control circuit further includes controller, and the controller is connect with the regulated power supply, and the controller is used for
The Parameters variation in the delay control circuit is detected, and is generated according to the Parameters variation and preset stable operating voltage
Strategy, generates the output of the stable operating voltage corresponding with the Parameters variation, and the output of the stable operating voltage is used
In being supplied to the internal circuit；
Wherein, the stable operating voltage is V by operating voltagedd1Internal work power supply or external power supply provide charge pump
It provides, the stable operating voltage is more than the voltage V that the internal work power supply providesdd2Or Vddq, VddqIt is available to described
The voltage of DQS input circuits and the DQ input circuits, Vdd2It is available to the voltage of the part internal circuit.
7. DQS signal delay control circuit as claimed in claim 6, which is characterized in that the ginseng in the delay control circuit
Number variation is the variation of the temperature in the delay control circuit, and the preset stable operating voltage generation strategy is default
In temperature range, the temperature is positively correlated with the stable operating voltage.
8. DQS signal delay control circuit as claimed in claim 7, which is characterized in that the ginseng in the delay control circuit
Number variation is the voltage change for the internal circuit for not accessing the regulated power supply in the delay control circuit, described preset steady
Fixed working voltage generation strategy is voltage and the stable operating voltage of the internal circuit for not accessing the regulated power supply at negative
It is related.
9. DQS signal delay control circuit as claimed in claim 6, which is characterized in that the internal circuit includes that buffering is posted
Storage.
10. a kind of semiconductor memory, which is characterized in that be delayed including DQS signal as described in any one of claim 1 to 9
Control circuit.
11. a kind of DQS signal delay control method, the DQS signal delay control circuit being applied in semiconductor memory is special
Sign is, in the DQS signal delay control circuit, in the transmission line between DQS input circuits and DQ input circuits
The regulated power supply of at least one internal circuit access semiconductor memory, wherein when there are multiple inside in the transmission line
When circuit, multiple internal circuits are sequentially connected in the transmission direction of the DQS input circuits to the DQ input circuits；
The control method includes：
The Parameters variation in DQS signal delay control circuit in the semiconductor memory is detected, when the Parameters variation is institute
When stating the voltage change for the internal circuit for not accessing the regulated power supply in delay control circuit, preset steady operation electricity
Pressure generation strategy is that the voltage for the internal circuit for not accessing the regulated power supply is negatively correlated with stable operating voltage；
According to the voltage for the internal circuit for not accessing the regulated power supply in the delay control circuit and the stable work
Make the relevant generation strategy of voltage negative, generates the output of the corresponding stable operating voltage；
The output of the stable operating voltage is supplied to the internal circuit, so that DQS signal is in the transmission line
The variation of delay time tends to a stationary value.
12. DQS signal delay control method as claimed in claim 11, which is characterized in that generate the stable operating voltage
Output the step of include：
When detecting the variation of the temperature in the delay control circuit, the preset stable operating voltage generation strategy is pre-
If in temperature range, the temperature is positively correlated with the stable operating voltage；
According to the variation of the temperature and the positively related generation strategy of the stable operating voltage, the corresponding stable work is generated
Make the output of voltage.
13. a kind of DQS signal delay control method, the DQS signal delay control circuit being applied in semiconductor memory is special
Sign is, in the DQS signal delay control circuit, in the transmission line between DQS input circuits and DQ input circuits
The regulated power supply of at least one internal circuit access semiconductor memory, wherein when there are multiple inside in the transmission line
When circuit, multiple internal circuits are sequentially connected in the transmission direction of the DQS input circuits to the DQ input circuits；
The control method includes：
The Parameters variation in DQS signal delay control circuit in the semiconductor memory is detected, and according to the Parameters variation
And preset stable operating voltage generation strategy, generate the output of stable operating voltage corresponding with the Parameters variation；
Operating voltage is Vdd1Internal work power supply or the charge pump that provides of external power supply the stable operating voltage, institute are provided
It states stable operating voltage and is more than the voltage V that the internal work power supply providesdd2Or Vddq, VddqIt is available to the DQS inputs
The voltage of circuit and the DQ input circuits, Vdd2It is available to the voltage of the part internal circuit；
The output of the stable operating voltage is supplied to the internal circuit, so that the DQS signal is in the transmission line
In the variation of delay time tend to a stationary value.
14. DQS signal delay control method as claimed in claim 13, which is characterized in that generate the stable operating voltage
Output the step of include：
When detecting the variation of the temperature in the delay control circuit, the preset stable operating voltage generation strategy is pre-
If in temperature range, the temperature is positively correlated with the stable operating voltage；
According to the variation of the temperature and the positively related generation strategy of the stable operating voltage, the corresponding stable work is generated
Make the output of voltage.
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| CN117784882A (en) * | 2022-09-21 | 2024-03-29 | 长鑫存储技术有限公司 | Data sampling circuit, delay detection circuit and memory |
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Effective date of registration: 20181008 Address after: 230000 room 630, Hai Heng mansion 6, Cui Wei Road, Hefei economic and Technological Development Zone, Anhui Patentee after: Changxin Storage Technology Co., Ltd. Address before: 230000 room 526, Hai Heng mansion 6, Cui Wei Road, Hefei economic and Technological Development Zone, Anhui Patentee before: Ever power integrated circuit Co Ltd |