CN107452323B - Circuit and method for realizing continuous scanning of any channel - Google Patents
Circuit and method for realizing continuous scanning of any channel Download PDFInfo
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- CN107452323B CN107452323B CN201610373438.3A CN201610373438A CN107452323B CN 107452323 B CN107452323 B CN 107452323B CN 201610373438 A CN201610373438 A CN 201610373438A CN 107452323 B CN107452323 B CN 107452323B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
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Abstract
The invention relates to a circuit and a method for realizing continuous scanning of any channel, wherein the circuit comprises a channel enabling register, a channel enabling temporary register, a priority decoding module, a logic gate group and a channel scanning module, wherein the input end of the channel enabling temporary register is connected with the output end of the channel enabling register, the input end of the priority decoding module is connected with the output end of the channel enabling temporary register, the output end of the priority decoding module is connected with the input end of the logic gate group, the output end of the logic gate group is connected with the input end of the channel scanning module, and the input end of the channel enabling temporary register is also connected with the output end of the channel scanning module. By adopting the circuit and the method with the structure, the scanning channels can be freely configured, strong application flexibility can be realized, the scanning sequence is not fixed, the scanning sequence of the channels can be selected according to the default priority or the set priority, and the scanning efficiency is improved.
Description
Technical Field
The invention relates to the technical field of scanning circuits, in particular to a hardware-based scanning circuit, and specifically relates to a circuit and a method for realizing continuous scanning of any channel.
Background
A typical implementation is shown in FIG. 1, where modulo n of the counter is equal to a selected number of COM pins, e.g., the selected number of COM pins is 3, the counter is a modulo 3 counter, of course, the number of COM pins may also be software configurable, where the counter is a modulo variable counter, the current count value of the counter is compared, the carrier generated in FIG. 1 is assigned to the corresponding COM pin, e.g., the current count value is 1, the carrier is assigned to a COM pin 56 (e.g., the current count value is 1, the remaining COM pins are assigned to a COM pin (e.g., the Common pins are assigned to a COM pin), the remaining COM pins are assigned to a Common pin, the Common pins are assigned a Common pin number of a Common pin number equal number, and the Common pins are assigned a Common pin number equal to a Common pin number of a Common pin number equal to the Common pin number of a Common pin, e.g., a Common pin number equal to a Common pin number of a Common pin equal to a Common pin number of a Common pin equal number of Common pin, e.g., Common pin equal to a Common pin, a Common pin number of Common pin equal pin, a.
The waveform of the existing scanning circuit is shown in fig. 2, and only a plurality of channels in fixed sequence can be scanned in sequence, and the scanning technology has two defects: first, the scanning channel is fixed (channel 1, channel 2, channel 3 … … channel n in the example of fig. 2), and the application flexibility is not strong. For example, the application needs only channel 1, channel 3 and channel 7 to output the scanning waveform, and the technology cannot be realized; secondly, the scanning sequence is fixed (the scanning waveforms are sequentially output from the channel 1, the channel 2 and the channel 3 … … in the example of fig. 2), and the efficiency is not high. For example, the application only needs to use the scanning waveforms of the pin1 and the pin3, the pin2 is not used, and under the technology, the scanning waveform of the pin3 is given after the scanning waveform on the pin2 is finished, so that the scanning time is wasted.
Disclosure of Invention
The present invention is directed to overcoming the above-mentioned drawbacks of the prior art and providing a circuit and a method for enabling a scan channel to be freely configured and for continuously scanning any channel.
In order to achieve the above object, the present invention has the following configurations:
the invention provides a circuit for realizing continuous scanning of any channel, which comprises a channel enabling register, a channel enabling temporary storage register, a priority decoding module, a logic gate group and a channel scanning module, wherein the input end of the channel enabling temporary storage register is connected with the output end of the channel enabling register, the input end of the priority decoding module is connected with the output end of the channel enabling temporary storage register, the output end of the priority decoding module is connected with the input end of the logic gate group, and the output end of the logic gate group is connected with the input end of the channel scanning module, wherein:
the channel enabling register is used for setting the enabling state of each channel and sending the initial set value to the channel enabling temporary storage register;
the channel enable temporary storage register is used for receiving the initial set value, storing the initial set value as a temporary storage value and modifying the enable state of a channel corresponding to the channel scanning end signal in the temporary storage value when the channel scanning end signal is received;
the priority decoding module is used for carrying out priority decoding on the temporary storage value according to the preset priority relationship among the enabled channels;
the logic gate group is used for carrying out logic operation on the carrier wave according to the result of the priority decoding to generate a scanning output signal;
and the channel scanning module is used for scanning channels according to the scanning output signals of the logic gate group and sending a channel scanning end signal to the channel enable temporary storage register after each scanning is finished.
Preferably, the output end of the priority decoding module is further connected to the input end of a channel enable register, and the channel enable register determines the channel corresponding to the channel scan end signal according to the result of the priority decoding output by the priority decoding module.
Preferably, the priority decoding module further includes a plurality of priority configuration registers, the priority configuration registers correspond to the channels one to one, and the priority configuration registers are used for performing preset configuration on the priority relationship between the enabled channels in the initial setting values.
Preferably, the priority decoding module further includes a plurality of priority configuration registers, the priority configuration registers correspond to the channels one to one, and the priority configuration registers are used for performing preset configuration on the priority relationship between the channels.
Preferably, the initial setting value is an array having a bit width n, where n is a total number of channels, a bit number corresponding to an enabled channel in the initial setting value is a number 1, and a number corresponding to a channel which is not required to be scanned in the initial setting value is 0.
Preferably, the result of the priority decoding is an array with a bit width of n, wherein the bit number corresponding to the channel with the highest priority among the enabled channels in the temporary storage value is a value 1, and the bit numbers corresponding to the other channels are values 0.
Preferably, the channel enable register is used for storing a series of different setting values, and each setting value sets the enable state of each channel; and during each continuous scanning, selecting one unprocessed set value from the stored set values as an initial set value, and sending the initial set value to the channel enable temporary storage register.
The invention also relates to a method for realizing continuous scanning of any channel based on the circuit, which is characterized by comprising the following steps:
(1) the channel enabling register sends an initial set value to the channel enabling temporary storage register;
(2) the channel enabling temporary storage register receives the initial set value and stores the initial set value as a temporary storage value;
(3) the priority decoding module performs priority decoding on the temporary storage value according to the preset priority relationship among the enabled channels and sends a priority decoding result to the logic gate group;
(4) the logic gate group performs logic operation on the carrier wave according to the priority decoding result to generate a scanning output signal;
(5) the channel scanning module carries out channel scanning according to the scanning output signal of the logic gate group and sends a channel scanning end signal to the channel enable temporary storage register;
(6) the channel enabling temporary storage register modifies the enabling state corresponding to the channel finishing scanning in the temporary storage value;
(7) and (4) the channel enabling temporary storage register judges whether an enabled channel still exists in the temporary storage value, if so, the step (3) is continued, and if not, the exit is finished.
Preferably, the priority decoding module further includes a plurality of priority configuration registers, the plurality of priority configuration registers correspond to the channels one by one, and the steps (2) and (3) include the following steps:
and (2-1) the priority configuration registers are used for presetting and configuring the priority relationship of each enabled channel in the initial setting value.
Preferably, the priority decoding module further includes a plurality of priority configuration registers, the plurality of priority configuration registers correspond to the respective channels one to one, and before the step (1), the method further includes the following steps:
(0-1) the priority configuration registers are used for carrying out preset configuration on the priority relationship of each channel.
Preferably, the preset priority relationship among the enabled channels is: the larger the lane number, the higher the lane priority.
Preferably, the initial setting value is an array having a bit width n, where n is a total number of channels, a bit number corresponding to an enabled channel in the initial setting value is a value 1, and a value that is not required to be scanned in the initial setting value is 0.
Preferably, the result of the priority decoding is an array with a bit width of n, wherein the bit number corresponding to the channel with the highest priority among the enabled channels in the temporary storage value is a value 1, and the bit numbers corresponding to the other channels are values 0.
Preferably, the output end of the priority decoding module is further connected to the input end of the channel enable register, and the method between steps (5) and (6) further includes the following steps:
and (5-1) the channel enable register determines the channel corresponding to the channel scanning end signal according to the result of the priority decoding output by the priority decoding module.
Preferably, in the preset of the channel scan module, when the enabled channel in the temporary storage value in the scan output signal is at a high level, the logic gate set generates the scan output signal according to the result of the priority decoding, specifically:
the logic gate group adopts an AND gate group, and the result signal of the priority decoding and the carrier are subjected to bitwise AND operation to generate a scanning output signal.
Preferably, in the preset of the channel scan module, when the enabled channel in the temporary storage value in the scan output signal is at a low level, the logic gate set generates the scan output signal according to the result of the priority decoding, specifically:
the logic gate group adopts an OR gate group, firstly, the result signal of the priority decoding is inverted according to bits, and then the result signal and the carrier wave are subjected to OR operation according to bits to generate a scanning output signal.
Preferably, the channel enable register is configured to store a series of different setting values, each setting value setting an enable state of each channel, and the step (1) specifically includes:
during each continuous scanning, the channel enabling register selects one unprocessed set value from the stored set values as an initial set value and sends the initial set value to the channel enabling temporary storage register;
the step (7) comprises the following steps:
(7-1) the channel enabling temporary storage register judges whether an enabled channel still exists in the temporary storage value, if so, the step (3) is continued, otherwise, the step (7-2) is continued;
and (7-2) the channel enabling register judges whether unprocessed set values exist or not, if so, the step (1) is continued, and if not, the exit is finished.
By adopting the circuit and the method for realizing continuous scanning of any channel, the scanning channel can be freely configured, strong application flexibility can be realized, the scanning sequence is not fixed, the channel scanning sequence can be selected according to the default priority or the set priority, and the scanning efficiency is improved.
Drawings
Fig. 1 is a schematic block diagram of a typical embodiment of the prior art.
Fig. 2 is a waveform diagram illustrating an operation of a scan circuit according to the prior art.
FIG. 3 is a block diagram of one embodiment of a circuit for continuous scanning of any channel of the present invention.
FIG. 4 is a waveform diagram illustrating the operation of one embodiment of the present invention for a circuit for continuously scanning any channel.
Detailed Description
In order to more clearly describe the technical contents of the present invention, the following further description is given in conjunction with specific embodiments.
The circuit for realizing continuous scanning of any channel is characterized by comprising a channel enabling register, a channel enabling temporary storage register, a priority decoding module, a logic gate group and a channel scanning module, wherein the input end of the channel enabling temporary storage register is connected with the output end of the channel enabling register, the input end of the priority decoding module is connected with the output end of the channel enabling temporary storage register, the output end of the priority decoding module is connected with the input end of the logic gate group, and the output end of the logic gate group is connected with the input end of the channel scanning module, wherein:
the channel enabling register is used for setting the enabling state of each channel and sending the initial set value to the channel enabling temporary storage register;
the channel enable temporary storage register is used for receiving the initial set value, storing the initial set value as a temporary storage value and modifying the enable state of a channel corresponding to the channel scanning end signal in the temporary storage value when the channel scanning end signal is received;
the priority decoding module is used for carrying out priority decoding on the temporary storage value according to the preset priority relationship among the enabled channels;
the logic gate group is used for carrying out logic operation on the carrier wave according to the result of the priority decoding to generate a scanning output signal;
and the channel scanning module is used for scanning channels according to the scanning output signals of the logic gate group and sending a channel scanning end signal to the channel enable temporary storage register after each scanning is finished.
In a preferred embodiment, the output end of the priority decoding module is further connected to the input end of a channel enable register, and the channel enable register determines a channel corresponding to the channel scan end signal according to a result of the priority decoding output by the priority decoding module.
In a preferred embodiment, the priority decoding module further includes a plurality of priority configuration registers, the priority configuration registers correspond to the channels one to one, the priority configuration registers are configured to perform preset configuration on the priority relationships between the channels enabled in the initial setting values, and the priority configuration registers may also perform preset configuration on the priority relationships between the channels.
In a preferred embodiment, the initial setting value is an array having a bit width n, where n is the total number of channels, the number of bits corresponding to the enabled channels in the initial setting value is 1, and the number of bits corresponding to the channels that are not required to be scanned in the initial setting value is 0.
In a preferred embodiment, the result of the priority decoding is an array with a bit width of n, wherein the bit number corresponding to the channel with the highest priority among the enabled channels in the temporary storage value is a value 1, and the bit numbers corresponding to the other channels are values 0.
In a preferred embodiment, the channel enable register is configured to store a series of different setting values, each setting value setting an enable state of a respective channel; and during each continuous scanning, selecting one unprocessed set value from the stored set values as an initial set value, and sending the initial set value to the channel enable temporary storage register.
The invention also relates to a method for realizing continuous scanning of any channel based on the circuit, which is characterized by comprising the following steps:
(1) the channel enabling register sends an initial set value to the channel enabling temporary storage register;
(2) the channel enabling temporary storage register receives the initial set value and stores the initial set value as a temporary storage value;
(3) the priority decoding module performs priority decoding on the temporary storage value according to the preset priority relationship among the enabled channels and sends a priority decoding result to the logic gate group;
(4) the logic gate group performs logic operation on the carrier wave according to the priority decoding result to generate a scanning output signal;
(5) the channel scanning module carries out channel scanning according to the scanning output signal of the logic gate group and sends a channel scanning end signal to the channel enable temporary storage register;
(6) the channel enabling temporary storage register modifies the enabling state corresponding to the channel finishing scanning in the temporary storage value;
(7) and (4) the channel enabling temporary storage register judges whether an enabled channel still exists in the temporary storage value, if so, the step (3) is continued, and if not, the exit is finished.
In a preferred embodiment, the priority decoding module further includes a plurality of priority configuration registers, the plurality of priority configuration registers are in one-to-one correspondence with the channels, and the steps (2) and (3) include the following steps:
and (2-1) the priority configuration registers are used for presetting and configuring the priority relationship of each enabled channel in the initial setting value.
In a preferred embodiment, the priority decoding module further includes a plurality of priority configuration registers, the plurality of priority configuration registers correspond to the channels one by one, and before the step (1), the method further includes the following steps:
(0-1) the priority configuration registers are used for carrying out preset configuration on the priority relationship of each channel.
In a preferred embodiment, the predetermined priority relationship between each enabled channel is: the larger the lane number, the higher the lane priority.
In a preferred embodiment, the initial setting value is an array having a bit width n, where n is a total number of channels, a number of bits corresponding to enabled channels in the initial setting value is 1, and a value not required to be scanned in the initial setting value is 0.
In a preferred embodiment, the result of the priority decoding is an array with a bit width of n, wherein the bit number corresponding to the channel with the highest priority among the enabled channels in the temporary storage value is a value 1, and the bit numbers corresponding to the other channels are values 0.
In a preferred embodiment, the output terminal of the priority decoding module is further connected to the input terminal of the channel enable register, and the method further includes, between steps (5) and (6):
and (5-1) the channel enable register determines the channel corresponding to the channel scanning end signal according to the result of the priority decoding output by the priority decoding module.
In a preferred embodiment, in the preset of the channel scan module, when the enabled channel in the temporary storage of the scan output signal is at high level, the logic gate set generates the scan output signal according to the result of the priority decoding, specifically:
the logic gate group adopts an AND gate group, and the result signal of the priority decoding and the carrier are subjected to bitwise AND operation to generate a scanning output signal.
In a preferred embodiment, in the preset of the channel scan module, when the enabled channel in the temporary storage of the scan output signal is at low level, the logic gate set generates the scan output signal according to the result of the priority decoding, specifically:
the logic gate group adopts an OR gate group, firstly, the result signal of the priority decoding is inverted according to bits, and then the result signal and the carrier wave are subjected to OR operation according to bits to generate a scanning output signal.
In a preferred embodiment, the channel enable register is configured to store a series of different setting values, each setting value setting an enable state of each channel, and the step (1) is specifically:
during each continuous scanning, the channel enabling register selects one unprocessed set value from the stored set values as an initial set value and sends the initial set value to the channel enabling temporary storage register;
the step (7) comprises the following steps:
(7-1) the channel enabling temporary storage register judges whether an enabled channel still exists in the temporary storage value, if so, the step (3) is continued, otherwise, the step (7-2) is continued;
and (7-2) the channel enabling register judges whether unprocessed set values exist or not, if so, the step (1) is continued, and if not, the exit is finished.
Thus, a series of setting values can be stored in the channel enable register at the same time, and the scanning of multiple frames and multiple channels can be continuously carried out as long as the setting values are set.
The following describes the process of continuous scanning of a specific channel in a specific embodiment:
the channel enable register is configurable as shown in FIG. 3 to determine which channels are scanned and which are not. Assuming that there are n channels at most (in the following description, n represents the maximum number of channels), the register is n bit, bit0 ═ 0/1 represents channel 0 no scan/scan, bit1 ═ 0/1 represents channel 1 no scan/scan, and so on.
At the beginning of the scan, the value of the channel enable register is assigned to the channel enable scratch register. Namely: the channel enable scratch register "scratches" the value of the channel enable register at this time.
And performing priority decoding on the value in the channel enable temporary storage register to obtain a ch _ dec signal, wherein the bit width is n. Assuming that n is 4, the value in the channel enable register is 0111 (channel 3 is not enabled, channels 2, 1, 0 are enabled), and among channels 2, 1, 0, channel 2 has the highest priority, then the decoded ch _ dec signal is 0100 (bit 2 is 1 only, and the rest are 0).
The priority of the channel can be fixed in hardware or can be matched in software. If a software-configurable channel priority is selected, this may be implemented using a set of priority configuration registers.
If the implementation of the priority configuration registers is adopted, the number of the priority configuration registers is selected to be n, and each priority configuration register corresponds to one channel (whether the channel is scanned or not scanned). The value in the priority configuration register corresponding to the enabled channel in the initial setting value expresses the priority of the channel, and the value in the priority configuration register corresponding to the disabled channel in the initial setting value is an irrelevant value. The priority decoding module obtains a ch _ dec signal according to the value of the channel enable register and the value of the priority configuration register.
Another typical implementation of priority decoding is that the number of priority configuration registers is n (number of lanes), and the bit width ≧ log2 n. For example, if n is 4, 4 priority configuration registers (one for each channel) are used, and the bit width is 2. Assuming that the channel priority order is channel 2> channel 3> channel 1> channel 4, the values in the 4 priority configuration registers are shown in table 1 (here, only a typical implementation of the priority configuration registers is given, and other implementations may be used in practice):
watch 1
| Priority order (from high to low) | Corresponding to the value of the configuration register |
| Channel 2 | 3 |
| Channel 3 | 2 |
| Channel 1 | 1 |
| Channel 4 | 0 |
The result of the priority decoding, namely the ch _ dec signal, enters the logic gate set and is respectively subjected to logic operation with the carrier to generate a scan output signal. If the application requires that the channel which is not scanned at present should output low level, the logic gate group adopts an AND gate group, and the ch _ dec signal and the carrier wave are bitwise AND; if the application requires that the channel which is not scanned currently should output high level, the logic gate group adopts an OR gate group, and the ch _ dec signal is inverted according to bits and then subjected to bit OR with the carrier wave. The carrier wave may be a fixed high level, a fixed low level, or a plurality of continuous pulses or other waveforms, depending on the application environment. Assuming that n is 4, the ch _ dec signal is 0100, and the and gate set is used for the logic gate set, the scan output is as shown in table 2:
TABLE 2
| Channel number | Corresponding to ch _ dec value | The channel outputs |
| 3 | 0 | 0 (Low) |
| 2 | 1 | Carrier wave |
| 1 | 0 | 0 (Low) |
| 0 | 0 | 0 (Low) |
Assuming that n is 4, the ch _ dec signal is 0100, and the or gate set is used for the logic gate set, the scan output is as shown in table 3:
TABLE 3
| Channel number | Corresponding to ch _ dec value | Corresponding to the inverted value of ch _ dec | The channel outputs |
| 3 | 0 | 1 | 1 (high) |
| 2 | 1 | 0 | Carrier wave |
| 1 | 0 | 1 | 1 (high) |
| 0 | 0 | 1 | 1 (high) |
Each time one channel scan is finished, one channel scan end signal is generated. When the channel scan end signal is asserted, the "1" of the most significant bit in the channel enable register is cleared. For example, if n is 4, the value in the channel enable register is 0111 (channel 3 is not enabled, channels 2, 1, 0 are enabled), then a scan waveform will be generated in channel 2 after priority decoding, when channel 2 scanning is finished, bit2 of the channel enable register will be cleared according to the generated channel scan end signal, its value is 0011 (channels 3, 2 are not enabled, channels 1, 0 are enabled), then channel 1 will be scanned, and so on.
When one frame of scanning is finished (all enabled channels are scanned completely), if the next frame of scanning needs to be started, a frame scanning end signal is generated. According to the signal, the value of the channel enable register is given to the channel enable register again. The previous process can then be repeated for the next frame scan. When the frame scanning end signal and the channel scanning end signal occur simultaneously, the frame scanning end signal takes precedence (the action of "assigning the value of the channel enable register to the channel enable register" is still performed).
The complete operating waveform is shown in fig. 4, assuming that n is 4, the channel enable register value is 0111, the hardware has a fixed channel priority, the channel 3 priority > the channel 2> the channel 1> the channel 0, and the carrier is a fixed high level.
By adopting the circuit and the method for realizing continuous scanning of any channel, the scanning channel can be freely configured, strong application flexibility can be realized, the scanning sequence is not fixed, the channel scanning sequence can be selected according to the default priority or the set priority, and the scanning efficiency is improved.
In this specification, the invention has been described with reference to specific embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.
Claims (13)
1. A circuit for realizing continuous scanning of any channel is characterized by comprising a channel enable register, a channel enable temporary storage register, a priority decoding module, a logic gate group and a channel scanning module, the input end of the channel enable temporary storage register is connected with the output end of the channel enable register, the input end of the priority decoding module is connected with the output end of the channel enable temporary storage register, the output end of the priority decoding module is connected with the input end of a logic gate group, the output end of the logic gate group is connected with the input end of the channel scanning module, the output end of the priority decoding module is also connected with the input end of the channel enable temporary storage register, the channel enabling temporary storage register determines a channel corresponding to a channel scanning end signal according to a priority decoding result output by the priority decoding module; wherein:
the channel enabling register is used for setting the enabling state of each channel and sending the initial set value to the channel enabling temporary storage register;
the channel enable temporary storage register is used for receiving the initial set value, storing the initial set value as a temporary storage value and modifying the enable state of a channel corresponding to the channel scanning end signal in the temporary storage value when the channel scanning end signal is received;
the priority decoding module is used for carrying out priority decoding on the temporary storage value according to the preset priority relationship among the enabled channels;
the logic gate group is used for carrying out logic operation on the carrier wave according to the result of the priority decoding to generate a scanning output signal;
and the channel scanning module is used for scanning channels according to the scanning output signals of the logic gate group and sending a channel scanning end signal to the channel enable temporary storage register after each scanning is finished.
2. The circuit according to claim 1, wherein the priority decoding module further comprises a plurality of priority configuration registers, the plurality of priority configuration registers are in one-to-one correspondence with the channels, and the plurality of priority configuration registers are configured to pre-configure the priority relationship between enabled channels in the initial setting value; the value in the priority configuration register corresponding to the enabled channel in the initial setting value is the priority of the channel, and the value in the priority configuration register corresponding to the channel which is not enabled in the initial setting value is an irrelevant value.
3. The circuit according to claim 1, wherein the priority decoding module further comprises a plurality of priority configuration registers, the plurality of priority configuration registers correspond to the channels one by one, and the plurality of priority configuration registers are used for configuring the priority relationship between the channels in a preset manner.
4. The circuit according to claim 1, wherein the initial setting value is an array having a bit width n, n is a total number of channels, a number of bits corresponding to enabled channels in the initial setting value is 1, and a number of bits corresponding to channels not to be scanned in the initial setting value is 0.
5. The circuit according to claim 4, wherein the result of the priority decoding is an array with a bit width n, wherein the number of bits corresponding to the channel with the highest priority among the enabled channels in the temporary storage is 1, and the number of bits corresponding to other channels is 0.
6. The circuit of claim 1, wherein the channel enable register is configured to store a series of different setting values, each setting value setting an enable status of a respective channel; and during each continuous scanning, selecting one unprocessed set value from the stored set values as an initial set value, and sending the initial set value to the channel enable temporary storage register.
7. A method for realizing continuous scanning of any channel based on the circuit of any one of claims 1 to 6, wherein the method comprises the following steps:
(1) the channel enabling register sends an initial set value to the channel enabling temporary storage register;
(2) the channel enabling temporary storage register receives the initial set value and stores the initial set value as a temporary storage value;
(3) the priority decoding module performs priority decoding on the temporary storage value according to the preset priority relationship among the enabled channels and sends a priority decoding result to the logic gate group;
(4) the logic gate group performs logic operation with the carrier according to the priority decoding result to generate a scanning output signal;
(5) the channel scanning module carries out channel scanning according to the scanning output signal of the logic gate group and sends a channel scanning end signal to the channel enable temporary storage register;
(6) the channel enabling temporary storage register modifies the enabling state corresponding to the channel finishing scanning in the temporary storage value;
(7) and (4) the channel enabling temporary storage register judges whether an enabled channel still exists in the temporary storage value, if so, the step (3) is continued, and if not, the exit is finished.
8. The method according to claim 7, wherein the priority decoding module further comprises a plurality of priority configuration registers, the plurality of priority configuration registers are in one-to-one correspondence with the respective channels, and the steps (2) and (3) include the following steps:
(2-1) the priority configuration registers are used for carrying out preset configuration on the priority relationship of each enabled channel in the initial setting value; the value in the priority configuration register corresponding to the enabled channel in the initial setting value is the priority of the channel, and the value in the priority configuration register corresponding to the channel which is not enabled in the initial setting value is an irrelevant value.
9. The method according to claim 7, wherein the priority decoding module further comprises a plurality of priority configuration registers, the plurality of priority configuration registers correspond to the channels one by one, and before the step (1), the method further comprises the following steps:
(0-1) the priority configuration registers are used for carrying out preset configuration on the priority relationship of each channel.
10. The method of claim 7, wherein the preset priority relationship between enabled channels is: the larger the lane number, the higher the lane priority.
11. The method as claimed in claim 7, wherein in the preset of the channel scan module, when the enabled channel in the temporary storage of the scan output signal is at high level, the logic gate set generates the scan output signal according to the result of the priority decoding, specifically:
the logic gate group adopts an AND gate group, and the result signal of the priority decoding and the carrier are subjected to bitwise AND operation to generate a scanning output signal.
12. The method as claimed in claim 7, wherein in the preset of the channel scan module, when the enabled channel in the temporary storage of the scan output signal is at low level, the logic gate set generates the scan output signal according to the result of the priority decoding, specifically:
the logic gate group adopts an OR gate group, firstly, the result signal of the priority decoding is inverted according to bits, and then the result signal and the carrier wave are subjected to OR operation according to bits to generate a scanning output signal.
13. The method according to claim 7, wherein the channel enable register is configured to store a series of different setting values, each setting value setting an enable status of a respective channel, and the step (1) is specifically:
during each continuous scanning, the channel enabling register selects one unprocessed set value from the stored set values as an initial set value and sends the initial set value to the channel enabling temporary storage register;
the step (7) comprises the following steps:
(7-1) the channel enabling temporary storage register judges whether an enabled channel still exists in the temporary storage value, if so, the step (3) is continued, otherwise, the step (7-2) is continued;
and (7-2) the channel enabling register judges whether unprocessed set values exist or not, if so, the step (1) is continued, and if not, the exit is finished.
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