CN107450305B - Time correction method and device for clock chip and intelligent equipment - Google Patents
Time correction method and device for clock chip and intelligent equipment Download PDFInfo
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- CN107450305B CN107450305B CN201710693313.3A CN201710693313A CN107450305B CN 107450305 B CN107450305 B CN 107450305B CN 201710693313 A CN201710693313 A CN 201710693313A CN 107450305 B CN107450305 B CN 107450305B
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- G04—HOROLOGY
- G04G—ELECTRONIC TIME-PIECES
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Abstract
The invention provides a time correction method, a time correction device and intelligent equipment of a clock chip, wherein the time correction method of the clock chip comprises the following steps: s1: acquiring time information determined by a timer and/or a counter, and judging whether an error exists in the travel time of a clock chip according to the time information determined by the timer and/or the counter; s2: and if the travel time of the clock chip is judged to have an error, compensating the travel time of the clock chip by using the timing of a timer and/or a counter. The invention can reduce the time error of the clock chip.
Description
Technical Field
The invention relates to the technical field of electronic devices, in particular to a time correction method and a time correction device of a clock chip and intelligent equipment.
Background
With the explosion of the intelligent consumer electronics industry, more and more intelligent devices are present in people's daily life.
Present intelligent equipment (like intelligent desk lamp, intelligent (window) curtain etc.) all have real-time clock function usually, and the main realization mode of this function includes two kinds: the first mode is that a clock chip is additionally arranged in the equipment, the second mode is that the current time is obtained by utilizing the Internet, and compared with the second mode, the first mode for realizing the clock function has no limitation of the Internet, so the application is wider;
however, for the first method of implementing a clock function by using a clock chip, the clock chip is usually provided with an accurate time base by a quartz crystal oscillator, but the real-time clock chip cannot accurately travel due to external electromagnetic interference, parasitic capacitance on a circuit board, and other factors, and even if an error of several seconds per day is accumulated over a long period of time, the problem is solved by performing a calibration once per day, that is, performing factory inspection on a batch of samples, then performing a calibration on the clock chips of the batch of products according to the detected error (for example, performing calibration at 0 minute of 0 day), and usually selecting an integer (for example, compensating for 3 seconds per day) to calibrate the clock chips, but since the error per day is not necessarily an integer, there is still an accumulated error.
Disclosure of Invention
Based on the above situation, the main objective of the present invention is to provide a time calibration method, a time calibration device, and an intelligent device for a clock chip, which can reduce the travel time error of the clock chip.
In order to achieve the above object, a technical solution of the present invention provides a timing method for a clock chip, including:
s1: acquiring time information determined by a timer and/or a counter, and judging whether an error exists in the travel time of a clock chip according to the time information determined by the timer and/or the counter;
s2: and if the travel time of the clock chip is judged to have an error, compensating the travel time of the clock chip by using the timing of a timer and/or a counter.
Preferably, the method for compensating the travel time of the clock chip by using the timing of the timer and/or the counter comprises the following steps: and if the time of the clock chip is judged to have an error, timing by using a timer and/or a counter, and compensating the time of the clock chip for second preset time when the timed time reaches first preset time.
Preferably, step S1 includes:
s11: reading a preset minute variable value and a minute value of the time of the clock chip, wherein the value range of the minute variable is an integer between 0 and 59, and the minute variable performs an operation of adding 1 per minute according to the timing of a timer and/or a counter;
s12: and if the read minute variable value is different from the minute value of the clock chip travel time, judging that the travel time of the clock chip has an error.
Preferably, before step S1, the method further includes:
and calculating the time required by the clock chip for generating the error of the second preset time relative to the standard time during the travel, thereby obtaining the first preset time.
Preferably, step S1 is performed once every third preset time.
Preferably, the third preset time is less than or equal to the first preset time.
Preferably, the second preset time is 1 second.
Preferably, before step S1, the method further includes:
and judging whether the clock chip is in a networking state, if not, executing a step S1, if so, acquiring time information from a preset server, and timing the clock chip according to the time information acquired from the server.
In order to achieve the above object, the technical solution of the present invention further provides a clock chip timing device, including:
the judging module is used for acquiring time information determined by a timer and/or a counter and judging whether an error exists in the travel time of the clock chip according to the time information determined by the timer and/or the counter;
and the timing module is used for compensating the travel time of the clock chip by utilizing the timing of the timer and/or the counter when the judging module judges that the travel time of the clock chip has errors.
Preferably, the timing module is configured to count time by using a timer and/or a counter when the determining module determines that there is an error in the travel time of the clock chip, and compensate for a second preset time of the travel time of the clock chip when the counted time reaches a first preset time.
Preferably, the judging module includes:
the clock chip comprises a reading unit, a timer and a counter, wherein the reading unit is used for reading a preset minute variable value and a clock chip travel time minute value, the value range of the minute variable is an integer between 0 and 59, and the minute variable performs an operation of adding 1 per minute according to the timing of the timer and/or the counter;
and the judging unit is used for judging that an error exists in the travel time of the clock chip if the read value of the minute variable is different from the minute value of the travel time of the clock chip.
Preferably, the timing device further includes:
and the calculating module is used for calculating the time required by the error of the second preset time generated by the travel time relative to the standard time of the clock chip so as to obtain the first preset time.
Preferably, every third preset time, the judging module acquires time information determined by a timer and/or a counter, and judges whether an error exists in the travel time of the clock chip according to the time information determined by the timer and/or the counter.
Preferably, the third preset time is less than or equal to the first preset time.
Preferably, the second preset time is 1 second.
Preferably, the timing device further includes:
the control module is used for judging whether the clock chip is in a networking state or not, if not, the control module controls the judging module to acquire time information determined by a timer and/or a counter, judges whether an error exists in the time of the clock chip according to the time information determined by the timer and/or the counter, and if the clock chip is in the networking state, acquires the time information from a preset service end and corrects the time of the clock chip according to the time information acquired from the service end.
In order to achieve the above object, the present invention further provides an intelligent device, including:
a clock chip;
a processor;
a memory for storing processor-executable instructions;
wherein the processor is configured to:
acquiring time information determined by a timer and/or a counter, and judging whether an error exists in the travel time of the clock chip according to the time information determined by the timer and/or the counter;
and if the time of the clock chip is judged to have an error, timing by using a timer and/or a counter, and compensating the time of the clock chip for second preset time when the timed time reaches first preset time.
Preferably, the processor comprises the timer and/or counter.
The time correcting method of the clock chip provided by the invention judges whether the travel time of the clock chip has errors or not by utilizing the time information determined by the timer and/or the counter, and compensates the travel time of the clock chip by utilizing the timing of the timer and/or the counter when judging that the travel time of the clock chip has errors.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
fig. 1 is a flowchart of a timing method of a clock chip according to an embodiment of the present invention;
FIG. 2 is a flowchart of another clock chip timing method according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a timing device of a clock chip according to an embodiment of the present invention.
Detailed Description
The following detailed description of embodiments of the present invention is provided in connection with the accompanying drawings and examples. The following examples are intended to illustrate the invention but are not intended to limit the scope of the invention.
Referring to fig. 1, fig. 1 is a flowchart of a timing method of a clock chip according to an embodiment of the present invention, where the method includes:
s1: acquiring time information determined by a timer and/or a counter, and judging whether an error exists in the travel time of a clock chip according to the time information determined by the timer and/or the counter;
s2: if the travel time of the clock chip is judged to have an error, the travel time of the clock chip is compensated by using the timer and/or the counter, specifically, if the travel time of the clock chip is judged to have an error, the travel time of the clock chip is timed by using the timer and/or the counter, and when the timed time reaches a first preset time, the travel time of the clock chip is compensated by using a second preset time.
According to the time correcting method of the clock chip provided by the embodiment of the invention, whether the travel time of the clock chip has an error is judged by utilizing the time information determined by the timer and/or the counter, when the travel time of the clock chip is judged to have the error, the timer and/or the counter is utilized for timing, and when the timing time reaches the first preset time, the travel time of the clock chip is compensated for the second preset time.
In step S1, the time information determined by the timer and/or the counter may include hour information, minute information, and second information, and since the current smart device usually displays only the hour information and the minute information and the error of the clock chip is not too large, it is possible to determine whether there is an error in the travel time of the clock chip by determining whether the minute information is accurate, preferably, the step S1 includes:
s11: reading a preset minute variable value and a minute value of the time of the clock chip, wherein the value range of the minute variable is an integer between 0 and 59, and the minute variable performs an operation of adding 1 per minute according to the timing of a timer and/or a counter;
s12: and if the read minute variable value is different from the minute value of the clock chip travel time, judging that the travel time of the clock chip has an error.
For example, the minute bit value of the current time may be assigned to the minute variable while the current time is being written to the clock chip (e.g., the current time written to the clock chip is 22 minutes and 42 minutes, when the minute variable is also assigned 42), after which the minute variable performs an add-1-per-minute operation based on the timing of the timer and/or counter, at any subsequent time, as the value of the minute variable read at the same time is the same as the minute value of the clock chip travel time, judging that there is no error in the clock chip, performing no timing operation in step S2, judging that there is an error in the clock chip if the value of the minute variable read at the same time is different from the minute value of the clock chip' S travel time, performing a timing operation in step S2, timing by using a timer and/or a counter, and compensating the travel time of the clock chip for second preset time when the timed time reaches first preset time;
in the invention, the value of the first preset time can be obtained by a pre-detection mode, that is, when the value of the second preset time is fixed, the time required for generating the error of the second preset time when the clock chip travels relative to the standard time can be calculated by pre-detecting the clock chip, then the required time is taken as the first preset time, for example, the sample clock chip can be tested, the error generated when the sample clock chip travels relative to the standard time every 24 hours (the test can be carried out for multiple times, then the average value is taken), then the time required for generating the error of the second preset time when the sample clock chip travels is obtained by the error calculation, namely the value of the first preset time is obtained, and the value is taken as the first preset time of the clock chips in the same batch with the sample clock chip;
for example, the second preset time is 1 second, and the error of the sample clock chip is measured to be +2.4 seconds/24 hours (i.e. every 24 hours is slower than the standard time by 2.4 seconds), so every 24 × 60/2.4 is 600 minutes, the clock chip will generate an error of about +1 second (i.e. every 600 minutes is slower than the standard time by 1 second), in the using process of the clock chips of the batch, if the walking time of the clock chip is judged to have an error, the clock chip is timed by using a timer and/or a counter, and when the timed time reaches 600 minutes, the walking time of the clock chip is compensated by adding 1 second;
for example, the second preset time is 1 second, and the error of the sample clock chip is measured to be-2.4 seconds/24 hours (i.e. every 24 hours is 2.4 seconds faster than the standard time), so every 24 × 60/2.4 is 600 minutes, the clock chip will generate an error of about-1 second (i.e. every 600 minutes is 1 second faster than the standard time), in the using process of the clock chips of the batch, if the timing of the clock chip is judged to have an error, the clock chip is timed by using a timer and/or a counter, and when the timed time reaches 600 minutes, the timing of the clock chip is compensated by subtracting 1 second;
preferably, to improve the accuracy of timing, each clock chip may obtain the value of the first preset time by detecting itself in advance, in an embodiment of the present invention, before step S1, the method further includes:
and calculating the time required by the clock chip for generating the error of the second preset time relative to the standard time during the travel, thereby obtaining the first preset time. The method comprises the steps of detecting a clock chip by a sample, detecting the clock chip by a sample detector, and obtaining a value of first preset time by detecting the clock chip, wherein the value of the first preset time of each clock chip is more accurate, and the accuracy of time correction is improved.
In the implementation of the present invention, step S1 may be executed once every third preset time, and preferably, the third preset time is less than or equal to the first preset time, so that step S1 is executed at least once every first preset time.
Referring to fig. 2, fig. 2 is a flowchart of another clock chip timing method according to an embodiment of the present invention, where the method includes:
s101: writing the current time into a new clock chip, and assigning the value of the minute bit of the current time to a minute variable a;
s102: resetting the timing and starting timing;
s103: judging whether the timing in the step S102 reaches a third preset time, if so, executing the step S104, meanwhile, resetting the timing, restarting the timing, and if not, continuing the timing;
step S104 can be executed once every preset third preset time through steps S102 to S103, wherein the timing in steps S102 to S103 can also be realized by using a timer and/or a counter;
s104: simultaneously reading the value of a minute variable a and the minute value of the travel time of the clock chip, wherein the value range of the minute variable a is an integer between 0 and 59, the minute variable executes the operation of adding 1 per minute according to the timing of a timer and/or a counter, and whether the read minute value of the travel time of the new clock chip and the value of the minute variable a have errors is judged, if not, the time correction operation is not carried out on the clock chip at this time, and if yes, the step S105 is executed;
s105: triggering a variable b to start to execute an operation of adding 1 per minute according to the timing of a timer and/or a counter;
s106: judging whether the trigger variable b reaches a set value, if not, continuing to accumulate the trigger variable, if so (namely, the timed time reaches a first preset time), executing the step S107, and resetting the value of the trigger variable b;
s107: and compensating the second preset time for the travel time of the clock chip.
The steps S105 to S107 realize that the timing is performed by using the timer and/or the counter, and when the timing reaches the first preset time, the second preset time is compensated for the travel time of the clock chip.
Preferably, in order to obtain more accurate real-time, the clock chip may be calibrated in a manner of combining online and offline, that is, the clock chip may be calibrated by using the time obtained when the device is networked, in an embodiment of the present invention, before step S1, the method further includes:
and judging whether the clock chip is in a networking state, if not, executing a step S1, if so, acquiring time information from a preset server, and timing the clock chip according to the time information acquired from the server.
In addition, referring to fig. 3, fig. 3 is a schematic diagram of a timing device of a clock chip according to an embodiment of the present invention, where the timing device includes:
the judging module 100 is configured to acquire time information determined by using a timer and/or a counter, and judge whether an error exists in the travel time of the clock chip according to the time information determined by using the timer and/or the counter;
the timing module 200 is configured to compensate the travel time of the clock chip by using the timing of the timer and/or the counter when the determining module 100 determines that there is an error in the travel time of the clock chip, and specifically, the timing module 200 is configured to perform timing by using the timer and/or the counter when the determining module determines that there is an error in the travel time of the clock chip, and perform compensation of a second preset time in the travel time of the clock chip when the timing time reaches a first preset time.
Preferably, the judging module includes:
the clock chip comprises a reading unit, a timer and a counter, wherein the reading unit is used for reading a preset minute variable value and a clock chip travel time minute value, the value range of the minute variable is an integer between 0 and 59, and the minute variable performs an operation of adding 1 per minute according to the timing of the timer and/or the counter;
and the judging unit is used for judging that an error exists in the travel time of the clock chip if the read value of the minute variable is different from the minute value of the travel time of the clock chip.
Preferably, the timing device further includes:
and the calculating module is used for calculating the time required by the error of the second preset time generated by the travel time relative to the standard time of the clock chip so as to obtain the first preset time.
Preferably, every third preset time, the judging module acquires time information determined by a timer and/or a counter, and judges whether an error exists in the travel time of the clock chip according to the time information determined by the timer and/or the counter.
Preferably, in an embodiment of the present invention, the third preset time is less than or equal to the first preset time.
For example, in an embodiment of the present invention, the second preset time is 1 second.
Preferably, in an embodiment of the present invention, the timing device further includes:
the control module is used for judging whether the clock chip is in a networking state or not, if not, the control module controls the judging module to acquire time information determined by a timer and/or a counter, judges whether an error exists in the time of the clock chip according to the time information determined by the timer and/or the counter, and if the clock chip is in the networking state, acquires the time information from a preset service end and corrects the time of the clock chip according to the time information acquired from the service end.
In addition, an embodiment of the present invention further provides an intelligent device, including:
a clock chip, for example, the clock chip may be DS 1302;
a processor (CPU);
a memory for storing processor-executable instructions;
wherein the processor is configured to:
acquiring time information determined by a timer and/or a counter, and judging whether an error exists in the travel time of the clock chip according to the time information determined by the timer and/or the counter;
and if the time of the clock chip is judged to have an error, timing by using a timer and/or a counter, and compensating the time of the clock chip for second preset time when the timed time reaches first preset time.
Preferably, the processor includes the timer and/or the counter, that is, the determination and timing of the time information can be realized by using the timer and/or the counter in the processor (CPU) of the intelligent device, without adding an additional timer and/or counter in the intelligent device.
For example, a clock chip of the smart device may be tested in advance, an error generated every 24 hours when the clock chip travels relative to a standard time is tested (may be tested multiple times and then averaged), and then a time required for every 1 second of error generated by the clock chip is calculated from the error, that is, a first preset time value is obtained, for example, the error of the clock chip DS1302 is measured to be +2.4 seconds/24 hours (i.e., every 24 hours is slower than the standard time by 2.4 seconds), so every 24 × 60/2.4 is 600 minutes, the clock chip may generate an error of about +1 second (i.e., every 600 minutes is slower than the standard time by 1 second);
adding an automatic time calibration instruction to a CPU of the intelligent device in a corresponding compiling environment, presetting two variables, namely a minute variable a (the value range of the minute variable a is an integer from 0 to 59 and circulates in the range) and a trigger variable b in the instruction, when the CPU writes the current time into the clock chip DS1302, simultaneously assigning the value of the minute bit of the current time to the minute variable a (for example, when the current time written into the clock chip DS1302 by the CPU is 22 o' clock 42 minutes, the minute variable a is also assigned to 42), the minute variable a starts to execute an operation of adding 1 per minute according to the timing of a timer and/or a counter of the CPU, and at the moment, the clock chip is independently timed by a time base provided by an external 32.768K quartz crystal oscillator;
in the use process of the intelligent device, the CPU of the intelligent device reads a minute value of the travel time of the clock chip every third preset time and compares the minute value with a minute variable a in the CPU, when the two values are not equal, the fact that the travel time of the clock chip has an error relative to the standard time is judged, the trigger variable b starts to execute an operation of adding 1 per minute according to the timing of a timer and/or a counter of the CPU, and when the value of the trigger variable b is equal to a set value (for example, if the first preset time obtained in advance is 600 minutes, the set value is 600), the CPU calibrates the clock chip for +1 second.
By the aid of the method, the timer/counter of the CPU of the intelligent device is used as a reference, and error timing is carried out every time the clock chip generates 1 second of error, so that a user can obtain more accurate time information.
The intelligent device may be an intelligent household device, such as an intelligent desk lamp, an intelligent curtain, or the like;
the intelligent device provided by the embodiment of the invention can reduce the travel time error of the clock chip by taking the timer and/or the counter of the CPU as the reference under the condition of occupying less CPU resources, thereby providing more accurate time information for users.
Those skilled in the art will readily appreciate that the above-described preferred embodiments may be freely combined, superimposed, without conflict.
It will be understood that the embodiments described above are illustrative only and not restrictive, and that various obvious and equivalent modifications and substitutions for details described herein may be made by those skilled in the art without departing from the basic principles of the invention.
Claims (16)
1. A time correction method of a clock chip is characterized by comprising the following steps:
s1: acquiring time information determined by a timer and/or a counter, and judging whether an error exists in the travel time of a clock chip according to the time information determined by the timer and/or the counter;
s2: if the travel time of the clock chip is judged to have an error, compensating the travel time of the clock chip by using the timing of a timer and/or a counter;
wherein, step S1 includes:
s11: reading a preset minute variable value and a minute value of the time of the clock chip, wherein the value range of the minute variable is an integer between 0 and 59, and the minute variable performs an operation of adding 1 per minute according to the timing of a timer and/or a counter;
s12: and if the read minute variable value is different from the minute value of the clock chip travel time, judging that the travel time of the clock chip has an error.
2. The method for timing a clock chip according to claim 1, wherein the method for compensating the travel time of the clock chip by using the timing of the timer and/or the counter comprises: and if the time of the clock chip is judged to have an error, timing by using a timer and/or a counter, and compensating the time of the clock chip for second preset time when the timed time reaches first preset time.
3. The method for timing clock chips according to claim 2, further comprising, before step S1:
and calculating the time required by the clock chip for generating the error of the second preset time relative to the standard time during the travel, thereby obtaining the first preset time.
4. The method for calibrating time of a clock chip according to claim 3, wherein the step S1 is executed once every third predetermined time.
5. The method according to claim 4, wherein the third predetermined time is less than or equal to the first predetermined time.
6. The method according to claim 2, wherein the second predetermined time is 1 second.
7. The method for timing clock chips according to any one of claims 1-6, further comprising, before step S1:
and judging whether the clock chip is in a networking state, if not, executing a step S1, if so, acquiring time information from a preset server, and timing the clock chip according to the time information acquired from the server.
8. A timing device of a clock chip is characterized by comprising:
the judging module is used for acquiring time information determined by a timer and/or a counter and judging whether an error exists in the travel time of the clock chip according to the time information determined by the timer and/or the counter;
the time correction module is used for compensating the travel time of the clock chip by using the timing of a timer and/or a counter when the judgment module judges that the travel time of the clock chip has an error;
wherein, the judging module comprises:
the clock chip comprises a reading unit, a timer and a counter, wherein the reading unit is used for reading a preset minute variable value and a clock chip travel time minute value, the value range of the minute variable is an integer between 0 and 59, and the minute variable performs an operation of adding 1 per minute according to the timing of the timer and/or the counter;
and the judging unit is used for judging that an error exists in the travel time of the clock chip if the read value of the minute variable is different from the minute value of the travel time of the clock chip.
9. The clock chip timing device according to claim 8, wherein the timing module is configured to count time by using a timer and/or a counter when the determining module determines that there is an error in the travel time of the clock chip, and compensate for a second preset time of the travel time of the clock chip when the counted time reaches a first preset time.
10. The clock chip timing apparatus of claim 9, further comprising:
and the calculating module is used for calculating the time required by the error of the second preset time generated by the travel time relative to the standard time of the clock chip so as to obtain the first preset time.
11. The device according to claim 10, wherein the determining module obtains time information determined by a timer and/or a counter every third preset time, and determines whether there is an error in the travel time of the clock chip according to the time information determined by the timer and/or the counter.
12. The clock chip timing device of claim 11, wherein the third predetermined time is less than or equal to the first predetermined time.
13. The clock chip timing device of claim 9, wherein the second predetermined time is 1 second.
14. The clock chip timing apparatus according to any one of claims 9 to 13, further comprising:
the control module is used for judging whether the clock chip is in a networking state or not, if not, the control module controls the judging module to acquire time information determined by a timer and/or a counter, judges whether an error exists in the time of the clock chip according to the time information determined by the timer and/or the counter, and if the clock chip is in the networking state, acquires the time information from a preset service end and corrects the time of the clock chip according to the time information acquired from the service end.
15. A smart device, comprising:
a clock chip;
a processor;
a memory for storing processor-executable instructions;
wherein the processor is configured to:
acquiring time information determined by a timer and/or a counter, and judging whether an error exists in the travel time of the clock chip according to the time information determined by the timer and/or the counter;
if the time of the clock chip is judged to have an error, timing by using a timer and/or a counter, and compensating for second preset time of the clock chip when the timed time reaches first preset time;
wherein the acquiring time information determined by using a timer and/or a counter, and determining whether an error exists in the travel time of the clock chip according to the time information determined by using the timer and/or the counter includes:
s11: reading a preset minute variable value and a minute value of the time of the clock chip, wherein the value range of the minute variable is an integer between 0 and 59, and the minute variable performs an operation of adding 1 per minute according to the timing of a timer and/or a counter;
s12: and if the read minute variable value is different from the minute value of the clock chip travel time, judging that the travel time of the clock chip has an error.
16. The smart device of claim 15, wherein the processor comprises the timer and/or counter.
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