CN107436729B - Control device of storage system and storage space recovery method thereof - Google Patents
Control device of storage system and storage space recovery method thereof Download PDFInfo
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- CN107436729B CN107436729B CN201610364876.3A CN201610364876A CN107436729B CN 107436729 B CN107436729 B CN 107436729B CN 201610364876 A CN201610364876 A CN 201610364876A CN 107436729 B CN107436729 B CN 107436729B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0638—Organizing or formatting or addressing of data
- G06F3/064—Management of blocks
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0662—Virtualisation aspects
- G06F3/0665—Virtualisation aspects at area level, e.g. provisioning of virtual or logical volumes
Abstract
The invention provides a control device of a storage system and a storage space recovery method thereof. The control device comprises a data read-write circuit and a judgment circuit. The judging circuit is coupled to the data reading and writing circuit. The data read-write circuit reads the data stored in the storage device. The judging circuit receives the data and judges whether the data conforms to one of a plurality of preset data forms. When the data conforms to one of the preset data forms, the judgment circuit outputs a judgment signal to the firmware unit. The firmware unit updates the logical entity mapping table according to the determination signal and directs the logical address of the data to one of the plurality of dummy data spaces of the memory unit. The dummy data spaces store the predetermined data patterns, respectively. Finally, the control device controls the storage device to clear the data.
Description
Technical Field
The present invention relates to a control device of a storage system, and more particularly, to a control device of a flash memory and a storage space recycling method thereof.
Background
In recent years, electronic devices such as smart phones, tablet computers, desktop computers, and digital cameras have rapidly grown, which has led to an increase in consumer demand for built-in storage devices of electronic devices, and Flash memories (Flash memories) are common storage devices in the electronic industry in recent years.
Flash memory is a non-volatile memory. Taking NAND Flash memory as an example, Flash memory is commonly used in memory cards, USB Flash devices (USB Flash devices), Solid State Disks (SSD), and other storage devices. The storage array provided by the flash memory is composed of a plurality of Blocks (Blocks). Each block includes a plurality of Pages (Pages). When copy or Erase (Erase) data is flashed, it is done in units of all pages in the entire block.
However, the conventional flash memory has several problems. When copying data, a conventional flash memory uses the logical address of a block to perform data transfer. In copying data, useful data is moved along with useless data (e.g., free areas of the disk). These useless data are stored in the conventional flash memory for a long time, so that the conventional flash memory needs to perform space Collection (garpage Collection) to remove the useless data. The less empty storage space in the conventional flash memory, the more times the space reclamation is performed will increase, so that the lifetime of the conventional flash memory will decrease. In addition, when the conventional flash memory writes useless data, the conventional flash memory also needs to perform Read-Modify-Write (Read-Modify-Write) operations, so that the utilization rate of the cpu increases.
Disclosure of Invention
The embodiment of the invention provides a control device of a storage system. The control device comprises a data read-write circuit and a judgment circuit. The judging circuit is coupled to the data reading and writing circuit. The data read-write circuit is used for reading at least one datum stored in the storage device. The judging circuit is used for receiving the data and judging whether the data conforms to one of a plurality of preset data forms. When the data conforms to one of the preset data forms, the judgment circuit outputs a judgment signal to the firmware unit. Then, the firmware unit updates the logical entity mapping table according to the determination signal, and directs the logical address of the data to one of the plurality of dummy data spaces of the memory unit. The dummy data spaces store the predetermined data patterns, respectively. Finally, the control device controls the storage device to clear the data.
The embodiment of the invention provides a storage space recovery method. The storage space recycling method is suitable for the control device. The storage space recycling method comprises the following steps. Step A: reading at least one datum stored in the storage device. And B: determining whether the data conforms to one of a plurality of predetermined data types. And C: when the data conforms to one of the preset data forms, a judgment signal is output to the firmware unit. Step D: the logical entity mapping table is updated according to the determination signal, and the logical address of the data is directed to one of the plurality of dummy data spaces of the memory cell. The dummy data spaces store the predetermined data patterns, respectively. Step E: and controlling the storage device to clear the data.
In summary, the control device of the storage system and the storage space recycling method thereof according to the embodiments of the present invention can clear the useless data in the storage device, thereby reducing the number of times of performing space recycling by the storage device and prolonging the life of the storage device. In addition, when the data to be read by the operating system conforms to the preset data form, the operating system can directly obtain the data from the memory unit without a storage device, so that the data reading speed of the operating system is increased.
Drawings
Fig. 1 is a schematic structural diagram of a storage system according to an embodiment of the present invention.
Fig. 2 is a schematic structural diagram of a control device according to an embodiment of the present invention.
FIG. 3 is a flowchart illustrating a storage space recycling method according to an embodiment of the present invention.
Fig. 4A is a schematic diagram of a logical entity mapping table before updating according to an embodiment of the present invention.
Fig. 4B is a schematic diagram of the updated logical entity mapping table according to the embodiment of the present invention.
Detailed Description
Referring to fig. 1, fig. 1 is a schematic structural diagram of a storage system according to an embodiment of the present invention. The storage system 1 may be installed in an electronic device such as a smart phone, a tablet computer, a desktop computer, and a digital camera. The storage system 1 includes a control device 10, a storage device 11, a memory unit 12, a firmware unit 13, and an operating system 14. The control device 10 is coupled to the storage device 11, the memory unit 12, the firmware unit 13, and the operating system 14. The memory unit 12 is coupled to an operating system 14. The firmware unit 13 is coupled to an operating system 14.
The control device 10 is used for reading the data stored in the storage device 11 and determining whether the read data conforms to one of a plurality of predetermined data types. Then, the control device 10 outputs a determination signal to the firmware unit 13 according to the determination result. On the other hand, the control device 10 may write data into the storage device 11.
Furthermore, the control device 10 can read the data stored in the storage device 11 according to the data reading request outputted by the operating system 14, and determine whether the data conforms to one of the predetermined data types. When the data read by the control device 10 conforms to one of the predetermined data formats, the control device 10 notifies the firmware unit 13 to update the internal data. Then, the control device 10 controls the storage device 11 to clear the data. On the other hand, when the operating system 14 does not output a data Read request, the control device 10 performs Background Scan Read (Background Scan Read) at intervals to Read data in the storage device 11, thereby achieving data retention. If the control device 10 does not periodically read the data in the storage device 11, the storage device 11 will slowly leak current, causing data loss. The internal structure of the control device 10 will be described in the following paragraphs with reference to fig. 2.
In the present embodiment, a first predetermined data pattern of the predetermined data patterns is binary all-0 data (i.e., hexadecimal all-0 x00 data), and a second predetermined data pattern of the predetermined data patterns is binary all-1 data (i.e., hexadecimal all-0 xFF data). For the storage system 1, the binary all-0 data and the binary all-1 data may be useless data. However, the invention is not limited thereto. In other embodiments, one skilled in the art can design other default data types, and the invention is not limited thereto.
The storage device 11 is a rewritable non-volatile memory for storing data. For example, the storage device 11 is a solid state disk. The storage device 11 may include a non-NOR type Flash memory (NAND Flash), a NOR type Flash memory (NOR Flash), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or any combination thereof, based on floating gate or charge collection techniques.
The storage device 11 is composed of a plurality of blocks, and each of the blocks includes a plurality of pages. The storage device 11 provides other devices (e.g. the control device 10) to read or write the storage medium in the storage device 11 according to the physical address, such as the address of the physical page or the address of the physical block.
It should be noted that the memory unit 12 includes a plurality of dummy data spaces, and the dummy data spaces store the predetermined data patterns respectively. For example, the first dummy data space of the memory cell 12 stores a first predetermined data pattern (i.e., binary all-0 data), and the second dummy data space of the memory cell 12 stores a second predetermined data pattern (i.e., binary all-1 data). Incidentally, in the present embodiment, the physical address of the first dummy data space is 00, and the physical address of the second dummy data space is FF.
The firmware unit 13 is used for storing a firmware. The Firmware unit 130 is, for example, a read only memory or a flash memory, and the Firmware is, for example, a Basic Input/Output System (BIOS), an Extensible Firmware Interface (EFI) BIOS, or a Unified Extensible Firmware Interface (UEFI) BIOS. In addition, the firmware unit 13 also stores a logical entity comparison table. The logical entity mapping table records the corresponding relationship between the logical address in the firmware unit 13 and the physical address in the storage device 11. The firmware unit 13 updates the logical-entity mapping table according to the determination signal provided by the control device 10, and directs the logical address of the data indicated in the determination signal to one of the dummy data spaces of the memory unit 12. The detailed update flow will be described with reference to fig. 3, 4A, and 4B in the following paragraphs.
The operating system 14 is used to operate the storage system 1. Specifically, the os 14 may output a data read request to the firmware unit 13, and the firmware unit 13 commands the control device 10 to obtain data from the storage device 11 according to the logical entity mapping table. The data read request includes the logical address of the data to be read by the operating system 14. It should be noted that, when the data to be read by the operating system 14 conforms to one of the predetermined data types, the firmware unit 13 notifies the operating system 14 to directly read the corresponding dummy data spaces in the memory unit 12, so as to directly obtain the data desired by the operating system 14.
Referring to fig. 2, fig. 2 is a schematic structural diagram of a control device according to an embodiment of the present invention. The control device 10 includes a data read/write circuit 100, a determination circuit 101, a transmission circuit 102, and a data erase circuit 103. The data read/write circuit 100 is coupled to the storage device 11, the determining circuit 101 and the transmitting circuit 102. The determining circuit 101 is coupled to the firmware unit 13, the transmitting circuit 102 and the data erasing circuit 103. The transmission circuit 102 is coupled to the memory unit 12 and the firmware unit 13. The data erasing circuit 103 is coupled to the storage device 11.
The data read/write circuit 100 is used for reading at least one data stored in the storage device 11. Specifically, the data read/write circuit 100 performs the background scan reading at intervals to read the data in the storage device 11. Alternatively, the data read/write circuit 100 reads data in the storage device 11 in response to a data read request output from the operating system 14.
The determining circuit 101 is used for receiving the data read by the data reading/writing circuit 100 and determining whether the data conforms to one of the predetermined data types. When the read data conforms to one of the predetermined data types, the determining circuit 101 outputs a determining signal to the firmware unit 13. The judgment signal includes a plurality of judgment bits. The judgment bits respectively correspond to different preset data forms. That is, the number of the determination bits is proportional to the number of the predetermined data types set by the determination circuit 101.
For example, when the determining circuit 101 determines that the data conforms to the first predetermined data format, the determining circuit 101 marks the first determination bit in the determination signal as 1. At this time, the other determination bit (e.g., the second determination bit) is marked as 0. Similarly, when the determining circuit 101 determines that the data conforms to the second predetermined data format, the determining circuit 101 marks the second determining bit in the determining signal as 1 and marks the other determining bits as 0. On the other hand, if the data does not conform to any of the predetermined data formats, the judgment circuit 101 marks all the judgment bits as 0. In other words, the firmware unit 13 can directly determine whether the data conforms to one of the predetermined data types according to the determination signal to update the logical entity comparison table.
The transmission circuit 102 is used for writing data into the memory unit 12. Specifically, when the data to be read by the operating system 14 does not conform to the predetermined data formats, the determining circuit 101 controls the data reading/writing circuit 100 to read the corresponding data from the storage device 11 according to the logical entity mapping table of the firmware unit 13. The data read/write circuit 100 outputs the read data to the transmission circuit 102. The transmission circuit 102 outputs the data read by the data read/write circuit 100 to the memory unit 12, and notifies the firmware unit 13 of the address of the data in the memory unit 12. Finally, the firmware unit 13 notifies the operating system 14 to retrieve data from the memory unit 12.
On the other hand, when the data to be read by the operating system 14 conforms to one of the predetermined data types (e.g. the first predetermined data type), the determining circuit 10 outputs the physical address 00 in the first dummy data space of the memory unit 12 to the operating system 14 according to the logical-physical mapping table. Finally, the operating system 14 directly reads the first dummy data space to obtain data corresponding to the first predetermined data format.
The data erasing circuit 103 is controlled by the determining circuit 101 for erasing the data stored in the storage device 11.
How the control device 10 recovers the storage space in the storage device 11 will be further described below. Referring to fig. 3, fig. 3 is a flowchart illustrating a storage space recycling method according to an embodiment of the invention. The storage space recycling method of fig. 3 is applied to the control device 10 of fig. 2. At this time, the operating system 14 does not output a data read request, so the control device 10 performs a background scan read. In step S301, the data read/write circuit 100 reads data in the storage device 11 and outputs the read data to the judgment circuit 101. In step S302, the determining circuit 101 determines whether the data conforms to one of the predetermined data types. If the data conforms to one of the predetermined data types, step S303 is performed. Otherwise, if the data does not conform to one of the predetermined data types, the process returns to step S301 to read the next data.
In step S303, the determining circuit 101 correspondingly marks the determining bit in the determining signal according to the predetermined data format to which the data conforms, and outputs the determining signal to the firmware unit 13. In the present embodiment, the data conforms to a first predetermined data format. Therefore, the judgment circuit 101 marks the first judgment bit in the judgment signal as 1 and outputs the judgment signal to the firmware unit 13.
In step S304, the firmware unit 13 updates the logical-to-physical mapping table according to the determination signal, so as to point the logical address of the data to one of the dummy data spaces (e.g., the first dummy data space) of the memory unit 12.
In step S305, the determining circuit 101 outputs an erase signal to the data erasing circuit 103, so that the data erasing circuit 103 controls the storage device 11 to erase the data, so as to recycle the storage space occupied by the data.
In this way, the storage space in the storage device 11 can be released. The storage device 11 can save unnecessary data transfer during the process of reforming the storage space inside, so as to prolong the life of the storage device 11. In addition, when the operating system 14 wants to read the data corresponding to the first predetermined data format, the firmware unit 13 notifies the operating system 14 to directly read the first dummy data space of the memory unit 12 according to the logical-entity mapping table. Accordingly, the operating system 14 can obtain the data from the memory unit 13 without going through the storage device 11, so that the data reading speed of the operating system 14 is increased.
It should be noted that the control device 10 also has an Error Checking and correcting (Error Checking and correcting) function, and performs an Error correction procedure on the data when reading the data. Specifically, the determining circuit 101 may perform an error correction procedure to check bits in the data during the process of determining whether the data conforms to one of the predetermined data types. If the error correction process indicates the data error, the determination circuit 101 notifies the operating system 14 of the data error, or directly controls the data erase circuit 103 to erase the data. If the error correction process indicates that the data is correct, the determining circuit 101 continues to execute steps S303 to S305 of fig. 3 to release the storage space.
Incidentally, in the present embodiment, the memory unit 12 is a dynamic random access memory. Therefore, when the storage system 1 is turned off, the predetermined data patterns stored in the memory unit 12 are cleared. When the storage system 1 is started again, the control device 10 stores the predetermined data patterns into the corresponding dummy data spaces.
How the control device 10 recovers the storage space in the storage device 11 will be described as a practical example. Referring to fig. 4A and 4B, fig. 4A is a schematic diagram of a logical entity comparison table before updating according to an embodiment of the present invention. Fig. 4B is a schematic diagram of the updated logical entity mapping table according to the embodiment of the present invention. Fig. 4A and 4B respectively show a logical entity comparison table stored in the firmware unit 13 and a corresponding relationship table between the physical address and the data content of the data in the storage device 11. At this time, the storage device 11 stores useless data (i.e., binary all-0 data and binary all-1 data).
First, the control device 10 also performs background scanning reading, and reads the data stored at the physical addresses 25, 94, 388 from the storage device 11. The determining circuit 101 determines that the physical address 25 stores binary all-0 data, the physical address 94 stores binary all-1 data, and the physical address 388 stores non-binary all-0 data and non-binary all-1 data. On the other hand, in the logical-to-physical table of FIG. 4A, physical address 25 corresponds to logical address 10, physical address 388 corresponds to logical address 11, and physical address 94 corresponds to logical address 12.
Then, the determining circuit 101 outputs a first determining signal, a second determining signal and a third determining signal to the firmware unit 13. The first determination signal is used to indicate whether the data stored at the physical address 25 conforms to the predetermined data types. The second determination signal is used to indicate whether the data stored at the physical address 94 conforms to the predetermined data types. The third determination signal is used to indicate whether the data stored at the physical address 388 conforms to the predetermined data types. Since the data stored in the physical address 25 conforms to the first predetermined data format, the judgment circuit 101 marks the first judgment bit in the first judgment signal as 1, and marks the other judgment bits as 0. On the other hand, since the data stored in the physical address 94 conforms to the second predetermined data format, the determining circuit 101 marks the second determining bit in the second determining signal as 1, and marks the other determining bits as 0. Since the data stored in the physical address 388 does not conform to the first predetermined data format and the second predetermined data format, the determining circuit 101 marks all the determining bits in the third determining signal as 0.
The firmware unit 13 receives the first, second, and third determination signals, and updates the logical entity mapping table of FIG. 4A to the logical entity mapping table of FIG. 4B according to the first, second, and third determination signals. Specifically, the firmware unit 13 updates the physical addresses corresponding to the logical addresses 10 and 12. The updated logical address 10 points to physical address 00 of the first dummy data space in memory unit 12, and the updated logical address 12 points to physical address FF of the second dummy data space in memory unit 12. Accordingly, the operating system 14 can read the binary all-0 data from the first dummy data space directly or read the binary all-1 data from the second dummy data space according to the logical-entity mapping table of FIG. 4B.
Alternatively, when the operating system 14 wants to read the data stored at the physical address 388, the determining circuit 13 controls the data reading unit 100 to read the physical address 388 according to the logical-physical mapping table provided by the firmware unit 13. The transmission circuit 102 then outputs data corresponding to the physical address 388 to the memory unit 12. Firmware unit 13 then notifies operating system 14 to read the desired data from memory unit 12. Finally, the data erasing circuit 103 controls the storage device 11 to erase the data stored in the physical addresses 25, 94, so as to release the storage space of the physical addresses 25, 94.
In summary, the control device of the storage system and the storage space recycling method thereof according to the embodiments of the present invention can clear the useless data in the storage device, thereby reducing the number of times of performing space recycling by the storage device and prolonging the life of the storage device. In addition, when the data to be read by the operating system conforms to the preset data form, the operating system can directly obtain the data from the memory unit without a storage device, so that the data reading speed of the operating system is increased.
On the other hand, the storage space recovery method provided by the embodiment of the invention is executed by the control device. Therefore, the utilization rate of the CPU of the storage system is not increased because the storage device executes space recycling.
Description of the symbols
1: storage system
10: control device
11: storage device
12: memory cell
13: firmware unit
14: operating system
100: data read-write circuit
101: judgment circuit
102: transmission circuit
103: data erasing circuit
S301 to S305: and (5) step flow.
Claims (10)
1. A control device for a storage system, comprising:
a data read-write circuit for reading at least one data stored in a storage device; and
a judging circuit, coupled to the data read-write circuit, for receiving the data and judging whether the data conforms to one of a plurality of preset data types, when the data conforms to one of the plurality of preset data types, the judging circuit outputs a judging signal to a firmware unit;
the firmware unit updates a logical entity mapping table according to the determination signal, directs a logical address of the data to one of a plurality of dummy data spaces of a memory unit, and controls the storage device to clear the data, wherein the dummy data spaces respectively store the plurality of predetermined data types.
2. The control device according to claim 1, wherein the control device further comprises:
a transmission circuit, coupled to the data read-write circuit, the judgment circuit and the memory unit, wherein when an operating system intends to read the data stored in the storage device and does not conform to the plurality of preset data formats, the judgment circuit controls the data read-write circuit to read the corresponding data in the storage device, the data read-write circuit outputs the read data to the transmission circuit, and then the transmission circuit writes the received data into the memory unit.
3. The control device as claimed in claim 2, wherein when the data to be read by the operating system conforms to one of the predetermined data types, the operating system reads the corresponding dummy data space in the memory unit according to the logical entity mapping table stored in the firmware unit to directly obtain the data.
4. The control device of claim 1, wherein the plurality of predetermined data forms include binary all-0 data and binary all-1 data.
5. The control device of claim 1, wherein the control device has an error checking and correcting function, and performs an error correction procedure on the data when reading the data.
6. A storage space recycling method is suitable for a control device and comprises the following steps:
step A: reading at least one datum stored in a storage device;
and B: determining whether the data conforms to one of a plurality of predetermined data types;
and C: when the data conforms to one of the preset data forms, outputting a judgment signal to a firmware unit;
step D: updating a logical entity mapping table according to the determination signal, and pointing a logical address of the data to one of a plurality of dummy data spaces of a memory unit, wherein the dummy data spaces respectively store the plurality of predetermined data types; and
step E: controlling the storage device to clear the data.
7. The storage space recycling method according to claim 6, wherein the space recycling method further comprises:
step F: receiving a data reading request sent by an operating system;
step G: when the data stored in the storage device to be read by the operating system does not conform to the plurality of preset data forms, controlling a data read-write circuit of the control device to read the corresponding data in the storage device, and then outputting the data read by the data read-write circuit to the memory unit;
step H: and informing the operating system to acquire the data from the memory unit.
8. The storage space recycling method of claim 7, wherein the space recycling method further comprises:
step I: when the data to be read by the operating system conforms to one of the preset data forms, the operating system reads the corresponding dummy data space in the memory unit according to the logical entity comparison table stored in the firmware unit so as to directly obtain the data.
9. The storage space recycling method of claim 6, wherein the predetermined data types include binary all-0 data and binary all-1 data.
10. The method as claimed in claim 6, wherein in step A, the control device performs an error correction procedure on the data by using an error checking and correcting function.
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| US8694563B1 (en) * | 2009-04-18 | 2014-04-08 | Hewlett-Packard Development Company, L.P. | Space recovery for thin-provisioned storage volumes |
| TWI493339B (en) * | 2012-06-13 | 2015-07-21 | Silicon Motion Inc | Data storage device and data trimming method |
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