CN107424969A - Semiconductor encapsulation device and its manufacture method - Google Patents

Semiconductor encapsulation device and its manufacture method Download PDF

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Publication number
CN107424969A
CN107424969A CN201710256395.5A CN201710256395A CN107424969A CN 107424969 A CN107424969 A CN 107424969A CN 201710256395 A CN201710256395 A CN 201710256395A CN 107424969 A CN107424969 A CN 107424969A
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Prior art keywords
layer
welding disk
conductive
conductive welding
dielectric layer
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CN201710256395.5A
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CN107424969B (en
Inventor
张简千琳
高金利
李长祺
洪志斌
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Priority claimed from US15/404,093 external-priority patent/US10600759B2/en
Priority claimed from US15/479,074 external-priority patent/US9917043B2/en
Application filed by Advanced Semiconductor Engineering Inc filed Critical Advanced Semiconductor Engineering Inc
Publication of CN107424969A publication Critical patent/CN107424969A/en
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Publication of CN107424969B publication Critical patent/CN107424969B/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

According to one or more embodiments of the present invention, semiconductor packages includes redistribution layer, conductive welding disk, dielectric layer, silicon layer and conductive contact.Redistribution layer has first surface and the second surface relative with first surface.Conductive welding disk is on the first surface of redistribution layer.Dielectric layer is located on the first surface of redistribution layer to cover the Part II of the Part I of conductive welding disk and exposure conductive welding disk.Silicon layer is located on dielectric layer.Silicon layer has groove to expose the Part II of conductive welding disk.Conductive contact is positioned on silicon layer and extended into the groove of silicon layer.

Description

Semiconductor encapsulation device and its manufacture method
Technical field
The present invention relates to semiconductor encapsulation device and its manufacture method, and more precisely, it is to be related to stack architecture Semiconductor encapsulation device and its manufacture method.
Background technology
In traditional 3 D semiconductor encapsulation, one or more semiconductor devices (such as processing unit or internal memory) can be in Interlayer conforms to substrate (ball grid array (ball grid array, BGA) substrate), the insertion silicon hole wherein in intermediary layer (through-silicon vias, TSVs) provides the electrical connection between semiconductor device and substrate.However, led to using insertion silicon Hole intermediary layer can increase the gross thickness or height of semiconductor packages.
The content of the invention
The preferential of U.S. provisional patent application cases (No.62/326,678, it applied on April 22nd, 2016) is advocated in this case Power, the content system of the U.S. provisional patent application cases are incorporated as the disclosure of this case.This case is U.S. patent application case The part of (No.15/404,093, it applied on January 11st, 2017), which is continued, case and advocates the excellent of the U.S. patent application case First weigh, the content system of the U.S. patent application case is incorporated as the disclosure of this case.
According to an embodiment of the invention, intermediary layer includes：Redistribute layer, conductive welding disk and dielectric layer.Redistribute layer With first surface and the second surface relative with first surface.Conductive welding disk is on the first surface of redistribution layer.Lead Electrical bonding pads include Part I and Part II.Dielectric layer is located on the first surface of redistribution layer to cover conductive welding disk The Part II of Part I and exposure conductive welding disk.The surface of the Part II of conductive welding disk and the surface of dielectric layer are substantial Copline.
According to an embodiment of the invention, semiconductor packages includes redistribution layer, conductive welding disk, dielectric layer, silicon layer and led Electric contact.Redistribution layer has first surface and the second surface relative with first surface.Conductive welding disk is positioned at redistribution On the first surface of layer.Dielectric layer is located on the first surface of redistribution layer to cover the Part I of conductive welding disk and exposure The Part II of conductive welding disk.Silicon layer is located on dielectric layer.Silicon layer has groove to expose the Part II of conductive welding disk.It is conductive Contact is positioned on silicon layer and extended into the groove of silicon layer.
According to an embodiment of the invention, manufacturing the method for semiconductor packages includes：Silicon carrier is provided；Dielectric layer is positioned over On the silicon carrier, the dielectric layer includes conductive welding disk；Redistribution layer is positioned on dielectric layer to be electrically connected to conduction Pad；Connect the die to redistribution layer；A part of silicon carrier and dielectric layer are removed to expose conductive welding disk；And place conductive Contact is to contact conductive welding disk.
Brief description of the drawings
Figure 1A illustrates the profile of semiconductor packages according to an embodiment of the invention.
Figure 1B illustrates the enlarged drawing of a part for Figure 1A according to an embodiment of the invention semiconductor packages.
Fig. 1 C illustrate the enlarged drawing of a part for Figure 1A according to an embodiment of the invention semiconductor packages.
Fig. 2A, 2B, 2C, 2D and 2E illustrate the method for manufacture semiconductor packages according to an embodiment of the invention.
Fig. 3 A, 3B and 3C illustrate the method for manufacture semiconductor packages according to an embodiment of the invention.
Through schema and embodiment using common reference manuals to indicate same or like component.From below in conjunction with The detailed description that accompanying drawing is made, the present invention will become apparent from.
Embodiment
Figure 1A illustrates the profile of the semiconductor packages 100 of the section Example according to the present invention.Semiconductor encapsulation device 100 include semiconductor encapsulation device 1, intermediary layer 10 and substrate 13.
According to specific purposes, substrate 13 can be flexible substrate or rigid substrate.In some embodiments, wrapped in substrate 13 Include complex conduction wiring.In some embodiments, outer contact layer also can be formed or be positioned on substrate 13.In section Example In, outer contact layer includes ball grid array (ball grid array, BGA).In other embodiments, outer contact layer includes The number of (but not limited to) such as land grid array (land grid array, LGA) or pin array (array of pin, PGA) Group.In some embodiments, outer contact layer includes soldered ball 13b, and it can be used or including lead, also can be without using lead (such as Including such as gold and the alloy or silver of tin solder and the alloy of tin solder).
Semiconductor encapsulation device 1 is positioned over the top of substrate 13.Semiconductor encapsulation device 1 include electronic building brick 11a, 11b and Packaging body 12.Each electronic building brick 11a, 11b include a plurality of semiconductor devices, such as (but not limited to) transistor, electric capacity and resistance, It is interconnected into functional circuitry to form integrated circuit by tube core interconnection structure.As those skilled in the art are apprehensible, partly lead Body tube core includes active part, and it has integrated circuit and interconnection structure.Electronic installation 11a, 11b can be any suitable integrated Circuit arrangement, it may include (but not limited to) microprocessor (single core or multi-core), memory device, core according to different embodiments Piece group, display device or application specific integrated circuit.
Packaging body 12 is disposed to cover or coats electronic building brick 11a, 11b.In some embodiments, packaging body 12 includes With filler (filler) distribution epoxy resin therein, molding compound (such as epoxy molding compound or other moldings Compound), polyimides, phenolic composite or material, the material with polysiloxanes or its combination.
Intermediary layer 10 is positioned between semiconductor encapsulation device 1 and substrate 13 to provide semiconductor encapsulation device 1 and substrate Electrical connection between 13.Electronic building brick 11a, 11b electrically connect with conductive contact (such as microbonding disk) 10b on intermediary layer 10.Intermediary Layer 10 by conductive contact (such as controlled collapse chip connection pad, controlled collapse chipconnection, C4) 10b2 electrically connects with substrate 13.In some embodiments, conductive contact 10b1,10b2 can be covered or wrapped by bottom filler Cover.
Figure 1B illustrates in Figure 1A according to an embodiment of the invention semiconductor packages 100 with the square frame A parts surrounded Enlarged drawing.Intermediary layer 10 includes redistribution layer (redistribution layer, RDL), dielectric layer 10d, 10n, silicon layer 10s, passivation layer 10g and conductive welding disk 10p.
In some embodiments, redistributing layer 10r includes stacking interlayer dielectric (interlayer Dielectrics, ILD) 10r1,10r2 and conductive layer 10m1,10m2 (such as metal level).Conductive layer 10m1,10m2 are integrated to layer Between in dielectric 10r1,10r2, and separate each other.Conductive layer 10m1,10m2 are respectively by interlayer dielectric 10r1,10r2 bag Cover or cover.Conductive layer 10m1,10m2 are electrically connected to each other by conductive interconnecting structure (such as through hole) 10v1.In section Example In, conductive layer 10m1,10m2 are melted (or heating) metal by plasma spray technology and are sprayed on surface.In section Example In, redistribution layer 10r can include any number of interlayer dielectric and conductive layer according to different embodiments.For example, again Distribution layer 10r may include N number of interlayer dielectric and conductive layer, and wherein N is integer.In some embodiments, interlayer dielectric 10r2 includes multiple openings with the conductive layer 10m2 of an exposure part.Conductive contact 10b1 is placed in redistribution layer 10r table Face (such as second surface) 10r2 is upper and extends into the partial electrical contact in opening to be exposed with conductive layer 10m2.
Conductive welding disk 10p is positioned on redistribution layer 10r surface (such as first surface) 101r, and by conductive interconnection Structure (such as through hole) 10v2 electrically connects with conductive layer 10m1.In some embodiments, conductive interconnecting structure 10v2 height is less than About 1 micron (μm).Conductive welding disk 10p include the Part I 10p1 being positioned on redistribution layer 10r surface 101r and with The Part II 10p2 of Part I 10p1 contacts.Part I 10p1 width D 1 is more than Part II 10p2 width D 2.
Dielectric layer 10d is positioned on redistribution layer 10r surface 101r to coat or cover the first of conductive welding disk 10p A part for part 10p1 and conductive welding disk 10p Part II 10p2 side wall.In some embodiments, dielectric layer 10d can Including molding compound, pre-impregnation composite material dimension (such as pre impregnated material, pre-preg), boron-phosphorosilicate glass (Borophosphosilicate Glass, BPSG), silica, silicon nitride, silicon oxynitride, undoped silicon glass (Undoped Silicate Glass, USG) or any combinations.In some embodiments, molding compound may include (but not limited to) have fill out Expect that (filler) spreads epoxy resin therein.In some embodiments, pre impregnated material may include (but not limited to) by storehouse Or the sandwich construction that a plurality of pre impregnated material/sheet materials of lamination are formed.
Dielectric layer 10n is positioned on dielectric layer 10d to coat or cover conductive welding disk 10p Part II 10p2 side wall The part not covered by dielectric layer 10d.In some embodiments, the second of dielectric layer 10n surface 10n1 and conductive welding disk 10p The part 10p2 substantial coplines of surface 10p21.In some embodiments, dielectric layer 10n and dielectric layer 10d are by different materials Material is formed.For example, dielectric layer 10n can be formed by silicon nitride, and dielectric layer 10d can be formed by silica.In other embodiment In, dielectric layer 10n and dielectric layer 10d can be made up of identical material.
Silicon layer 10s is positioned on dielectric layer 10n surface 10n1.Silicon layer 10s includes opening to expose conductive welding disk 10p's Part II 10p2 surface 10p21.In some embodiments, silicon layer 10s thickness is about 10 μm to 30 μm.
Passivation layer 10g is positioned on silicon layer 10s and extended into silicon layer 10s opening to cover conductive welding disk 10p's A Part II 10p2 surface 10p21 part.In some embodiments, passivation layer 10g includes silica, silicon nitride, oxygen Change gallium, aluminum oxide, scandium oxide, zirconium oxide, lanthana or hafnium oxide.
Conductive layer (metallurgy layer, under bump metallurgy, UBM under such as ball) 10u be positioned on passivation layer 10g and Silicon layer 10s opening is extended into contact the not passivated layer 10g of conductive welding disk 10p Part II 10p2 surface 10p21 The part of covering.For example, conductive layer 10u and passivation layer 10g side wall 10g1 and conductive welding disk 10p Part II 10p2 table Face 10p21 is contacted.
Conductive contact (such as C4 pads) 10b2 be positioned on conductive layer 10u and extend into defined by conductive layer 10u it is recessed In groove.In some embodiments, the side wall 10u1 and lower surface 10u2 for the groove that conductive contact 10b2 and conductive layer 10u is defined Electrical contact.
As described above, tradition insertion silicon hole intermediary layer can increase the gross thickness of semiconductor device.According to this exposure part Embodiment, conductive contact 10b2 and conductive contact 10b1 are mutual by conductive layer 10u, 10m1,10m2, conductive welding disk 10p and conduction Link structure 10v1,10v2 to be electrically connected to each other, to provide the electrical connection between semiconductor encapsulation device 1 and substrate 13.Therefore, partly lead The gross thickness of body encapsulation 100 will be reduced.
Fig. 1 C illustrate the portion surrounded in the semiconductor packages 100 of Figure 1A according to another embodiment of the present invention with square frame A The enlarged drawing divided.Fig. 1 C intermediary layer 10' is similar to Figure 1B intermediary layers 10, and its difference is that intermediary layer 10' does not have silicon layer 10s. In some embodiments, passivation layer 10g is positioned on dielectric layer 10n surface 10n1.Passivation layer 10g includes opening to be led with exposure An electrical bonding pads 10p Part II 10p2 surface 10p21 part.
Fig. 2A, 2B, 2C, 2D and 2E are the semiconductor structure manufacturer in different phase according to this exposure section Example The profile of method.Partial view is simplified to help the embodiment for being better understood upon this exposure.
Refering to Fig. 2A, there is provided substrate 20.Substrate 20 includes carborundum (SiC) substrate, Sapphire Substrate or silicon substrate.Interconnection Structure 21 is formed at or is positioned on the surface (such as first surface) 201 of substrate 20.In some embodiments, interconnection structure 21 can Including redistribution layer 10r, conductive welding disk 10p, dielectric layer 10d and 10n and conductive contact 10b1 as shown in Figure 1B.
Refering to Fig. 2 B, electronic building brick 22a, 22b are formed at or are positioned on interconnection structure 21 and led with interconnection structure 21 Electric contact 10b1 is electrically connected.Each electronic building brick 22a, 22b include a plurality of semiconductor devices, such as (but not limited to) transistor, electricity Appearance and resistance, it is interconnected into functional circuitry to form integrated circuit by tube core interconnection structure.As those skilled in the art can Solution, the device side of semiconductor element includes active part, and it has integrated circuit and interconnection structure.Electronic installation 22a, 22b Can be any suitable IC apparatus, its according to different embodiments may include (but not limited to) microprocessor (single core or Multi-core), memory device, chipset, display device or application specific integrated circuit.
Bottom filler 22f is through forming or covering or coat electronic building brick 22a, 22b master end and interconnection through placing The conductive contact 10b1 of structure 21.Then it can perform backflow (reflow) processing procedure.Packaging body 23 then through formed or through place with Covering or cladding electronic building brick 22a, 22b.In some embodiments, packaging body 23 includes that there is filler to spread ring therein Oxygen tree fat, molding compound (such as epoxy molding compound or other molding compounds), polyimides, phenolic composite or Material, the material with polysiloxanes or its combination.
Refering to Fig. 2 C, Fig. 2 B semiconductor structure is overturn, and by such as applying processing procedure of polishing in the surface of substrate 20 (such as Second surface) on 202 so that the substrate 20 of a part is removed to reduce the thickness of substrate 20.In some embodiments, substrate 20 The thickness of remainder be about 10 μm to 30 μm.The remainder of substrate 20 can provide it is structure-reinforced, to reduce successive process Caused structural bending.
Opening 20h is formed at one or more precalculated positions of substrate 20 to expose conductive welding disk 10p Part II 10p2 Surface 10p21.Opening 20h can be formed by etching or other suitable processing procedures.In some embodiments, conductive welding disk 10p It is completely covered by dielectric layer.Because substrate 20 and dielectric layer are made up of different materials, therefore have to carry out two kinds of different etching systems Journey can so increase manufacturing cost, time and degree of difficulty to remove substrate 20 and dielectric layer respectively.It is real according to the part of this exposure Example is applied, because conductive welding disk 10p Part II 10p2 surface 10p21 is not covered by dielectric layer 10n, as long as therefore to substrate 20 perform single etch process can exposure conductive welding disk 10p.In some embodiments, substrate 20 can be completely removed with Exposure conductive welding disk 10p Part II 10p2 surface 10p21.
Refering to Fig. 2 D, conductive layer 20u (such as UBM) is formed at or is positioned in opening 20h to contact the of conductive welding disk 10p Two part 10p2 surface 10p21.Then, conductive contact 20b (such as C4 pads) is formed at or is positioned on conductive layer 20u and prolonged Extend into opening 20h to form semiconductor encapsulation device 2.
Refering to Fig. 2 E, Fig. 2 D semiconductor structure is connected to substrate 24 (such as BGA substrates).Bottom filler through formed or Through placing with covering or coated with conductive contact 20b, reflow process then can perform.Edges of the supporting construction 24p along substrate 24 Formed or placed, to avoid semiconductor structure device 2 from being split because other objects are placed thereon.In some embodiments, scheme Processing procedure shown in 2A-2E can be described as " chip is preferential " (chip-first) processing procedure.
Fig. 3 A, 3B and 3C are that semiconductor structure manufacture method is cutd open in different phase according to this exposure section Example Face figure.Partial view is simplified to help the embodiment for being better understood upon this exposure.In some embodiments, Fig. 3 A operation continues Performed after Fig. 2A operation.
Refering to Fig. 3 A, semiconductor structure as shown in Figure 2 A is through upset, and interconnection structure 21 is positioned in substrate 30.Substrate 30 can be substrate of glass.By such as apply polishing processing procedure on the surface of substrate 20 with by a part substrate 20 remove with reduce The thickness of substrate 20.In some embodiments, the thickness of the remainder of substrate 20 is about 10 μm to 30 μm.The residue of substrate 20 Part can provide it is structure-reinforced, to reduce the structural bending caused by successive process.
Opening 20h is formed at one or more precalculated positions of substrate 20 to expose conductive welding disk 10p Part II 10p2 Surface 10p21.Opening 20h can be formed by etching or other suitable processing procedures.As noted previously, as conductive welding disk 10p Part II 10p2 surface 10p21 is not covered by dielectric layer 10n, as long as therefore performing single etch process just to substrate 20 Conductive welding disk 10p can be exposed.In some embodiments, substrate 20 can be completely removed to expose the second of conductive welding disk 10p Part 10p2 surface 10p21.
Refering to Fig. 3 B, Fig. 3 A semiconductor structure is overturn and removes substrate 30 from interconnection structure 21.Conductive layer 20u (such as UBM) is formed at or is positioned in opening 20h to contact conductive welding disk 10p Part II 10p2 surface 10p21.Connect , conductive contact 20b (such as C4 pads) is formed at or is positioned on conductive layer 20u and extended into opening 20h.
Refering to Fig. 3 C, Fig. 3 B semiconductor structure is overturn.Electronic building brick 22a, 22b are formed at or are positioned over mutual link Electrically connected on structure 21 and with the conductive contact 10b1 of interconnection structure 21.Each electronic building brick 22a, 22b fill including a plurality of semiconductors Put, such as (but not limited to) transistor, electric capacity and resistance, it is interconnected into functional circuitry to be formed by tube core interconnection structure Integrated circuit.As those skilled in the art are apprehensible, the device side of semiconductor element includes active part, and it has integrated circuit and mutually Link structure.Electronic installation 22a, 22b can be any suitable IC apparatus, and it may include according to different embodiments (but not It is limited to) microprocessor (single core or multi-core), memory device, chipset, display device or application specific integrated circuit.
Bottom filler 22f is through forming or covering or coat electronic building brick 22a, 22b master end and interconnection through placing The conductive contact 10b1 of structure 21.Then it can perform reflow process.Packaging body 23 is then through forming or covering or wrap through placing Electronic building brick 22a, 22b are covered to form semiconductor encapsulation device 2 as shown in Figure 3 C.In some embodiments, packaging body 23 wraps Include including with filler distribution epoxy resin therein, molding compound, (such as epoxy molding compound or other moldings are multiple Compound), polyimides, phenolic composite or material, the material with polysiloxanes or its combination.In some embodiments, scheme Processing procedure shown in 3A-3C can be described as " chip is last " (chip-last) processing procedure.
As used herein, term " substantial ", " substantive ", " about " and " about " is describing and consider small change Change.When being used in combination with event or situation, the term can refer to the situation that wherein event or situation clearly occur and its Middle event or situation pole is similar to situation about occurring.For example, the term can refer to less than or equal to ± 10%, such as small In or equal to ± 5%, less than or equal to ± 4%, less than or equal to ± 3%, less than or equal to ± 2%, less than or equal to ± 1%th, less than or equal to ± 0.5%, less than or equal to ± 0.1% or less than or equal to ± 0.05%.Term is " substantially flat altogether Face " can refer to two surfaces has difference within micron along same plane, as in 40 μm, in 30 μm, in 20 μm, in 10 μm or 1 μ In m.When term " substantial ", " about ", " about " are used for an event or situation, it can refer to the event or the situation is accurate Ground occurs, and is also referred to as the event or the situation close to an approximation.
If the displacement of two planes no more than 5 μm, no more than 2 μm, no more than 1 μm or no more than 0.5 μm, it is described two Surface can be considered copline or substantial copline.
" conduction " and " electrical contact " used herein can be considered the ability for transmitting electric current.Conductive material generally represents that it will not To hindering the flowing of electric current or causing the obstruction of very little.A kind of unit of conductance is Siemens/meter (S/m).Generally tool Conductive material, which has, is more than 104S/m conductance, such as at least 105S/m or at least 106S/m.The conductance of material sometimes with Temperature change and change.Especially indicated unless this exposure has, otherwise the conductance of material all measures under normal temperature.
In the narration of section Example, a component be located at another component it " on " may include the component located immediately at another On one component (such as material contact), it is also referred to as that there are other assemblies between the component and another component.
Although being described with reference to the particular embodiment of the present invention and illustrating the present invention, these descriptions and explanation are not intended to limit The present invention.Those who familiarize themselves with the technology, which should be understood that, is not departing from true spirit of the invention as defined by the appended claims And in the case of category, it can be variously modified and may replace equivalent.The explanation can be not necessarily drawn to scale.It is attributed to system Make processing procedure and tolerance limit, difference may be present between the art recurring and physical device in the present invention.Not certain illustrated may be present The other embodiment of the present invention.This specification and schema should be considered as illustrative and not restrictive.It can modify, so that Particular case, material, material composition, method or processing procedure are adapted to the target of the present invention, spirit and scope.These all modification meanings It is intended in the category of appended claims.Although method disclosed herein is with reference to the specific behaviour being performed in a specific order Work is described, it should be appreciated that can combine, segment or resequence these operations in the case where not departing from teachings of the present invention To form equivalent method.Therefore, unless special instructions herein, the order otherwise operated and packet and the limitation of non-invention.

Claims (13)

1. a kind of intermediary layer (ineterposer), it includes：
Layer (redistribution layer) is redistributed, it has first surface and relative with the first surface second Surface；
Conductive welding disk, its positioned at it is described redistribution layer the first surface on, the conductive welding disk include Part I and Part II；And
Dielectric layer, it is located on the first surface of the redistribution layer to cover the Part I of the conductive welding disk simultaneously The Part II of the exposure conductive welding disk, wherein the surface of the Part II of the conductive welding disk and the surface of the dielectric layer Substantial copline.
2. according to the intermediary layer as described in claim 1, wherein the width of the Part I of the conductive welding disk is more than the conduction The width of the Part II of pad.
3. according to the intermediary layer as described in claim 1, wherein
The dielectric layer further comprises oxide skin(coating) and nitride layer, institute of the oxide skin(coating) positioned at the redistribution layer State on first surface and the nitride layer is located in the oxide layer；And
The surface of the Part II of the conductive welding disk and the substantial copline in surface of the nitride layer.
4. according to the intermediary layer as described in claim 1, wherein the redistribution layer includes the first interconnection layer, described first interconnects Layer includes the through hole (via) electrically connected with the conductive welding disk.
5. according to the intermediary layer as described in claim 4, wherein the height of the through hole is less than 1 micron (μm).
6. according to the intermediary layer as described in claim 4, it further comprises the first conductive contact, and it is located at the redistribution layer Second surface on and electrically connect with first interconnection layer.
7. according to the intermediary layer as described in claim 1, it further comprises
Passivation layer, it is located on the surface of the dielectric layer, and the passivation layer has groove with the of the exposure conductive welding disk The surface of two parts；And
Second conductive contact, it is located on the passivation layer and extended into the groove of the passivation layer.
8. according to the intermediary layer as described in claim 7, it further comprises conductive layer, and it is located at the side wall of the groove and described On the surface of the Part II of conductive welding disk, wherein second conductive contact is by the conductive layer and conductive welding disk electricity Connection.
9. according to the intermediary layer as described in claim 1, it further comprises silicon layer, and it is located at the passivation layer and the dielectric layer Between, wherein disconnected from each other on the direction on the surface of the silicon layer dielectric layer substantially parallel with the conductive layer.
10. semiconductor packages, it includes：
Layer is redistributed, it has first surface and the second surface relative with the first surface；
Conductive welding disk, it is on the first surface of the redistribution layer；
Dielectric layer, it is located on the first surface of the redistribution layer to cover the Part I of the conductive welding disk and exposure The Part II of the conductive welding disk；And
Silicon layer, it is located on the dielectric layer, and the silicon layer has groove with the Part II of the exposure conductive welding disk；And
Conductive contact, it is positioned on the silicon layer and extended into the groove of the silicon layer.
11. according to the semiconductor packages as described in claim 10, it further includes passivation layer, and the passivation layer is located at the silicon On layer and the groove is extended into cover a part for the Part II of the side wall of the groove and the conductive welding disk.
12. according to the semiconductor packages as described in claim 10, wherein the width of the Part I of the conductive welding disk is more than institute State the width of the Part II of conductive welding disk.
13. according to the semiconductor packages as described in claim 10, wherein the surface of the Part II of the conductive welding disk with it is described The substantial copline in surface of dielectric layer.
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