CN107404353A - LiFi signal modulating methods and modulator based on FPGA - Google Patents
LiFi signal modulating methods and modulator based on FPGA Download PDFInfo
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- CN107404353A CN107404353A CN201710684482.0A CN201710684482A CN107404353A CN 107404353 A CN107404353 A CN 107404353A CN 201710684482 A CN201710684482 A CN 201710684482A CN 107404353 A CN107404353 A CN 107404353A
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- frequency
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- binary
- carrier wave
- fpga
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/11—Arrangements specific to free-space transmission, i.e. transmission through air or vacuum
- H04B10/114—Indoor or close-range type systems
- H04B10/116—Visible light communication
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/50—Transmitters
- H04B10/516—Details of coding or modulation
- H04B10/548—Phase or frequency modulation
- H04B10/556—Digital modulation, e.g. differential phase shift keying [DPSK] or frequency shift keying [FSK]
- H04B10/5563—Digital frequency modulation
Abstract
The present invention relates to a kind of LiFi signal modulating methods and modulator based on FPGA, the method comprising the steps of：8 data are inputted with frequency f0 parallel, each data is binary one or Binary Zero；The data for judging input are binary one or Binary Zero, if binary one, then gate the second carrier wave that output frequency is f2, if Binary Zero, then gate the first carrier that output frequency is f1；The carrier wave that frequency is f1 is obtained by clock drive source fc by Fractional-N frequency, and the carrier wave that frequency is f2 is obtained by clock drive source fc by 2N frequency dividings, and frequency f0 is equal with frequency f2.Modulator approach provided in an embodiment of the present invention and modulator, no matter can ensure either with or without data transfer and transmit which kind of data, light can keep normal illumination functions.
Description
Technical field
The present invention relates to modulating and demodulating signal technical field, more particularly to a kind of LiFi signal modulating methods based on FPGA
And modulator.
Background technology
Solves multi-point signal access problem using visible light wireless communication (Light Fidelity, LiFi) technology, no
Can only realize multimachine access to LAN simultaneously, and can simultaneous transmission data, there is anti-electric wire electrical interference, wireless without application
Be properly received in the case of frequency spectrum, transmitting-receiving two-end clock are nonsynchronous data, it is economic and practical the characteristics of, this is a kind of emerging more PC
The new technology of terminal accessing LAN, is in development both at home and abroad.
LiFi technologies are a kind of to modulate LED lamplight as the communication mode of data transfer carrier, can solve interior simultaneously
Lighting and the transmission of data.Because light first has to solve lighting demand, for the data to be transmitted being not handled by, when
0 signal is transmitted or transmitted in no data, can all cause lights.Therefore transmission means is accessed first with LiFi technology multiple spots
Need to treat transmission signal and encoded, no matter this pattern should ensure that either with or without data transfer and transmit which kind of number
According to light can keep normal illumination functions.
The content of the invention
It is an object of the invention to provide a kind of LiFi signal modulating methods and modulator based on FPGA.
In order to realize foregoing invention purpose, the embodiments of the invention provide following technical scheme：
A kind of LiFi signal modulating methods based on FPGA, including step：
8 data are inputted with frequency f0 parallel, each data is binary one or Binary Zero；
0/1 decision unit judges that the data of input are binary one or Binary Zero, if binary one, then gates defeated
Go out the second carrier wave that frequency is f2, if Binary Zero, then gate the first carrier that output frequency is f1；
Wherein, the carrier wave that frequency is f1 is obtained by clock drive source fc by Fractional-N frequency, and frequency is that f2 carrier wave is swashed by clock
Encourage source fc to obtain by 2N frequency dividings, frequency f0 is equal with frequency f2.
In above-mentioned modulator approach, the data of input are always Binary Zero or binary one, circuit long-time when not sending out data
And high level signal is transmitted always, no matter therefore can ensure either with or without data transfer and transmit which kind of data, light
It can keep normally illuminating.F0=f2=f1/2 and receiving terminal f0=f2=f1/2 is sent, and receives sample frequency fs=
8f0, preceding 3/8 instance sample in the T0 cycles could correctly adjudicate output.Now the T0 cycles 2/8~4/8 period midpoint,
That is f1 is in the low level section in the 1st later half cycle in cycle, and f2 is in preceding half period high level latter half high level section.
Send with reception at the 3/8T0 before and after one fs period level of error time it is constant.As being such as height to adjudicate if low as " 1 "
It can adjudicate as " 0 " so that 0/1 output judgement sampling unit can correctly judge " 1 ", " 0 " signal, and then can ensure
Also data can be properly received in the case of transmitting-receiving two-end system clock is nonsynchronous, eliminate the synchronised clock in conventional receiver circuit
Cost caused by extraction improves and technical complexity.
According to embodiments of the present invention, the above method also includes step：Using 8 data inputted parallel as a frame, in every frame
The beginning of data, increase a beginning flag position, represented with two f1 cycles, a T0 duration is sent after a frame data terminate
High level represent a frame data end mode, send with the 2FSK signals of two kinds of frequencies of f1 and f2 during data transfer.It is logical
Setting beginning flag and end mark are crossed, 8 data and other frames in each frame can be separated, avoid more frame data from being mixed in one
Rise, cause data interpretation mistake.
A kind of LiFi signal modulators based on FPGA, including：
Input buffer, 8 data are inputted with frequency f0/10 parallel for caching, each data is binary one or two
System 0；
Clock drive source, for producing the frequency of oscillation that frequency is fc；
Frequency divider, for the frequency of oscillation that frequency is fc to be carried out into Fractional-N frequency respectively, 2N is divided, and obtains that frequency is f1
One carrier wave, the second carrier wave that frequency is f2；
0/1 decision unit, for judging that the data of input are binary one or Binary Zero, if binary one, then select
The second carrier wave that logical output frequency is f2, if Binary Zero, then gate the first carrier that output frequency is f1；
8 digit counters, count frequency f0, for controlling input parallel 8 data Serial outputs single to 0/1 judgement
Member.
Compared with prior art, beneficial effects of the present invention：Modulator approach provided in an embodiment of the present invention and modulator, energy
0,1 is represented with two kinds of different frequencies, thus can transmit the letter of one of frequency in the case where transmission signal is continuously 0
Number, LED lamplight is not gone out.Pass through the setting of beginning flag position and end mark position so that receiving terminal correctly can continuously connect
Receive the 2FSK signals that modulator is sent.It can also ensure that and be properly received number in the case of transmitting-receiving two-end system clock is nonsynchronous
According to, eliminate in conventional receiver circuit synchronised clock extraction caused by cost improve and technical complexity so that utilize lamp
Light carries out data transmission being possibly realized so that data transmission security is reliable, and rapider.In addition, demodulation side of the embodiment of the present invention
Method and demodulator, realized based on FPGA, faster, reliability is high for the speed of service.
Brief description of the drawings
In order to illustrate the technical solution of the embodiments of the present invention more clearly, below by embodiment it is required use it is attached
Figure is briefly described, it will be appreciated that the following drawings illustrate only certain embodiments of the present invention, therefore be not construed as pair
The restriction of scope, for those of ordinary skill in the art, on the premise of not paying creative work, can also be according to this
A little accompanying drawings obtain other related accompanying drawings.
Fig. 1 is the structural representation of the LiFi signal modulators provided in an embodiment of the present invention based on FPGA.
Fig. 2 is the 2FSK modulated data transmitting forms of LiFi signals transmission.
Embodiment
Below in conjunction with accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Ground describes, it is clear that described embodiment is only part of the embodiment of the present invention, rather than whole embodiments.Generally exist
The component of the embodiment of the present invention described and illustrated in accompanying drawing can be configured to arrange and design with a variety of herein.Cause
This, the detailed description of the embodiments of the invention to providing in the accompanying drawings is not intended to limit claimed invention below
Scope, but it is merely representative of the selected embodiment of the present invention.Based on embodiments of the invention, those skilled in the art are not doing
The every other embodiment obtained on the premise of going out creative work, belongs to the scope of protection of the invention.
Fig. 1-2 is referred to, a kind of LiFi signal modulators based on FPGA are provided in the present embodiment, including：
Input buffer, for caching, with frequency f0,8 data of input, each data are that binary one or two enter parallel
System 0；
Clock drive source, for producing the frequency of oscillation that frequency is fc；
Frequency divider, for the frequency of oscillation that frequency is fc to be carried out into Fractional-N frequency respectively, 2N is divided, and obtains that frequency is f1
One carrier wave, the second carrier wave that frequency is f2；
0/1 decision unit, for judging that the data of input are binary one or Binary Zero, if binary one, then select
The second carrier wave that logical output frequency is f2, if Binary Zero, then gate the first carrier that output frequency is f1；
8 digit counters, count frequency f0, for controlling position number of input parallel 8 data by every data
Serial output is to 0/1 decision unit.
The input of 8 bit parallel datas can be used as by the use of 8 switch SW0~SW7 on BASYS or other development boards
D8xbitin, by the use of BTN0 button keys as the input of systematic reset signal, produce a high level when the key is pressed and reset and believe
Number.
A 8 digit counter i are designed, control the position number Serial output of 8 data inputting parallel by every data.
Count frequency should be consistent with the speed that serial mode is sent, therefore is f0.So, d8xbitin (i) is output to serial port
Fsk2xout, so that it may obtain the output that 8 bit parallel datas turn 8 bit string datas.
During SOD serial output data, first to d8xbitin (i) positions " 1 ", still " 0 " judges, if d8xbitin (i)=
" 1 ", f2, fsk2xout=f2 are gated, if d8xbitin (i)=" 0 ", gate f1, fsk2xout=f1.So that by 8 simultaneously
Row data d8xbitin is converted to 2FSK output signals fsk2xout.
Applicating example, the determination of 2FSK signal frequencies are that the key element being considered as is：The transfer rate of data, photosignal receive
The transmission characteristic and cost of circuit and realize level of technical sophistication.It is based on carrying out using inexpensive high-gain amplifier herein
The consideration of optical signal amplification, optical signal is amplified using LM324 operational amplifiers.LM324 is four with differential input
Amplifier device, within 10kHz (- 3dB), there is 100dB amplification characteristic when signal, after 10kHz amplifier characteristic drastically under
Drop, causes wave distortion, therefore, sets the carrier frequency of transmission 2FSK signals to be chosen as f1=10kHz, and carrier frequency f2=
5kHz.If necessary to higher message transmission rate, then need from the higher amplifier of gain bandwidth.
When input clock is fc=100MHz, f1=10kHz, f2=5kHz, f0=1/T0=1/200 μ s=are obtained
The square-wave signal of 5kHz frequencies to fc, it is necessary to divide.
Carrying out frequency dividing to clock fc has two methods：One kind is that clock fc continuous counters are divided, its frequency after dividing
Fn=fc/N；Another kind is by 2 to clock fcnDivided, its frequency fn=fc/2 after dividingn。
When using continuous counter frequency dividing, in transmitting terminal by setting parameter a N, N=fc/f1=100MHz/10kHz
=10000, N are any positive integer, export high level 1 with N/2 time clock cycle Tc, low electricity is exported with N/2 Tc times
Flat 0, to obtain arbitrary frequency dividing f1.As f1=10kHz, N=10000, i.e. f1=100MHz/10000=10kHz.
When the carrier wave f1 and f2 in 2FSK signals are identified receiving terminal, setting bits per inch according to transmission time T0
It is interior, it should at least receive the pulse of 2 f1 carrier waves and 1 f2 pulse, the consideration based on transmission rate, during with bits per inch according to transmission
Between the pulse of 2 f1 carrier waves is received in T0 and 1 f2 pulse is implemented, i.e. f1=10kHz, f2=5kHz, f0=1/T0=f2
=5kHz, then haveTherefore the transmission rate Rb of base band data,
2FSK signals are that a frame is transmitted with 8 when sending.In order to when continuously transmitting, allow receiving terminal correctly to distinguish
Each frame signal, in above-mentioned modulator approach, when carrying out the transmission of 2FSK signals, 8 data inputted parallel are a frame, every
The beginning of frame data, increase a beginning flag position, represented with two f1 cycles.One T0 duration of transmission after a frame end
High level represents the end of a frame.So, data frame take it is actual when degree be 10 T0 cycles.By setting data frame
Beginning flag and end mark, 8 data and other frames in each frame can be separated, avoid more frame data from mixing, make
Into data interpretation mistake.
In said modulator, the data of input are always Binary Zero or binary one, circuit long-time when not sending out data
To transmit high level signal always, no matter therefore can ensure either with or without data transfer and transmit which kind of data, light is all
Normal illumination can be kept.F0=f2=f1/2 and receiving terminal f0=f2=f1/2 is sent, and receives sample frequency fs=8f0,
Preceding 3/8 instance sample in the T0 cycles could correctly adjudicate output.Now in the midpoint of 2/8~4/8 period in T0 cycles, i.e. f1
In the low level section in the 1st later half cycle in cycle, f2 is in preceding half period high level latter half high level section.Send
With receive at the 3/8T0 before and after one fs period level of error time it is constant.As to adjudicate if low as " 1 ", if for height
Adjudicate as " 0 " so that 0/1 output judgement sampling unit can correctly judge " 1 ", " 0 " signal, and then can ensure receiving and dispatching
Also data can be properly received in the case of both ends system clock is nonsynchronous, eliminate the synchronised clock extraction in conventional receiver circuit
Caused cost improves and technical complexity.
In addition, by setting f0=f2=f1/2, transmission rate can be made to reach peak efficiency.Specifically, if circuit lath
Clock frequency caused by oscillation body device is fc, but the frequency of actual transmissions is different as needed, if the transmission rate of actual requirement
For f0, or every T0 1 data of time tranfer, this just needs fc obtaining f0 by dividing, if the multiple of frequency dividing is 2N, i.e. f0=
Fc/2N, here it is 2N frequency dividings are carried out to fc, the size for adjusting N just can adjust message transmission rate.Due to being transmitted with carrier wave f1
" 1 ", " 0 " is transmitted with carrier wave f2, when receiving terminal is received with counter, need to receive 2 one pulses when receiving f1 to counter
Just it is identified as " 1 ", receives 1 pulse when receiving f2 and just can determine that and receive digital " 0 ", therefore has T2=2T1, or f1=
2f2.Here just there is f0=f2=f1/2, due to having f0=fc/2N, f0=f2=2f1, therefore have f2=fc/2N, f1=fc/N.
Correspondingly, the modulator approach that can be realized based on said modulator, including step：
8 data are inputted with frequency f0/10 parallel, each data is binary one or Binary Zero.
The data for judging input are binary one or Binary Zero, if binary one, then it is f2's to gate output frequency
Second carrier wave, if Binary Zero, then gate the first carrier that output frequency is f1；
Wherein, the carrier wave that frequency is f1 is obtained by clock drive source fc by Fractional-N frequency, and frequency is that f2 carrier wave is swashed by clock
Encourage source fc to obtain by 2N frequency dividings, frequency f0 is equal with frequency f2.
Using 8 data inputted parallel as a frame, in the beginning of every frame data, increase a beginning flag position, with two
The f1 cycles are represented, the mode of the end of high level one frame data of expression of a T0 duration, number are sent after a frame data terminate
The 2FSK signals by 0/1 signal of input with two kinds of frequencies of f1 and f2 are sent during according to transmission.
The foregoing is only a specific embodiment of the invention, but protection scope of the present invention is not limited thereto, any
Those familiar with the art the invention discloses technical scope in, change or replacement can be readily occurred in, should all be contained
Cover within protection scope of the present invention.
Claims (2)
1. a kind of LiFi signal modulating methods based on FPGA, it is characterised in that including step：
8 data are inputted with frequency f0 parallel, each data is binary one or Binary Zero；
0/1 decision unit judges that the data of input are binary one or Binary Zero, if binary one, then gating exports frequency
Rate is f2 the second carrier wave, if Binary Zero, then gates the first carrier that output frequency is f1；
Wherein, the carrier wave that frequency is f1 is obtained by clock drive source fc by Fractional-N frequency, and frequency is f2 carrier wave by clock drive source
Fc obtains by 2N frequency dividings, and frequency f0 is equal with frequency f2.
A kind of 2. LiFi signal modulators based on FPGA, it is characterised in that including：
Input buffer, 8 data are inputted with frequency f0/10 parallel for caching, each data is binary one or binary system
0；
8 digit counters, count frequency f0, for controlling input parallel 8 data Serial outputs to 0/1 decision unit；
0/1 decision unit, for judging that the data of input are binary one or Binary Zero, if binary one, then gate defeated
Go out the second carrier wave that frequency is f2, if Binary Zero, then gate the first carrier that output frequency is f1；
Clock drive source, for producing the frequency of oscillation that frequency is fc；
Frequency divider, for the frequency of oscillation that frequency is fc to be carried out into Fractional-N frequency respectively, 2N is divided, and obtains the first load that frequency is f1
Ripple, the second carrier wave that frequency is f2.
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Cited By (2)
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| CN111800248A (en) * | 2020-05-28 | 2020-10-20 | 韦臣龙 | Communication method and device based on virtual carrier data mode |
| CN114297117A (en) * | 2021-12-28 | 2022-04-08 | 北京和利时系统工程有限公司 | Modulation method, modulation device, demodulation method and storage medium |
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