CN107403795A - A kind of power semiconductor device structure and its manufacture method - Google Patents
A kind of power semiconductor device structure and its manufacture method Download PDFInfo
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- CN107403795A CN107403795A CN201710465385.2A CN201710465385A CN107403795A CN 107403795 A CN107403795 A CN 107403795A CN 201710465385 A CN201710465385 A CN 201710465385A CN 107403795 A CN107403795 A CN 107403795A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 74
- 238000004519 manufacturing process Methods 0.000 title claims description 18
- 238000000034 method Methods 0.000 title claims description 16
- 239000000758 substrate Substances 0.000 claims abstract description 58
- 239000000919 ceramic Substances 0.000 claims description 35
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 21
- 239000011324 bead Substances 0.000 claims description 17
- 239000011521 glass Substances 0.000 claims description 9
- 238000011084 recovery Methods 0.000 claims description 8
- 239000004568 cement Substances 0.000 claims description 7
- 238000000227 grinding Methods 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 6
- 238000005498 polishing Methods 0.000 claims description 4
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- 239000003292 glue Substances 0.000 claims description 2
- 229910052573 porcelain Inorganic materials 0.000 claims 1
- 235000012431 wafers Nutrition 0.000 description 23
- 239000013078 crystal Substances 0.000 description 8
- 230000000903 blocking effect Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 5
- 238000002161 passivation Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910010293 ceramic material Inorganic materials 0.000 description 2
- 230000001419 dependent effect Effects 0.000 description 2
- 238000005553 drilling Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000005245 sintering Methods 0.000 description 2
- 238000003491 array Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000007850 degeneration Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005484 gravity Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000011031 large-scale manufacturing process Methods 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000010422 painting Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 238000009738 saturating Methods 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/06181—On opposite sides of the body
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
The present invention relates to a kind of power semiconductor device structure, including substrate and inlay chip array in a substrate, it is provided with the upper surface of the chip array and substrate for by one end of the chip in chip array top public electrode in parallel, being provided with the lower surface of the chip array and substrate for by the other end of the chip in chip array bottom public electrode in parallel.
Description
Technical field
The present invention relates to technical field of semiconductor device, more particularly, to a kind of power semiconductor device structure and its
Manufacture method.
Background technology
Power semiconductor is the core of modern power electronic system, and its cost is heavily dependent on the system of chip
Cause this.At present, the power semiconductor chips of most commercializations are all based on what monocrystalline silicon wafer crystal was manufactured.
On one wafer integrate power semiconductor chips it is more, then in production process once can mass processing power partly lead
Body device chip number is more, and the cost of every power semiconductor chips is lower.Known together based on this industry, reduce power half
Conductor device chip area and using large scale wafer be reduce power semiconductor chips manufacturing cost it is most direct two
Means.
The area of power semiconductor chips is limited by maximum operating temperature, its physics limit be present.Power is partly led
The maximum operating temperature of body device must not be higher than the intrinsic temperature of semi-conducting material in theory, when the intrinsic load in semi-conducting material
Flow sub- concentration close to device inside doping concentration when, PN junction will lose block electric current ability so that component failure.Mesh
Before, either with the majority carrier device that power metal-oxide field-effect transistor (MOSFET) is representative, or with exhausted
Edge grid bipolar transistor (IGBT) is the minority carrier devices of representative, and its chip area is all already close to its theory lower bound, no
In the presence of the space being greatly lowered.
On the other hand, although increasing always for the monocrystalline silicon wafer crystal size for manufacturing power semiconductor, speedup
Extremely slowly, the diameter wafer that industrial quarters uses in past 50 years only increases by 6% or so every year on average.Industry can use at present
Maximum a diameter of 12 inches of monocrystalline silicon wafer crystal, because material and corollary equipment are still immature, 18 inch wafers are expected to 2021
Nian Caineng comes into operation.
In summary, based on prior art development track, power semiconductor cost is by chip area and wafer size
Limitation, in the following space for being not present and significantly declining.
The content of the invention
The manufacturing cost for the power semiconductor that the present invention provides for solution above prior art is by chip area, monocrystalline
The limitation of Silicon Wafer size and irreducible technological deficiency, there is provided a kind of power semiconductor device structure.
To realize above goal of the invention, the technical scheme of use is：
A kind of power semiconductor device structure, including substrate and chip array in a substrate is inlayed, the chip array
Be provided with the upper surface of substrate for by one end of the chip in chip array top public electrode in parallel, it is described
It is provided with the lower surface of chip array and substrate for the other end of the chip in chip array bottom in parallel is public
Common electrode.
In such scheme, power semiconductor is made up of the chip array being embedded on substrate, its chi manufactured
It is very little only related to the size of substrate, and it is unrelated with the size of monocrystalline silicon wafer crystal, therefore power semiconductor device provided by the invention
Compared with prior art, its size is bigger, and manufacturing cost is lower for part structure.
Meanwhile present invention also offers the manufacture method of more than one power semiconductor device structures, its specific scheme
It is as follows：
S1. multiple holes are drilled through on ceramic substrate；
S2. it is ceramic substrate is sinter-hardened；
S3., the monocrystalline silicon bead that diameter is more than to the diameter in above-mentioned hole is embedded on ceramic substrate；
S4. in the front of ceramic substrate and reverse side coating glass glue；
S6. glass cement is made to harden at high temperature；
S7. the front to ceramic substrate is ground, polishes and make its front smooth；
S8. the reverse side to ceramic substrate is ground, polishes and make its reverse side smooth；
S9. after the grinding to ceramic positive and negative, polishing, chip is manufactured on the remaining part of monocrystalline silicon bead；
S10. metal is deposited on the upper surface of ceramic substrate and chip and is patterned, forms top public electrode；
S11. metal is deposited on the lower surface of ceramic substrate and chip and is patterned, forms bottom public electrode.
Compared with prior art, the beneficial effects of the invention are as follows：
Power semiconductor device structure provided by the invention is partly led by the integrated chip array on substrate to solve power
The large scale manufacture of body device and the technical barrier for reducing manufacturing cost.
Brief description of the drawings
Fig. 1 is the top view of the power semiconductor 100 that prior art provides and its corresponding wafer.
Fig. 2 is the sectional view for the power semiconductor 100 that prior art provides.
Fig. 3 is the top view of the power semiconductor 300 of one embodiment of the present of invention.
Fig. 4 is the sectional view of power semiconductor 300.
Fig. 5 is the equivalent circuit diagram of power semiconductor 300.
Fig. 6 is the equivalent circuit diagram of the power semiconductor 600 of an alternative embodiment of the invention.
Fig. 7 is the equivalent circuit diagram of the power semiconductor 700 of yet another embodiment of the present invention.
Fig. 8 is the front-end process flow chart of power semiconductor manufacture method provided by the invention.
Embodiment
The accompanying drawing of the present invention is used for the various aspects or feature for describing the present invention, and wherein identical reference number is used for all the time
Refer to identical device or part.In this manual, many details are elaborated to provide to the saturating of the present invention
Thorough understanding.However, it should be understood that can be in the case of these no details, or utilize other methods, component, material
Etc. realizing certain aspects of the present disclosure.
Embodiment 1
Fig. 1 is the top view of the power semiconductor 100 that prior art provides and its corresponding wafer.As illustrated,
A large amount of identical device chips equally are arranged with wafer, including device chip 100.Phase between each device chip
Dicing lane is separated with, different device chips is and is cut to open along dicing lane in encapsulation, and the size of dicing lane generally counts
Ten microns, much smaller than the size of device chip.Therefore, the device chip number that can be placed on a wafer is only dependent upon device core
The size of piece and the size of wafer.As it was noted above, the diameter maximum only 12 for the monocrystalline silicon wafer crystal that current industrial circle can use
Inch, and the area of power semiconductor chips has moved closer to theory lower bound at present.Therefore, for based single crystal silicon wafer
For the power semiconductor 100 of circle manufacture, its manufacturing cost has not declined significantly according to prior art path
Space.
Fig. 2 is the sectional view for the power semiconductor chips 100 that prior art provides.Device chip 100 is a PiN
Diode.The active area of device chip 100 is located at chip middle position, and what it is around active area is knot termination environment.Active area is by sun
Pole 221, the p with the formation Ohmic contact of anode 221+Area 211 and p+Area 211 forms the n of pn-junction-Area 212, n-The n of the lower section of area 212+
Area 213, n+The negative electrode 222 of the lower section of area 213 is formed.In silicon, doping concentration is typically higher than 1018/cm-3Region it is referred to as heavily doped
Miscellaneous area, with n+And p+Sign；And doping concentration is less than 1017/cm-3Region be referred to as lightly doped district, with n-And p-Sign, the above
It is industry general knowledge, is hereinafter not repeated to illustrate.For different types of power semiconductor chips, its active area
Structure is different, but the structure of its knot termination environment is same or similar.The effect of knot termination environment is to alleviate active area
The electric field spike at edge, and active area is kept apart with dicing lane.The knot termination environment of device chip 100 includes being covered in chip
On the passivation layer 231 on surface, vertical direction positioned at passivation layer below the 231 and in the horizontal direction field in chip outermost section
Only ring 223, positioned at passivation layer 231 and n-Dielectric layer 232, anode 221 between area 212 ride over a part on dielectric layer 232,
n-Area 212, n-The heavy doping n of the lower section of area 212+Area 213, n+The negative electrode 222 of the lower section of area 213.The effect of passivation layer 231 is to prevent
Steam, removable electric charge in environment cause device performance degeneration into chip internal.The effect of field cut-off ring 223 is preventer
Depletion region under part blocking state is along n-The upper surface of area 212 extends to chip edge because marginal position in scribing often
Many mechanical damages are produced, these mechanical damages, using as the generation center of electron-hole pair, are made once in depletion region
Into the leakage current increase under device blocking state.The part that anode 221 is ridden on dielectric layer 232 is as field plate, its effect
Alleviate p under the blocking state of device 100+The electric field spike of the final position of area 211, blocking of the lifting device chip 100 to voltage
Ability.
Fig. 3 is the top view of the power semiconductor chips 300 of one embodiment of the present of invention.Device chip 300 is
One PiN diode.Be different from device chip 100 one of device 300 is characterised by that device 300 is by multiple PiN diodes
It is formed in parallel, and these PiN diodes are all embedded in ceramic substrate 433.Ceramic substrate 433 is used as these small-sized PiN
The carrier of device, its area are not restricted by monocrystalline material growth, and the maximum substrate dimension that compatibility is only capable of by equipment is limited.
In display panel industry, for the substrate dimension that equipment can be compatible up to more than 3 meters, its area is 12 inches of monocrystalline silicon wafer crystals
More than 100 times.Therefore, if device chip 300 has identical voltage, current class and similar area with device chip 100,
The device chip 300 that can be placed on single ceramic substrate 433 is counted much larger than the device that can be placed on single monocrystalline silicon wafer crystal
Part 100 counts.For ease of processing and manufacturing, ceramic substrate 433 typically uses low-temperature co-burning ceramic material, and the material is in an initial condition
It is easy to cut out, punches, and there is the advantages of being unlikely to deform after high temperature sintering.9 are included in power semiconductor 300
PiN diodes, i.e. device chip 3001 are to device chip 3009.These PiN diodes equally arrangement form array, and
It is isolated from each other by ceramic substrate 433.
Fig. 4 is the sectional view of power semiconductor 300.Because PiN diode arrays have periodically, only provided in figure
The sectional view of ceramic material 433 between PiN diodes 3001 and PiN diodes 3002, and PiN diodes, and same
The sectional view of PiN diodes 3003 on one section does not provide.As illustrated, the sectional view and device of PiN diodes 3001,3002
Part chip 100 is similar, and its internal structure is not repeated to describe herein.Difference is the size of PiN diodes 3001,3002
Due to the limitation of original material, i.e. monocrystalline silicon bead, it is impossible to too big, in general PiN diodes 3001 and PiN diodes 3002
A diameter of 1mm to several mm, its area is usually no more than 10mm2.And the size of device chip 100 is only limited by wafer size
System, according to current class, its area can be greatly to tens mm2Even mm up to a hundred2.To reach specified current class, device chip
300 are formed in parallel by PiN diodes 3001,3002,3003,3004,3005,3006,3007,3008,3009.Such as institute in figure
Show, the anode 421 of PiN diodes 3001 and the anode of PiN diodes 3002, and the anode of other PiN diodes pass through top
Portion's public electrode 424 connects together.Top public electrode 424 is located at the upper surface of ceramic substrate 433 and PiN diodes,
Constitute the anode of power semiconductor 300.In the knot termination environment of PiN diodes 3001, top public electrode 424 is with partly leading
Body n-Area 412 is passivated floor 431 and dielectric layer 432 is kept apart, top public electrode 424 and conductive field cut-off ring 423 also by
Passivation layer 431 is kept apart, therefore pn-junction will not be caused short-circuit.In other miniature devices, above-described isolation is similar.
The negative electrode 422 of PiN diodes 3001 and the negative electrode of PiN diodes 3002, and the negative electrode of other PiN diodes are public by bottom
Common electrode 425 connects together.Bottom public electrode 425 is located at the lower surface of ceramic substrate 433 and above-mentioned PiN diodes, structure
Into the negative electrode of power semiconductor 300.Because the bottom of power semiconductor typically all only has an electrode, therefore
The bottom electrode of PiN diodes can also merge into same layer metal material with bottom public electrode, that is to say, that in figure
The negative electrode 422 and bottom public electrode 425 of PiN diodes can be same layer metal materials.
Fig. 5 is the equivalent circuit diagram of power semiconductor 300.As illustrated, power semiconductor 300 be equivalent to by
9 identical PiN diodes in parallel form.The negative electrode of all PiN diodes is connected to one by bottom common cathode 425
Rise, the anode of all PiN diodes is connected together by top public anode 424.Therefore, all PiN diode structures
Into parallel-connection structure, in forward conduction, electric current is homogeneously dispersed in each PiN diode；It is all in reverse blocking
PiN diodes are in reverse blocking state.What deserves to be explained is corresponding device chip can also be other types in Fig. 5
Rectifying device, such as Schottky diode or Schottky-PiN mixing (MPS) diode, the rectifying device pair of these types
The mode shown in the arrangement mode for the array answered, and the modes of emplacement and Fig. 4 of public electrode has no difference, and it is distinguished
The active area structure being only that inside miniature device.Also what deserves to be explained is, power semiconductor 300 provided by the invention can
It is formed in parallel with the device chip by 2 or 2 any of the above numbers, device chip number in parallel depends on power semiconductor device
The rated current size of part 300.
Fig. 6 is the equivalent circuit diagram of the power semiconductor 600 of an alternative embodiment of the invention.Power semiconductor device
Part 600 is similar with power semiconductor 300, and is formed in parallel by the device chip of multiple same types, each device core
The homonymy electrode of piece is all connected together by bottom or top public electrode.Device chip in figure is power metal-oxide field
Effect transistor (MOSFET), in general, power MOSFET grid and source electrode are located at the upper surface of device chip, and drain
Positioned at the lower surface of device chip.Therefore, in figure 3 power MOSFET grid by positioned at chip array and upper surface of base plate
Public grid connect together, 3 mini power MOSFET source electrode is by the public affairs positioned at chip array and upper surface of base plate
Common source connects together, and 3 mini power MOSFET drain electrode is by the public leakage positioned at chip array and base lower surface
Pole connects together.Although public source and public grid are all located at chip array and upper surface of base plate, the two not short circuit,
But be isolated from each other, as shown in the figure.The top view of power semiconductor 600 is similar with power semiconductor 300, simply
The device chip for forming power semiconductor 600 is different from the device chip for forming power semiconductor 300.It is worth explanation
, same connected mode applies also for other kinds of switching device, such as igbt (IGBT), three poles
Pipe, IGCT.
Fig. 7 is the equivalent circuit diagram of the power semiconductor 700 of yet another embodiment of the present invention.With power semiconductor
Unlike device 600 and power semiconductor 300, power semiconductor 700 by two distinct types of device chip,
IGBT is managed and fast recovery diode is formed in parallel.Wherein 2 IGBT pipes and 1 fast recovery diode form an elementary cell,
Power semiconductor 700 is formed in parallel by multiple such elementary cells.In elementary cell, IGBT emitter stage with it is fast extensive
The anode of multiple diode is connected by common-emitter, and IGBT colelctor electrode and the negative electrode of fast recovery diode pass through public current collection
Pole is connected, and IGBT grid is connected together by public grid.In power semiconductor 700, IGBT pipes are as switch
Device can be between domination set electrode-transmitter pole current switching, fast recovery diode can be in emitter stage as rectifying device
To current stream, the commonly known as inverse conductivity type IGBT device of this combination when voltage is higher than colelctor electrode.In general, IGBT grid
Pole and emitter stage are usually located at device upper surface, and colelctor electrode is usually located at device lower surface.Therefore, the public grid in figure and
Common-emitter should be located at chip array and the upper surface of substrate and the two is mutually isolated, and the common collector in figure should
Positioned at the lower surface of chip array and substrate.It is worthy of note that the IGBT pipes in figure can also be with other switching devices such as
Power MOSFET, triode etc. substitute, and the basic function of power semiconductor 700 is constant after replacement；Fast recovery two in figure
Pole pipe can also be substituted with other rectifying devices such as Schottky diode, MPS diodes, power semiconductor after replacement
700 basic function is constant.It is also worth noting that in power semiconductor 700, the quantity of switching device and rectifying device
Than can be adjusted according to actual conditions, its ratio can be any rational.
Fig. 8 is the front-end process flow chart of the manufacture method of power semiconductor provided by the invention.As illustrated, this
The manufacture method that invention provides is not based on traditional monocrystalline silicon wafer crystal, but is based on LTCC and monocrystalline silicon bead
's.
0001) first, on low-temperature co-fired ceramic substrate equidistant ground auger same diameter hole.The method of drilling include but
It is not limited to manual punching, machine drilling, laser boring.
0002) porose LTCC is sintered at high temperature after, solidifies ceramic substrate.The exemplary bar of sintering
Part is 900 degrees Celsius, 30 minutes.
0003) the monocrystalline silicon bead that diameter is more than to the diameter in above-mentioned hole after is embedded on above-mentioned ceramic substrate with holes.
Mosaic mode includes but is not limited to manual method or mechanical means.The typical preparation method of the monocrystalline silicon bead wherein used is：
After bulk single crystal silicon ingot melts, drip under gravity, bead is cooled into by inert gas during drippage.It is limited to cool down
Efficiency, typically only 1 millimeter to several millimeters of the diameter of bead.
0004) glass cement coated ceramic substrate front side and reverse side are used after, monocrystalline silicon bead is fixed on substrate.Wherein
Typical painting method is spin coating or spraying.After coating, baking in an oven, which may be selected, makes glass cement primary solidification.
0005) glass cement is made to harden at high temperature after.The representative condition of the process is 900 degrees Celsius, 30 minutes.
0006) positive grinding, polishing are carried out to whole substrate after.The top of monocrystalline silicon bead is gone after grinding and polishing
Remove, the upper surface of remainder is circle, while glass cement is also partly removed, the upper surface of remaining glass cement and bead
Upper surface is in same plane.
0007) grinding back surface is carried out to whole substrate after.The bottom of monocrystalline silicon bead is removed after grinding, remainder
Lower surface be circle, while ceramic substrate is also partly removed, the lower surface of remaining ceramic substrate and the lower surface of bead
In same plane.After this step, the remaining part of bead is sheet.
0008) device chip is manufactured after on the remaining silicon wafer of bead after grinding.This process with traditional silicon
It is identical that power semiconductor chips are manufactured on wafer.
0009) metal and graphical, formation top public electrode are deposited after in the upper surface of ceramic substrate and chip.
0010) metal is deposited in the lower surface of ceramic substrate and chip after, forms bottom public electrode.In fact, by
In the bottom of power semiconductor chips, typically only an electrode, this step can also be omitted, because in manufacture device core
The electrode of each device chip bottom is originally attached to together during piece.
Obviously, the above embodiment of the present invention is only intended to clearly illustrate example of the present invention, and is not pair
The restriction of embodiments of the present invention.For those of ordinary skill in the field, may be used also on the basis of the above description
To make other changes in different forms.There is no necessity and possibility to exhaust all the enbodiments.It is all this
All any modification, equivalent and improvement made within the spirit and principle of invention etc., should be included in the claims in the present invention
Protection domain within.
Claims (10)
- A kind of 1. power semiconductor device structure, it is characterised in that：Including substrate and chip array in a substrate is inlayed, it is described It is provided with the upper surface of chip array and substrate for one end of the chip in chip array top in parallel is public Electrode, it is provided with the lower surface of the chip array and substrate for the other end of the chip in the chip array is in parallel Bottom public electrode.
- 2. power semiconductor device structure according to claim 1, it is characterised in that：Chip in the chip array is Rectifying device, its one end are connected with top public electrode, and the other end is connected with bottom public electrode.
- 3. power semiconductor device structure according to claim 2, it is characterised in that：The rectifying device is the poles of PiN bis- Pipe, Schottky diode or MPS diodes, anode and the top of the PiN diodes, Schottky diode or MPS diodes Public electrode connects；The negative electrode of PiN diodes, Schottky diode or MPS diodes is connected with bottom public electrode.
- 4. power semiconductor device structure according to claim 1, it is characterised in that：Chip in the chip array is Switching device, the switching device are power MOSFET tube, IGBT pipes, triode or IGCT；It is described to be arranged on chip array Include the first public electrode and the second public electrode, the grid of power MOSFET tube with the top public electrode on upper surface of base plate Pole, the emitter stage of IGBT pipes, the emitter stage of the emitter stage of triode or IGCT are connected with the first public electrode, power MOSFET The source electrode of pipe, the base stage of IGBT pipes, the base stage of the base stage of triode or IGCT are connected with the second public electrode, power MOSFET The drain electrode of pipe, the colelctor electrode of IGBT pipes, the colelctor electrode of the colelctor electrode of triode or IGCT are connected with bottom public electrode.
- 5. power semiconductor device structure according to claim 1, it is characterised in that：Chip bag in the chip array Include IGBT pipes and fast recovery diode；The top public electrode being arranged on chip array and upper surface of base plate includes first Public electrode and the second public electrode；The emitter stage of the IGBT pipes and the anode of fast recovery diode pass through the first public electrode It is attached, the colelctor electrode of the IGBT pipes and the negative electrode of fast recovery diode are connected by bottom public electrode, the IGBT The base stage of pipe is connected with the second public electrode.
- 6. power semiconductor device structure according to claim 1, it is characterised in that：It is flat that the area of the chip is less than 10 Square millimeter.
- 7. according to the power semiconductor device structure described in any one of claim 1~6, it is characterised in that：The substrate is pottery Porcelain substrate.
- 8. power semiconductor device structure according to claim 7, it is characterised in that：The ceramic substrate is low temperature co-fired Ceramic substrate.
- 9. power semiconductor device structure according to claim 7, it is characterised in that：Chip in chip array is in substrate Upper equidistantly arrangement.
- A kind of 10. manufacture method of any one of claim 1~9 power semiconductor device structure, it is characterised in that：Including Following steps：S1. multiple holes are drilled through on ceramic substrate；S2. it is ceramic substrate is sinter-hardened；S3., the monocrystalline silicon bead that diameter is more than to the diameter in above-mentioned hole is embedded on ceramic substrate；S4. in the front of ceramic substrate and reverse side coating glass glue；S6. glass cement is made to harden at high temperature；S7. the front to ceramic substrate is ground, polishes and make its front smooth；S8. the reverse side to ceramic substrate is ground, polishes and make its reverse side smooth；S9. after the grinding to ceramic positive and negative, polishing, chip is manufactured on the remaining part of monocrystalline silicon bead；S10. metal is deposited on the upper surface of ceramic substrate and chip and is patterned, forms top public electrode；S11. metal is deposited on the lower surface of ceramic substrate and chip and is patterned, forms bottom public electrode.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114334897A (en) * | 2022-03-15 | 2022-04-12 | 合肥阿基米德电子科技有限公司 | IGBT module packaging structure |
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| CN103650318A (en) * | 2011-06-24 | 2014-03-19 | 日立汽车系统株式会社 | Power semiconductor module and electric power conversion device using same |
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| CN101136395A (en) * | 2006-08-30 | 2008-03-05 | 株式会社电装 | Power electronic packing member including two pieces of substrate with multiple electronic elements |
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