CN107401461B - External engine speed limiter - Google Patents
External engine speed limiter Download PDFInfo
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- CN107401461B CN107401461B CN201710876002.0A CN201710876002A CN107401461B CN 107401461 B CN107401461 B CN 107401461B CN 201710876002 A CN201710876002 A CN 201710876002A CN 107401461 B CN107401461 B CN 107401461B
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- F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
- F02—COMBUSTION ENGINES; HOT-GAS OR COMBUSTION-PRODUCT ENGINE PLANTS
- F02D—CONTROLLING COMBUSTION ENGINES
- F02D31/00—Use of speed-sensing governors to control combustion engines, not otherwise provided for
- F02D31/001—Electric control of rotation speed
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- F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
- F02—COMBUSTION ENGINES; HOT-GAS OR COMBUSTION-PRODUCT ENGINE PLANTS
- F02D—CONTROLLING COMBUSTION ENGINES
- F02D41/00—Electrical control of supply of combustible mixture or its constituents
- F02D41/02—Circuit arrangements for generating control signals
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- F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
- F02—COMBUSTION ENGINES; HOT-GAS OR COMBUSTION-PRODUCT ENGINE PLANTS
- F02D—CONTROLLING COMBUSTION ENGINES
- F02D2200/00—Input parameters for engine control
- F02D2200/02—Input parameters for engine control the parameters being related to the engine
- F02D2200/10—Parameters related to the engine output, e.g. engine torque or engine speed
- F02D2200/101—Engine speed
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- F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
- F02—COMBUSTION ENGINES; HOT-GAS OR COMBUSTION-PRODUCT ENGINE PLANTS
- F02D—CONTROLLING COMBUSTION ENGINES
- F02D2200/00—Input parameters for engine control
- F02D2200/60—Input parameters for engine control said parameters being related to the driver demands or status
- F02D2200/602—Pedal position
Abstract
The invention discloses an external engine speed limiter which comprises an accelerator pedal used for inputting signals and a controller used for controlling the engine speed, wherein a speed limiter used for limiting the engine speed is connected between the accelerator pedal and the controller, and a speed limiting circuit is arranged in the speed limiter. The structure of the invention is convenient to disassemble and assemble, reduces the use cost and has strong universality by arranging the external speed limiter which is connected between the accelerator pedal and the controller and is used for limiting the rotating speed of the engine; the top of the input signal is cut off by moving the input signal up and down by a fixed value, so that the amplitude of the input signal is limited, and meanwhile, the function of speed limitation is not realized by conducting and controlling the optocoupler, so that the use requirements of people are met; the purpose of adjusting and controlling the maximum rotating speed given signal of the engine is achieved by adjusting the size of the adjustable potentiometer, meanwhile, the required rotating speed value can be adjusted and locked on site, and the adjustment is quick, convenient and fast, and the use is convenient.
Description
Technical Field
The invention relates to the technical field of engines, in particular to an external engine speed limiter.
Background
With the continuous improvement of environmental protection standards and requirements, internal combustion engines used by domestic engineering machinery are upgraded to three-stage emission, the three-stage emission engines completely adopt an electronic injection control technology to meet the environmental protection requirements, and the engines are provided with own electronic controllers and can control the actual output rotating speed of the engines through rotating speed instruction signals input by electronic accelerator pedals.
When a certain domestic special user uses the engineering vehicle, the vehicle speed is clearly limited due to strict safety standard requirements of a factory, the product of an engineering vehicle manufacturer is required, the vehicle speed limited in the safety standard cannot be exceeded when the engineering vehicle is used, a new technical requirement is provided for the engineering vehicle manufacturer, and if the vehicle speed limitation is realized, the requirements of limiting the gear of a gearbox and limiting the rotating speed of an engine must be simultaneously met, so that the aim of limiting the vehicle speed of the user can be perfectly realized.
Generally, according to the technical scheme of limiting the vehicle speed, firstly, gear limitation is carried out on a gearbox, the gear of the gearbox required by speed limitation needs to be calculated, and the gear limitation of the gearbox can be realized by directly replacing a gear shifting handle or refreshing a gear shifting program of a gearbox controller and the like; secondly, the rotating speed of the engine is dynamically limited according to the feedback of the actual vehicle speed, an engine manufacturer is required to compile a special engine speed limit control program and brush the program into an engine controller to realize the rotating speed limitation of the engine, the technical communication and the connection realization process are complicated, and the engine is changed from a general standard type to a special customized type, so that the use cost is increased, and the use requirements of people cannot be met.
Disclosure of Invention
The invention aims to provide an external engine speed limiter to solve the problems in the background technology.
In order to achieve the purpose, the invention provides the following technical scheme:
an external engine rotating speed limiter comprises an accelerator pedal used for inputting signals and a controller used for controlling the rotating speed of an engine, wherein a speed limiter used for limiting the rotating speed of the engine is connected between the accelerator pedal and the controller, a speed limiting circuit is arranged in the speed limiter, and the speed limiting circuit comprises a single speed limiting circuit used for processing single signal input and a synchronous speed limiting circuit used for processing double signal input;
the single speed limiting circuit comprises a single-input addition circuit for parallel upward shifting input signals, a single-input subtraction circuit for parallel downward shifting input signals and an output voltage follower circuit for increasing output impedance, which are connected in sequence;
the synchronous speed limiting circuit comprises an operational amplification circuit for amplifying an input signal, a double-input addition circuit for parallelly shifting up the input signal, a double-input subtraction circuit for parallelly shifting down the input signal and a division and voltage following circuit for outputting a speed limiting signal, which are connected in sequence;
the single-input addition circuit and the single-input subtraction circuit of the single speed limiting circuit are both connected with a speed limiting regulation circuit with a speed limiting enabling control unit, and the single-input addition circuit and the single-input subtraction circuit which are connected in series are connected with the double-input addition circuit and the double-input subtraction circuit which are connected in series.
As a further scheme of the invention: the speed-limiting regulation and control circuit comprises a speed-limiting enabling control unit consisting of a resistor R11 and a control optocoupler U3 connected with the resistor R11 in series, and an up-down movement regulation and control unit consisting of an adjustable potentiometer RT1 and a resistor R12 which are connected with the resistor R10 in series in sequence and an operational amplifier U2B connected between the adjustable potentiometer RT1 and the resistor R12.
As a further scheme of the invention: the single-input addition circuit comprises an operational amplifier U1A, a resistor R1 with equal resistance, a resistor R2, a resistor R4 and a resistor R8; the resistor R1 is connected with the resistor R2 in series, and a node between the resistor R1 and the resistor R2 is connected with the reverse input end of the operational amplifier U1A; one ends of the resistor R4 and the resistor R8 are connected with the homodromous input end of the operational amplifier U1A, and the other end of the resistor R4 is connected with an IN1 signal input by an accelerator pedal.
As a further scheme of the invention: the single-input subtraction circuit comprises an operational amplifier U1B, a resistor R3 with equal resistance, a resistor R6, a resistor R7, a resistor R9 and a capacitor C1; one end of the resistor R3 is connected with the output end of the single-input addition circuit, the other end of the resistor R3 is connected with the resistor R6 with one end grounded, and the resistor R3 and the resistor R6 are both connected with the homodromous input end of the operational amplifier U1B; one end of each of the resistor R7 and the resistor R9 is connected with the reverse input end of the operational amplifier U1B; one end of the capacitor C1 is grounded, and the other end of the capacitor C1 is connected with the power supply input end of the operational amplifier U1B.
As a further scheme of the invention: the output voltage follower circuit comprises an operational amplifier U2A for outputting an OUT1 signal and a capacitor C2 connected with the operational amplifier U2A; and the homodromous input end of the operational amplifier U2A is connected with the output end of the single-input subtraction circuit.
As a further scheme of the invention: the operational amplification circuit comprises an operational amplifier U4B, a resistor R15, a resistor R16 and a resistor R20 which have the same resistance value, and a capacitor C3 connected with the power supply input end of the operational amplifier U4B; one end of the resistor R15 is grounded, the other end of the resistor R15 is connected with the resistor R16 in series, and a node between the resistor R15 and the resistor R16 is connected with the reverse input end of the operational amplifier U4B; one end of the resistor R20 is connected with an accelerator pedal input IN2 signal, and the other end of the resistor R is connected with the homodromous input end of the operational amplifier U4B.
As a further scheme of the invention: the dual-input addition circuit comprises an operational amplifier U4A, a resistor R13 with equal resistance, a resistor R14, a resistor R18 and a resistor R24; the resistor R13 is connected with the resistor R14 in series, and a node between the resistor R1 and the resistor R2 is connected with the reverse input end of the operational amplifier U4A; one ends of the resistor R18 and the resistor R24 are connected with the same-direction input end of the operational amplifier U4A, and the other end of the resistor R24 is connected with the resistor R8 of the single-input addition circuit, the resistor R9 of the single-input subtraction circuit and the output end of the operational amplifier U2B of the upward and downward shifting regulation and control unit.
As a further scheme of the invention: the dual-input subtraction circuit comprises an operational amplifier U5A, a resistor R17 with equal resistance, a resistor R21, a resistor R23 and a resistor R25; one end of the resistor R17 is connected with the output end of the double-input addition circuit, the other end of the resistor R17 is connected with the resistor R21 with one end grounded, and the resistor R17 and the resistor R21 are both connected with the homodromous input end of the operational amplifier U1B; one ends of the resistor R23 and the resistor R25 are connected with the reverse input end of the operational amplifier U5A, and the other end of the resistor R25 is connected with a resistor R24 of the double-input addition circuit.
As a further scheme of the invention: the division and voltage following circuit comprises an operational amplifier U5B, a resistor R19 with equal resistance, a resistor R22 and a capacitor C4; one end of the resistor R22 is grounded, the other end of the resistor R22 is connected with the resistor R19, and one end of the resistor R19 is connected with the output end of the double-input subtraction circuit operational amplifier U5A; and the capacitor C4 is connected with the power supply input end of the operational amplifier U5A.
Compared with the prior art, the invention has the beneficial effects that: the structure of the invention is convenient to disassemble and assemble and can be suitable for various engines by arranging the external speed limiter which is connected between the accelerator pedal and the controller and used for limiting the rotating speed of the engine, thereby avoiding the special manufacture of the engine with the requirement on the speed of the engine, reducing the use cost and having strong universality; the single speed limiting circuit, the synchronous speed limiting circuit and the speed limiting regulation and control circuit can process single signals and double signals input by an accelerator pedal, the speed limiting function is realized by the non-conduction control optocoupler, the top of the input signal is cut off by moving the input signal up and down by a fixed value, the amplitude of the input signal is limited, the speed limiting control function is realized, meanwhile, the non-speed limiting function can be realized by the conduction control optocoupler, and the use requirements of people are met; when the speed limit control function is realized, the amplitude of the signal can be controlled at a required voltage point by adjusting the size of the set adjustable potentiometer, the purpose of adjusting and controlling the maximum rotating speed given signal of the engine is achieved, the limitation of the rotating speed value is realized, meanwhile, the required rotating speed value can be adjusted and locked on site, the adjustment is quick and convenient, and the use is convenient; the output voltage following circuit adopts a voltage follower connection method, so that the output impedance can be infinite, the load capacity of the output voltage following circuit is enhanced, and the using effect is good.
Drawings
Fig. 1 is a diagram showing an overall control structure of the present invention.
Fig. 2 is an overall connection diagram of the present invention.
Fig. 3 is a circuit diagram of the speed limit circuit of the present invention.
FIG. 4 is a graphical illustration of the signal input to the accelerator pedal of the present invention.
Fig. 5 is a signal processing graph of a single input adder circuit according to the present invention.
FIG. 6 is a signal processing graph of a single input subtraction circuit according to the present invention.
FIG. 7 is a graphical representation of the accelerator pedal signal output of the present invention.
FIG. 8 is a signal processing graph of the operational amplifier circuit according to the present invention.
Fig. 9 is a signal processing graph of a dual input adder circuit of the present invention.
FIG. 10 is a signal processing graph of the dual input subtraction circuit of the present invention.
FIG. 11 is a signal processing diagram of a division and voltage follower circuit according to the present invention.
In the figure: the device comprises a speed limiter 1, an accelerator pedal 2, a controller 3, a single-input addition circuit 4, a single-input subtraction circuit 5, an output voltage following circuit 6, an operational amplification circuit 7, a double-input addition circuit 8, a double-input subtraction circuit 9, a division and voltage following circuit 10, a speed limit enable control unit 11 and a speed limit regulation and control circuit 12.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1-11, in an embodiment of the present invention, an external engine speed limiter includes an accelerator pedal 2 for inputting a signal and a controller 3 for controlling an engine speed, a speed limiter 1 for limiting an engine speed is connected between the accelerator pedal 2 and the controller 3, a speed limiting circuit is disposed inside the speed limiter 1, and the speed limiting circuit includes a single speed limiting circuit for processing a single signal input and a synchronous speed limiting circuit for processing a double signal input;
the single speed limiting circuit comprises a single input adding circuit 4 for parallelly shifting up input signals, a single input subtracting circuit 5 for parallelly shifting down the input signals and an output voltage following circuit 6 for increasing output impedance, which are connected in sequence, wherein the single input adding circuit 4 comprises an operational amplifier U1A, a resistor R1, a resistor R2, a resistor R4 and a resistor R8 which are equal in resistance, the resistor R1 and the resistor R2 are connected in series, and a node between the resistor R1 and the resistor R2 is connected with the reverse input end of the operational amplifier U1A; one end of each of the resistor R4 and the resistor R8 is connected with the homodromous input end of the operational amplifier U1A, and the other end of the resistor R4 is connected with an IN1 signal input by an accelerator pedal; the single-input subtraction circuit 5 comprises an operational amplifier U1B, a resistor R3, a resistor R6, a resistor R7, a resistor R9 and a capacitor C1, wherein the resistance values of the resistor R3 are equal, one end of the resistor R3 is connected with the output end of the single-input addition circuit 4, the other end of the resistor R3 is connected with the resistor R6, one end of the resistor R6 is grounded, the resistor R3 and the resistor R6 are both connected with the homodromous input end of the operational amplifier U1B, and one ends of the resistor R7 and the resistor R9 are both connected with the reverse input end of the operational amplifier U1B; one end of the capacitor C1 is grounded, and the other end of the capacitor C1 is connected with the power supply input end of the operational amplifier U1B; the output voltage follower circuit 6 comprises an operational amplifier U2A for outputting an OUT1 signal and a capacitor C2 connected with the operational amplifier U2A; the homodromous input end of the operational amplifier U2A is connected with the output end of the single-input subtraction circuit (5);
the synchronous speed-limiting circuit comprises an operational amplifier circuit 7 for amplifying an input signal, a double-input addition circuit 8 for parallelly shifting up the input signal, a double-input subtraction circuit 9 for parallelly shifting down the input signal and a division and voltage follower circuit 10 for outputting a speed-limiting signal which are connected in sequence; the operational amplification circuit 7 comprises an operational amplifier U4B, a resistor R15, a resistor R16, a resistor R20 and a capacitor C3, wherein the resistors R15, the resistor R16 and the resistor R20 are equal in resistance, the capacitor C3 is connected with the power input end of the operational amplifier U4B, one end of the resistor R15 is grounded, the other end of the resistor R15 is connected with the resistor R16 in series, and a node between the resistor R15 and the resistor R16 is connected with the reverse input end of the operational amplifier U4B; one end of the resistor R20 is connected with an accelerator pedal input IN2 signal, and the other end of the resistor R is connected with the homodromous input end of the operational amplifier U4B; the dual-input addition circuit 8 comprises an operational amplifier U4A, a resistor R13, a resistor R14, a resistor R18 and a resistor R24 which are equal in resistance, the resistor R13 is connected with the resistor R14 in series, a node between the resistor R1 and the resistor R2 is connected with the reverse input end of the operational amplifier U4A, one ends of the resistor R18 and the resistor R24 are connected with the same-direction input end of the operational amplifier U4A, and the other end of the resistor R24 is connected with the resistor R8 of the single-input addition circuit 4, the resistor R9 of the single-input subtraction circuit 5 and the output end of an operational amplifier U2B of the upward and downward movement regulating and controlling unit; the dual-input subtraction circuit 9 comprises an operational amplifier U5A, a resistor R17, a resistor R21, a resistor R23 and a resistor R25, wherein the resistors R17 are equal in resistance, one end of the resistor R17 is connected with the output end of the dual-input addition circuit 8, the other end of the resistor R17 is connected with the resistor R21, one end of the resistor R21 is grounded, the resistor R17 and the resistor R21 are both connected with the homodromous input end of the operational amplifier U1B, one ends of the resistor R23 and the resistor R25 are both connected with the reverse input end of the operational amplifier U5A, and the other end of the resistor R25 is connected with a resistor R24 of the dual-input addition circuit 8; the division and voltage following circuit 10 comprises an operational amplifier U5B, a resistor R19 with equal resistance, a resistor R22 and a capacitor C4, wherein one end of the resistor R22 is grounded, the other end of the resistor R22 is connected with the resistor R19, one end of the resistor R19 is connected with the output end of the operational amplifier U5A of the dual-input subtraction circuit 9, and the capacitor C4 is connected with the power supply input end of the operational amplifier U5A;
the speed limiting control circuit 12 comprises a speed limiting enable control unit 11, a speed limiting enable control unit 11 and an up-down control unit, wherein the speed limiting enable control unit 11 is composed of a resistor R11, a control optocoupler U3 connected with the resistor R11 in series, and an adjustable potentiometer RT1 and a resistor R12 which are connected in series in sequence through a resistor R10, and an operational amplifier U2B is connected between the adjustable potentiometer RT1 and the resistor R12.
The model of the operational amplifier adopted by the invention is TLC2262, the operation is stable, when the device is used, the speed limiter 1 for limiting the rotating speed of the engine is connected between the accelerator pedal 2 for inputting signals and the controller 3 for controlling the rotating speed of the engine, the device is convenient and quick to install, the device is suitable for various engines, the problem that one type of engine needs to be specially manufactured when the speed is limited is avoided, the use cost is reduced, and the universality is strong. The single signal IN1 is input through an accelerator pedal 2 of an engine, when the input single signal IN1 passes through a single input addition circuit 4, one end of a resistor R4 is connected with the accelerator pedal input IN1 signal, the single input addition circuit 4 consisting of an operational amplifier U1A, a resistor R1 with equal resistance, a resistor R2, a resistor R4 and a resistor R8 parallelly shifts up the single signal IN1 input by the accelerator pedal 2 by a fixed value, at the moment, the top of the output signal is cut off, and then the single input subtraction circuit 5 formed by connecting an operational amplifier U1B, a resistor R3 with equal resistance, a resistor R6, a resistor R7, a resistor R9 and a capacitor C1 parallelly shifts down the signal output by the single input addition circuit 4 by a fixed value, the parallel downward shift value is the same as the parallel upward shift value of the single input addition circuit 4, the signal is overlapped with the signal line of the single signal IN1 input by the accelerator pedal 2 of the original engine after being shifted downward, but the top of the signal line is cut off by a certain amount, the amplitude value processed by the single input addition circuit 4 and the single input subtraction circuit 5 can be controlled by adjusting the fixed value of the upward and downward movement of the single input addition circuit 4 and the single input subtraction circuit 5, the processed single signal IN1 input by the accelerator pedal 2 is output by the output voltage follower circuit 6, the OUT1 signal is output by the operational amplifier U2A of the output voltage follower circuit 6, finally, the output impedance can be infinitely large by the circuit 6 adopting the voltage follower connection method, and the load capacity of the output voltage follower circuit 6 is enhanced.
When the accelerator pedal 2 of the engine inputs double signals, the other synchronous pedal input signal IN2 firstly passes through the operational amplifier circuit 7, the operational amplifier circuit 7 which is composed of an operational amplifier U4B, a resistor R15, a resistor R16, a resistor R20 and a capacitor C3 connected with the power input end of the operational amplifier U4B amplifies the input signal IN2 by two times, then the input signal IN2 sequentially passes through the double-input addition circuit 8 and the double-input subtraction circuit 9, the input signal IN2 passes through the double-input addition circuit 8 and the double-input subtraction circuit 9 and is identical to the input single signal IN1 IN principle through the single-input addition circuit 4 and the single-input subtraction circuit 5, after the input signal IN2 is subjected to the same up-shifting and down-shifting, the input signal IN2 is reduced by two times through a division circuit of equal-voltage division, and then the input signal IN2 is output through a division and voltage following circuit 10 which is formed by connecting the operational amplifier U5B, the resistor R19, the resistor R22 and the capacitor C4 which are equal IN resistance.
In the working process of the speed limiting circuit, a speed limiting enabling control unit 11 consisting of a resistor R11 and a control optocoupler U3 connected with the resistor R11 in series works, when a diode connected with a 24V positive power supply enables the control optocoupler U3 to be conducted, an output signal of the control optocoupler U3 is close to zero, so that an upward moving fixed value of a double-input addition circuit 8 and a single-input addition circuit 4 and a downward moving fixed value of a double-input subtraction circuit 9 and a single-input subtraction circuit 5 are close to zero, the top of an output signal of an input signal after being processed cannot be cut off, and the function of speed limitation control is realized; when the diode connected with the 24V anode power supply enables the control optocoupler U3 to be non-conductive, the upward-shifting fixed values of the double-input addition circuit 8 and the single-input addition circuit 4 and the downward-shifting fixed values of the double-input subtraction circuit 9 and the single-input subtraction circuit 5 can be adjusted according to the use requirement, the top of the output signal of the processed input signal is cut off according to the use requirement, and the speed-limiting control function is realized. Meanwhile, the resistor R10 is sequentially connected with the adjustable potentiometer RT1 and the resistor R12 in series, the upward and downward movement regulating and controlling unit consisting of the operational amplifier U2B is connected between the adjustable potentiometer RT1 and the resistor R12 in an access mode, the amplitude of an output signal obtained after an input signal is processed can be controlled at a required voltage point by regulating the size of the adjustable potentiometer RT1, the purpose of regulating and controlling a maximum rotating speed given signal of an engine is achieved, the limitation of a rotating speed value is achieved, the required rotating speed value can be regulated and locked on site, the regulation is fast and convenient, and the use is convenient.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.
Claims (9)
1. An external engine speed governor comprising an accelerator pedal (2) for inputting a signal and a controller (3) for controlling the engine speed, characterized in that: a speed limiter (1) used for limiting the rotating speed of an engine is connected between the accelerator pedal (2) and the controller (3), a speed limiting circuit is arranged in the speed limiter (1), and the speed limiting circuit comprises a single speed limiting circuit used for processing single signal input and a synchronous speed limiting circuit used for processing double signal input;
the single speed limiting circuit comprises a single input addition circuit (4) for shifting an input signal upwards in parallel, a single input subtraction circuit (5) for shifting the input signal downwards in parallel and an output voltage following circuit (6) for increasing output impedance, which are connected in sequence;
the synchronous speed limiting circuit comprises an operational amplification circuit (7) for amplifying an input signal, a double-input addition circuit (8) for parallelly shifting up the input signal, a double-input subtraction circuit (9) for parallelly shifting down the input signal and a division and voltage following circuit (10) for outputting a speed limiting signal, which are connected in sequence;
the single-input addition circuit (4) and the single-input subtraction circuit (5) of the single speed limiting circuit are both connected with a speed limiting regulation circuit (12) with a speed limiting enabling control unit (11), and the single-input addition circuit (4) and the single-input subtraction circuit (5) which are connected in series are connected with the double-input addition circuit (8) and the double-input subtraction circuit (9) which are connected in series.
2. The external engine speed governor of claim 1, wherein: the speed-limiting regulation and control circuit (12) comprises a speed-limiting enabling control unit (11) consisting of a resistor R11 and a control optocoupler U3 connected with the resistor R11 in series, and an up-down regulation and control unit consisting of a resistor R10, an adjustable potentiometer RT1 and a resistor R12 which are connected in series in sequence and an operational amplifier U2B connected between the adjustable potentiometer RT1 and the resistor R12.
3. The external engine speed governor of claim 1, wherein: the single-input addition circuit (4) comprises an operational amplifier U1A, a resistor R1 with equal resistance, a resistor R2, a resistor R4 and a resistor R8; the resistor R1 is connected with the resistor R2 in series, and a node between the resistor R1 and the resistor R2 is connected with the reverse input end of the operational amplifier U1A; one ends of the resistor R4 and the resistor R8 are connected with the homodromous input end of the operational amplifier U1A, and the other end of the resistor R4 is connected with an IN1 signal input by an accelerator pedal.
4. The external engine speed governor of claim 1, wherein: the single-input subtraction circuit (5) comprises an operational amplifier U1B, a resistor R3, a resistor R6, a resistor R7, a resistor R9 and a capacitor C1, wherein the resistors R3, R6, R7 and R9 are equal in resistance; one end of the resistor R3 is connected with the output end of the single-input addition circuit (4), the other end of the resistor R3 is connected with a resistor R6 with one end grounded, and the resistor R3 and the resistor R6 are both connected with the same-direction input end of the operational amplifier U1B; one end of each of the resistor R7 and the resistor R9 is connected with the reverse input end of the operational amplifier U1B; one end of the capacitor C1 is grounded, and the other end of the capacitor C1 is connected with the power supply input end of the operational amplifier U1B.
5. The external engine speed governor of claim 1, wherein: the output voltage follower circuit (6) comprises an operational amplifier U2A for outputting an OUT1 signal and a capacitor C2 connected with the operational amplifier U2A; and the same-direction input end of the operational amplifier U2A is connected with the output end of the single-input subtraction circuit (5).
6. The external engine speed governor of claim 1, wherein: the operational amplification circuit (7) comprises an operational amplifier U4B, a resistor R15, a resistor R16, a resistor R20 and a capacitor C3, wherein the resistors R15, R16 and R20 are equal in resistance, and the capacitor C3 is connected with a power supply input end of the operational amplifier U4B; one end of the resistor R15 is grounded, the other end of the resistor R15 is connected with the resistor R16 in series, and a node between the resistor R15 and the resistor R16 is connected with the reverse input end of the operational amplifier U4B; one end of the resistor R20 is connected with an accelerator pedal input IN2 signal, and the other end of the resistor R is connected with the homodromous input end of the operational amplifier U4B.
7. The external engine speed governor of claim 1, wherein: the dual-input addition circuit (8) comprises an operational amplifier U4A, a resistor R13 with equal resistance, a resistor R14, a resistor R18 and a resistor R24; the resistor R13 is connected with the resistor R14 in series, and a node between the resistor R1 and the resistor R2 is connected with the reverse input end of the operational amplifier U4A; one ends of the resistor R18 and the resistor R24 are connected with the same-direction input end of the operational amplifier U4A, and the other end of the resistor R24 is connected with the resistor R8 of the single-input adding circuit (4), the resistor R9 of the single-input subtracting circuit (5) and the output end of the operational amplifier U2B of the up-down shifting regulation and control unit.
8. The external engine speed governor of claim 1, wherein: the dual-input subtraction circuit (9) comprises an operational amplifier U5A, a resistor R17 with equal resistance, a resistor R21, a resistor R23 and a resistor R25; one end of the resistor R17 is connected with the output end of the double-input addition circuit (8), the other end of the resistor R17 is connected with a resistor R21 with one end grounded, and the resistor R17 and the resistor R21 are both connected with the homodromous input end of the operational amplifier U1B; one ends of the resistor R23 and the resistor R25 are connected with the reverse input end of the operational amplifier U5A, and the other end of the resistor R25 is connected with a resistor R24 of the double-input addition circuit (8).
9. The external engine speed governor of claim 1, wherein: the division and voltage following circuit (10) comprises an operational amplifier U5B, a resistor R19 with equal resistance, a resistor R22 and a capacitor C4; one end of the resistor R22 is grounded, the other end of the resistor R22 is connected with the resistor R19, and one end of the resistor R19 is connected with the output end of the operational amplifier U5A of the double-input subtraction circuit (9); and the capacitor C4 is connected with the power supply input end of the operational amplifier U5A.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710876002.0A CN107401461B (en) | 2017-09-25 | 2017-09-25 | External engine speed limiter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710876002.0A CN107401461B (en) | 2017-09-25 | 2017-09-25 | External engine speed limiter |
Publications (2)
| Publication Number | Publication Date |
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| CN107401461A CN107401461A (en) | 2017-11-28 |
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