CN107395194B - A capacitive sensor interface circuit based on frequency conversion - Google Patents

Abstract

The invention discloses a capacitive sensor interface circuit based on frequency conversion, which consists of a frequency modulation circuit based on capacitance change and a frequency voltage conversion circuit; the input end of the frequency modulation circuit based on capacitance change forms the input end of the whole interface circuit and is connected with the tested capacitor; the output end of the frequency modulation circuit based on capacitance change is connected with the input end of the frequency-voltage conversion circuit; the output end of the frequency-voltage conversion circuit forms the output end of the whole interface circuit; the measured capacitance value is converted into a frequency value through the frequency modulation circuit based on capacitance change, and then the frequency value is converted into a voltage value through the frequency voltage conversion circuit. The invention can effectively inhibit the influence of noise at low frequency, only one input signal period is needed, and frequency signals can be converted into corresponding voltage signals, thereby reducing the output delay and greatly improving the response speed of the capacitive sensor interface circuit.

Description

A capacitive sensor interface circuit based on frequency conversion

technical field

The invention relates to the technical field of integrated circuits, in particular to a capacitive sensor interface circuit based on frequency conversion.

Background technique

As a front-end component in the measurement system, the sensor can perceive the changes of external physical quantities, chemical quantities and biological information, and convert these non-electrical information into electrical signals that can be detected and processed by the electronic system according to certain rules. Sensors have been widely used in industrial production, transportation, national defense and military, and biomedical fields. With the continuous advancement of science and technology, sensors are gradually developing in the direction of miniaturization, integration, and intelligence.

Compared with resistive sensors, capacitive sensors themselves do not consume any quiescent current, so they have been widely used in low-power portable mobile terminals, wearable devices and other fields. When the capacitive sensor is determined, the main performance of the sensing system depends on the interface circuit connected to the capacitive sensor. Therefore, higher requirements are put forward for performance indicators such as detection range, power consumption and precision of the interface circuit. The traditional capacitive sensor interface circuit directly amplifies the change in capacitance value and converts it into a change in voltage value, and most of them use the charge pump integration method, which needs to charge the charge pump for multiple cycles to generate a stable output voltage, resulting in The whole interface circuit has slow working speed, high power consumption, low accuracy and sensitivity, occupies too much chip area, and is easily disturbed by temperature, noise and external factors, which greatly limits its application.

Contents of the invention

The invention aims to solve the problems existing in the traditional capacitive sensor interface circuit, and provides a capacitive sensor interface circuit based on frequency conversion.

In order to solve the above problems, the present invention is achieved through the following technical solutions:

A capacitive sensor interface circuit based on frequency conversion, which is composed of a frequency modulation circuit based on capacitance change and a frequency-voltage conversion circuit; the input end of the frequency modulation circuit based on capacitance change forms the input end of the entire interface circuit, and the measured capacitance C _sen connected; the output end of the frequency modulation circuit based on capacitance change is connected to the input end of the frequency-voltage conversion circuit; the output end of the frequency-voltage conversion circuit forms the output end V _out of the entire interface circuit; through the frequency modulation circuit based on capacitance change, the measured The capacitance value C _sen is converted into a frequency value, and then the frequency value is converted into a voltage value through a frequency-voltage conversion circuit.

The above-mentioned frequency modulation circuit based on capacitance change is composed of PMOS transistors PM ₁ to PM ₂ , NMOS transistors NM ₁ to NM ₅ and inverter INV ₁ ; the sources of the PMOS transistors PM ₁ and PM ₂ are connected to the power supply VDD; the PMOS transistors The gate and drain of PM ₁ , the drain of NMOS transistor NM ₁ , the gate of NMOS transistor NM ₃ , and the gate of NMOS transistor NM ₃ are connected; the gate and drain of PMOS transistor PM ₂ , the gate of NMOS transistor NM ₃₁ The drain of the NMOS transistor NM ₁ , the gate of the NMOS transistor NM ₄ , and the input terminal of the inverter INV ₁ are connected; the other end of the inverter INV ₁ forms the output terminal of the frequency modulation circuit based on capacitance changes , connected to the input terminal of the frequency-voltage conversion circuit; after the source of the NMOS transistor NM ₁ is connected to the drain of the NMOS transistor NM ₂ , an input terminal of the frequency modulation circuit based on capacitance variation is formed, which is connected to one end of the measured capacitance C _sen connection; after the source of NMOS transistor N3 is connected to the drain of NMOS transistor NM ₂₄ , another input end of the frequency modulation circuit based on capacitance variation is formed, which is connected with the other end of the measured capacitance C _sen ; the source of NMOS transistor NM ₂ pole, the source of the NMOS transistor _NM4 , and the drain of the NMOS transistor _NM5 ; the gate of the NMOS transistor _NM5 is connected to the external bias voltage V _b1 ; the source of the NMOS transistor _NM5 is connected to the ground GND.

The above-mentioned frequency-voltage conversion circuit is composed of PMOS tubes PM ₃ ~ PM ₇ , NMOS tubes NM ₆ ~ NM ₉ , inverters INV ₂ ~ INV ₃ , flip-flops DFF ₁ ~ DFF ₂ and capacitor C ₁ ; flip-flops DFF ₁ ~ DFF The clock terminal CK of ₂ forms the input terminal of the frequency-voltage conversion circuit, and is connected with the output terminal of the frequency modulation circuit based on capacitance change; the D terminal and the SN terminal of the flip-flop DFF ₁ and the D terminal and the SN terminal of the flip-flop DFF ₂ are connected with The power supply VDD is connected; the Q terminal of the flip-flop DFF ₁ is connected to the gate of the NMOS transistor NM ₆ ; the drain of the NMOS transistor NM ₆ , the drain of the PMOS transistor PM ₃ , the drain of the PMOS transistor PM ₄ , and the drain of the PMOS transistor PM ₆ The gate, the input terminal of the inverter INV ₂ , and the RN terminal of the flip-flop DFF ₂ are connected; the source of the NMOS transistor NM ₆ is connected to the ground GND; the output terminal of the inverter INV ₂ is connected to the gate of the PMOS transistor PM ₃ Connection; the source of the PMOS transistor PM ₆ is connected to the drain of the PMOS transistor PM ₅ ; the source of the PMOS transistor PM ₃ , the source of the PMOS transistor PM ₄ and the source of the PMOS transistor PM ₅ are connected to the power supply VDD; the PMOS transistor PM After the grid of ₄ , the input terminal of the inverter INV ₃ is connected to the RN terminal of the flip-flop DFF ₁ , it is connected to the external reset signal RST; the output terminal of the inverter INV ₃ is connected to the gate of the NMOS transistor NM ₇ , the NMOS transistor The gate of NM ₈ and the gate of NMOS transistor NM ₉ ; the drain of NMOS transistor NM ₈ , the Q terminal of flip-flop DFF ₂ are connected to the gate of PMOS transistor PM ₇ ; the source of PMOS transistor PM ₇ , the source of NMOS transistor NM ₇ is connected to the drain of the PMOS transistor PM ₆ ; the source of the NMOS transistor NM ₇ , the source of the NMOS transistor NM ₈ , the source of the NMOS transistor NM ₉ , and one end of the capacitor C ₁ are connected to the ground GND; the NMOS After the drain of the transistor NM ₉ , the drain of the PMOS transistor PM ₇ , and the other end of the capacitor C ₁ are connected, they form the output end of the frequency-to-voltage conversion circuit, that is, the output end V _{out of} the entire interface circuit.

In the above solution, the flip-flops DFF ₁ -DFF ₂ are edge-triggered D flip-flops.

Compared with the prior art, the present invention has the following characteristics:

1. The frequency-to-voltage conversion circuit can complete the conversion from frequency to voltage within one signal cycle, reducing the signal processing time and improving the working efficiency and response speed of the overall circuit system;

2. Based on the frequency modulation and frequency voltage conversion method of capacitance change, the detection capacitance range can reach 1pF ~ 20pF, and effectively suppress the influence of low frequency noise and external factors;

3. Based on the switch-controlled relaxation oscillator, the capacitor charging direction can be automatically switched, and a square wave with a duty cycle of 50% can be generated.

Description of drawings

Fig. 1 is a structural diagram of a capacitive sensor interface circuit based on frequency conversion.

Fig. 2 is an input-output relationship diagram of the present invention.

Detailed ways

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in combination with specific examples and with reference to the accompanying drawings.

The present invention proposes a capacitive sensor interface circuit based on frequency conversion, as shown in Figure 1, which is composed of a frequency modulation circuit based on capacitance variation and a frequency-voltage conversion circuit. The frequency modulation circuit based on capacitance variation converts different capacitance values into square waves with different frequencies and a duty cycle of 50%. The frequency-to-voltage conversion circuit converts square waves of different frequencies into corresponding voltage signals after one input signal cycle, so that the generated voltage signal has a certain proportional relationship with the detected capacitance.

The above-mentioned frequency modulation circuit based on capacitance change includes: PMOS transistors PM ₁ and PM ₂ , NMOS transistors NM ₁ , NM ₂ , NM ₃ , NM ₄ , and NM ₅ , an inverter INV ₁ , and an external bias voltage V _b1 , which is Measure capacitance C _sen . Among them, the source of PM ₁ is connected to the power supply VDD, the gate of PM ₁ is connected to the drain of PM ₁ and then connected to the drain of NM ₁ , the gate of NM ₁ is connected to the drain of NM ₃ , and the source of NM ₁ The pole is connected to the drain of NM ₂ , the gate of NM ₂ is connected to the drain of NM ₁ , the source of NM ₂ is connected to the drain of NM ₅ , the gate of NM ₅ is connected to V _b1 , and the source of NM ₅ Connect to ground GND. The source of PM ₂ is connected to the power supply VDD, the gate of PM ₂ is connected to the drain of PM ₂ and then connected to the drain of NM ₃ , the gate of NM ₃ is connected to the drain of NM ₁ , and the source of NM ₃ is connected to The drain of NM ₄ is connected, the gate of NM ₄ is connected with the drain of NM ₃ and then connected with the input terminal of inverter INV ₁ , the source of NM ₄ is connected with the drain of NM ₅ . One end of the measured capacitance C _sen is connected to the source of NM ₁ , and the other end of C _sen is connected to the source of NM ₃ .

The above-mentioned frequency-voltage conversion circuit includes: PMOS transistors PM ₃ , PM ₄ , PM ₅ , PM ₆ , PM ₇ , NMOS transistors NM ₆ , NM ₇ , NM ₈ , NM ₉ , two inverters INV ₂ , INV ₃ , two Edge-triggered D flip-flops DFF ₁ and DFF ₂ , capacitor C ₁ , external bias voltage V _b2 , external reset signal RST, and output terminal V _out . Wherein, the output terminal of the inverter INV ₁ in the previous stage circuit is connected to the clock terminals CK of the two D flip-flops DFF ₁ and DFF ₂ . The D terminal of the DFF ₁ is connected to the SN terminal and then connected to the power supply VDD, the RN terminal of the DFF ₁ is connected to the external reset signal RST, and the Q terminal of the DFF ₁ is connected to the gate of the NM ₆ . The D terminal of the DFF ₂ is connected to the SN terminal and then connected to the power supply VDD, the RN terminal of the DFF ₂ is connected to the drain of the NM ₆ , and the Q terminal of the DFF ₂ is connected to the gate of the PM ₇ . The source of PM ₃ is connected to the power supply VDD, the gate of PM ₃ is connected to the output terminal of inverter INV ₂ , the drain of PM ₃ is connected to the input terminal of inverter INV ₂ and then connected to the drain of NM ₆ , The source of NM ₆ is connected to the ground GND. The source of PM ₄ is connected to the power supply VDD, the gate of PM ₄ is connected to the external reset signal RST, and the drain of PM ₄ is connected to the drain of NM ₆ . The input terminal of the inverter INV ₃ is connected to the external reset signal RST, and the output terminal of the inverter INV ₃ is connected to the gate of the NM ₇ . The gates of NM ₈ and NM ₉ are connected to the output terminal of the inverter INV ₃ , the drain of NM ₈ is connected to the gate of PM ₇ , and the source of NM ₈ is connected to the ground GND. The drain of NM ₉ is connected to the source of PM ₇ , and the source of NM ₉ is connected to the ground GND. The source of PM ₅ is connected to the power supply VDD, the gate of PM ₅ is connected to V _b2 , the drain of PM ₅ is connected to the source of PM ₆ , the gate of PM ₆ is connected to the drain of NM ₆ , and the drain of PM ₆ The pole is connected to the drain of NM ₇ , the source of NM ₇ is connected to GND, the source of PM ₇ is connected to the drain of NM ₇ , the drain of PM ₇ is connected to one end of capacitor _C1 and then connected to the output end of the circuit V _out , the other end of the capacitor C ₁ is connected to the ground GND.

The working principle of the invention is as follows: the measured capacitance value is first converted into a frequency value through a frequency modulation circuit based on capacitance change, and then the frequency value is converted into a voltage value through a frequency-voltage conversion circuit.

In the frequency modulation circuit based on capacitance change, PMOS transistors PM ₁ and PM ₂ are used as active loads, NMOS transistors NM ₁ , NM ₂ , NM ₃ , and NM ₄ are used as switches, NMOS transistor NM ₅ is used as a tail current source, and NMOS transistor NM ₁ When NM ₄ and NM 4 are turned on, NMOS transistors NM ₂ and NM ₃ are turned off to realize forward charging of capacitor C _sen ; when NMOS transistors NM ₁ and NM ₄ are turned off, NMOS transistors NM ₂ and NM ₃ are turned on to realize charging to capacitor C _sen is reversely charged; when the capacitor C _sen is positively charged, it forms an RC relaxation oscillator with the active resistor PM ₁ ; when the capacitor C _sen is reversely charged, it forms an RC relaxation oscillator with the active resistor PM ₂ ; finally, after the reverse The phase device INV ₁ is used for shaping and amplifying, and the frequency modulation circuit outputs a full-swing square wave signal whose frequency varies with capacitance and whose duty cycle is 50%.

In the frequency-voltage conversion circuit, when the RST signal is at low level, the PMOS transistor PM ₄ pulls the gate of PM ₆ to a high level, and the NMOS transistor NM ₇ pulls the source of PM ₇ to a low level, and the NMOS transistor NM ₈ pulls down the gate of PM ₇ to low level, and NMOS transistor NM ₉ pulls capacitor C ₁ down to low level; when the RST signal is high level, D flip-flop DFF ₁ starts to work, when D flip-flop DFF ₁ detects the rising edge of the input signal, and the output terminal Q of the D flip-flop DFF ₁ outputs a high level. At this time, the NMOS transistor NM ₆ is turned on, and the inverter INV ₂ and the PMOS transistor PM ₃ are used to turn the drain of NM ₆ The pole is locked at low level, so that the drain level of NM ₆ is always low. When the drain of NM ₆ is at low level, the PMOS transistor PM ₆ is turned on; when the drain of NM ₆ is at low level, D flip-flop DFF ₂ Start to work, when the D flip-flop DFF ₂ detects the rising edge of the input signal, the output terminal Q of the D flip-flop DFF ₂ outputs a high level, at this time the PMOS tube PM ₇ is turned off; the time when PM ₆ and PM ₇ are jointly turned on , is one cycle of the input signal, the bias current source PM ₅ charges the capacitor C ₁ for one cycle, the frequency of the input signal is different, the corresponding cycle is different, and the charging time of the capacitor C ₁ is also different, finally, Input signals of different frequencies correspond to different output voltages on the capacitor C ₁ , thereby realizing frequency-to-voltage conversion.

The frequency of the oscillating square wave generated by the frequency modulation circuit based on capacitance changes can be expressed as formula (1):

为流过被测电容C_sen的电流，V_swing为被测电容C_sen两端的电压差。in,

For the current flowing through the measured capacitor C _sen , V _swing is the voltage difference between the two ends of the measured capacitor C _sen .

So the period of the square wave can be expressed as formula (2):

After the frequency-to-voltage conversion circuit, the final output voltage is:

为PMOS管PM₅产生的电流。in,

It is the current generated by the PMOS transistor _PM5 .

The invention adopts a relaxation oscillator based on switch control to directly convert the change of capacitance into a change of frequency, realize automatic switching of the charging direction of the capacitor, and generate a square wave with a duty ratio of 50%, effectively suppressing the influence of noise at low frequencies, and effectively improving The accuracy of capacitance detection is improved. The invention adopts a frequency-voltage conversion circuit, which only needs one input signal cycle, and can convert the frequency signal into a corresponding voltage signal, which reduces the output delay, greatly improves the response speed of the capacitance sensor interface circuit, and realizes the adjustment of the capacitance value. detection. While simplifying the circuit structure, the present invention improves the processing speed of the circuit to the input signal, reduces the power consumption, which is only on the order of microwatts, and does not use resistors, and only uses a small amount of capacitance, which effectively reduces the power consumption caused by temperature changes. Thermal noise impact, reduced layout area, more convenient compatibility with standard CMOS processes, and reduced production costs. The method of frequency modulation and frequency-voltage conversion based on capacitance changes can effectively suppress the influence of low-frequency noise, and can realize high-speed and accurate capacitance detection. Figure 2 is a diagram of the relationship between input and output of the present invention. CadenceSpectre simulation based on 0.18-um CMOS technology shows that the detectable capacitance range is 1pF to 20pF, the output voltage range is 500mV to 1.225V, and the total power consumption is 85.14uW under the condition of 1.8V power supply. Delay can be at least 72.774nS.

The invention can solve the problems of long signal processing time, large delay, low sensitivity, narrow detection range, easy to be affected by noise, excessive chip area and power consumption and the like existing in the traditional capacitive sensor interface circuit.

It should be noted that although the above-mentioned embodiments of the present invention are illustrative, they are not intended to limit the present invention, so the present invention is not limited to the above specific implementation manners. Without departing from the principles of the present invention, all other implementations obtained by those skilled in the art under the inspiration of the present invention are deemed to be within the protection of the present invention.

Claims (3)

1. A capacitive sensor interface circuit based on frequency conversion, characterized by: the frequency modulation circuit is based on capacitance change, and the frequency voltage conversion circuit is composed of a frequency modulation circuit and a frequency voltage conversion circuit; the input end of the frequency modulation circuit based on capacitance change forms the input end of the whole interface circuit and the tested capacitor C _sen Connecting; the output end of the frequency modulation circuit based on capacitance change is connected with the input end of the frequency-voltage conversion circuit; the output end of the frequency-voltage conversion circuit forms the output end V of the whole interface circuit _out The method comprises the steps of carrying out a first treatment on the surface of the The measured capacitance value C is firstly measured by a frequency modulation circuit based on capacitance change _sen Converting the frequency value into a frequency value, and converting the frequency value into a voltage value through a frequency-voltage conversion circuit;

the frequency-voltage conversion circuit is formed by PMOS (P-channel metal oxide semiconductor) tubes PM ₃ ～PM ₇ NMOS tube NM ₆ ～NM ₉ Inverter INV ₂ ～INV ₃ Flip-flop DFF ₁ ～DFF ₂ And capacitor C ₁ Composition; flip-flop DFF ₁ ～DFF ₂ The clock end CK of the frequency-voltage conversion circuit is connected with the output end of the frequency modulation circuit based on capacitance change; flip-flop DFF ₁ D-terminal and SN-terminal of (a) and flip-flop DFF ₂ The D end and the SN end of the power supply are connected with the power supply VDD; flip-flop DFF ₁ Q terminal of (2) and NMOS transistor NM ₆ Is connected with the grid electrode; NMOS tube NM ₆ Drain electrode of PMOS tube PM ₃ Drain electrode of PMOS tube PM ₄ Drain electrode of PMOS tube PM ₆ Grid electrode of (C) and inverter INV ₂ Input terminal of (a), and flip-flop DFF ₂ Is connected with the RN end; NMOS tube NM ₆ Is connected to ground GND; inverter INV ₂ Output end of (2) and PMOS tube PM ₃ Is connected with the grid electrode; PMOS tube PM ₆ Source electrode of (C) and PMOS tube PM ₅ Is connected with the drain electrode of the transistor; PMOS tube PM ₃ Source electrode of PMOS tube PM ₄ Source electrode of (C) and PMOS tube PM ₅ Is connected with a power supply VDD; PMOS tube PM ₄ Grid electrode of (C) and inverter INV ₃ Is input to and flip-flop DFF ₁ Is connected with an external reset signal RST after being connected with an RN end; inverter INV ₃ The output end of (a) is connected with an NMOS tube NM ₇ Grid electrode of (n-channel metal oxide semiconductor) NMOS (N-channel metal oxide semiconductor) tube NM ₈ Gate and NMOS transistor NM ₉ A gate electrode of (a); NMOS tube NM ₈ Is of the drain and flip-flop DFF ₂ Q end of (2) and PMOS tube PM ₇ Is connected with the grid electrode; PMOS tube PM ₇ Source electrode of (NMOS) tube NM ₇ Drain electrode of (C) and PMOS tube PM ₆ Is connected with the drain electrode of the transistor; NMOS tube NM ₇ Source electrode of (NMOS) tube NM ₈ Source electrode of (NMOS) tube NM ₉ Source of (C), and capacitor C ₁ Is connected to ground GND; NMOS tube NM ₉ Drain electrode of PMOS tube PM ₇ Drain of (C), and capacitor C ₁ After the other end of the interface circuit is connected, an output end of the frequency-voltage conversion circuit, namely an output end V of the whole interface circuit _out 。

2. A capacitive sensor interface circuit based on frequency conversion as claimed in claim 1, wherein: the frequency modulation circuit based on capacitance change is formed by PMOS (P-channel metal oxide semiconductor) tube PM ₁ ～PM ₂ NMOS tube NM ₁ ～NM ₅ Inverter INV ₁ Composition;

PMOS tube PM ₁ And PM ₂ Is connected to a power supply VDD; PMOS tube PM ₁ Grid electrode, drain electrode and NMOS tube NM ₁ Drain of NMOS transistor NM ₂ Gate of (c), and NMOS transistor NM ₃ Gate phase of (c)Connecting; PMOS tube PM ₂ Grid electrode, drain electrode and NMOS tube NM ₃ Drain of NMOS transistor NM ₁ Grid electrode of (n-channel metal oxide semiconductor) NMOS (N-channel metal oxide semiconductor) tube NM ₄ Gate of (2), and inverter INV ₁ Is connected with the input end of the power supply; inverter INV ₁ The other end of the frequency modulation circuit based on capacitance change is connected with the input end of the frequency-voltage conversion circuit; NMOS tube NM ₁ Source and NMOS transistor NM ₂ After the drains of the capacitors are connected, an input end of the frequency modulation circuit based on capacitance change is formed to be connected with the capacitor C to be tested _sen Is connected with one end of the connecting rod; NMOS tube NM ₃ Source and NMOS transistor NM ₄ After the drain electrode of the capacitor is connected, another input end of the frequency modulation circuit based on capacitance change is formed and connected with the tested capacitor C _sen Is connected with the other end of the connecting rod; NMOS tube NM ₂ Source electrode of (NMOS) tube NM ₄ Source of (2), and NMOS transistor NM ₅ Is connected with the drain electrode of the transistor; NMOS tube NM ₅ Gate of (2) and external bias voltage V _b1 Connecting; NMOS tube NM ₅ Is connected to ground GND.

3. A capacitive sensor interface circuit based on frequency conversion as claimed in claim 1, wherein: flip-flop DFF ₁ ～DFF ₂ Is an edge-triggered D flip-flop.

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