CN107395194B - Capacitive sensor interface circuit based on frequency conversion - Google Patents
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Abstract
The invention discloses a capacitive sensor interface circuit based on frequency conversion, which consists of a frequency modulation circuit based on capacitance change and a frequency voltage conversion circuit; the input end of the frequency modulation circuit based on capacitance change forms the input end of the whole interface circuit and is connected with the tested capacitor; the output end of the frequency modulation circuit based on capacitance change is connected with the input end of the frequency-voltage conversion circuit; the output end of the frequency-voltage conversion circuit forms the output end of the whole interface circuit; the measured capacitance value is converted into a frequency value through the frequency modulation circuit based on capacitance change, and then the frequency value is converted into a voltage value through the frequency voltage conversion circuit. The invention can effectively inhibit the influence of noise at low frequency, only one input signal period is needed, and frequency signals can be converted into corresponding voltage signals, thereby reducing the output delay and greatly improving the response speed of the capacitive sensor interface circuit.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a capacitive sensor interface circuit based on frequency conversion.
Background
The sensor is used as a front end part in a measuring system, can sense the change of external physical quantity, chemical quantity and biological information, and converts the non-electric quantity information into an electric signal which can be detected and processed by an electronic system according to a certain rule. The sensor is widely applied to the fields of industrial production, transportation, national defense and military, biomedical treatment and the like, and along with the continuous progress of technology, the sensor gradually develops towards miniaturization, integration and intellectualization.
Compared with the resistive sensor, the capacitive sensor does not consume any static current, so the capacitive sensor has been widely applied in the fields of low-power-consumption portable mobile terminals, wearable devices and the like. When the capacitive sensor is determined, the primary performance of the sensing system is dependent on the interface circuit connected to the capacitive sensor. Therefore, high requirements are put on performance indexes such as detection range, power consumption, precision and the like of the interface circuit. The traditional capacitive sensor interface circuit directly amplifies the variation of the capacitance value, converts the variation into the variation of the voltage value, and most of the capacitive sensor interface circuit adopts a charge pump integration method, and a charge pump is charged through a plurality of periods to generate stable output voltage, so that the whole interface circuit is slower in working speed, higher in power consumption, lower in accuracy and sensitivity, occupies too much chip area, is easily interfered by temperature, noise and external factors, and is greatly limited in application.
Disclosure of Invention
The invention aims to solve the problems of the traditional capacitive sensor interface circuit and provides a capacitive sensor interface circuit based on frequency conversion.
In order to solve the problems, the invention is realized by the following technical scheme:
a capacitive sensor interface circuit based on frequency conversion is composed of a frequency modulation circuit based on capacitance variation and a frequency voltageA conversion circuit; the input end of the frequency modulation circuit based on capacitance change forms the input end of the whole interface circuit and the tested capacitor C sen Connecting; the output end of the frequency modulation circuit based on capacitance change is connected with the input end of the frequency-voltage conversion circuit; the output end of the frequency-voltage conversion circuit forms the output end V of the whole interface circuit out The method comprises the steps of carrying out a first treatment on the surface of the The measured capacitance value C is firstly measured by a frequency modulation circuit based on capacitance change sen Converting the voltage value into a frequency value, and converting the frequency value into a voltage value through a frequency-voltage conversion circuit.
The frequency modulation circuit based on capacitance change is formed by PMOS (P-channel metal oxide semiconductor) tube PM 1 ～PM 2 NMOS tube NM 1 ～NM 5 Inverter INV 1 Composition; PMOS tube PM 1 And PM 2 Is connected to a power supply VDD; PMOS tube PM 1 Grid electrode, drain electrode and NMOS tube NM 1 Drain of NMOS transistor NM 3 Gate of (c), and NMOS transistor NM 3 Is connected with the grid electrode of the power supply; PMOS tube PM 2 Grid electrode, drain electrode and NMOS tube NM 31 Drain of NMOS transistor NM 1 Grid electrode of (n-channel metal oxide semiconductor) NMOS (N-channel metal oxide semiconductor) tube NM 4 Gate of (2), and inverter INV 1 Is connected with the input end of the power supply; inverter INV 1 The other end of the frequency modulation circuit based on capacitance change is connected with the input end of the frequency-voltage conversion circuit; NMOS tube NM 1 Source and NMOS transistor NM 2 After the drains of the capacitors are connected, an input end of the frequency modulation circuit based on capacitance change is formed to be connected with the capacitor C to be tested sen Is connected with one end of the connecting rod; source electrode of NMOS tube N3 and NMOS tube NM 24 After the drain electrode of the capacitor is connected, another input end of the frequency modulation circuit based on capacitance change is formed and connected with the tested capacitor C sen Is connected with the other end of the connecting rod; NMOS tube NM 2 Source electrode of (NMOS) tube NM 4 Source of (2), and NMOS transistor NM 5 Is connected with the drain electrode of the transistor; NMOS tube NM 5 Gate of (2) and external bias voltage V b1 Connecting; NMOS tube NM 5 Is connected to ground GND.
The frequency-voltage conversion circuit is formed by PMOS (P-channel metal oxide semiconductor) tubes PM 3 ～PM 7 NMOS tube NM 6 ～NM 9 Inverter INV 2 ～INV 3 Flip-flop DFF 1 ～DFF 2 And capacitor C 1 Composition; flip-flop DFF 1 ～DFF 2 The clock end CK of the frequency-voltage conversion circuit is connected with the output end of the frequency modulation circuit based on capacitance change; flip-flop DFF 1 D-terminal and SN-terminal of (a) and flip-flop DFF 2 The D end and the SN end of the power supply are connected with the power supply VDD; flip-flop DFF 1 Q terminal of (2) and NMOS transistor NM 6 Is connected with the grid electrode; NMOS tube NM 6 Drain electrode of PMOS tube PM 3 Drain electrode of PMOS tube PM 4 Drain electrode of PMOS tube PM 6 Grid electrode of (C) and inverter INV 2 Input terminal of (a), and flip-flop DFF 2 Is connected with the RN end; NMOS tube NM 6 Is connected to ground GND; inverter INV 2 Output end of (2) and PMOS tube PM 3 Is connected with the grid electrode; PMOS tube PM 6 Source electrode of (C) and PMOS tube PM 5 Is connected with the drain electrode of the transistor; PMOS tube PM 3 Source electrode of PMOS tube PM 4 Source electrode of (C) and PMOS tube PM 5 Is connected with a power supply VDD; PMOS tube PM 4 Grid electrode of (C) and inverter INV 3 Is input to and flip-flop DFF 1 Is connected with an external reset signal RST after being connected with an RN end; inverter INV 3 The output end of (a) is connected with an NMOS tube NM 7 Grid electrode of (n-channel metal oxide semiconductor) NMOS (N-channel metal oxide semiconductor) tube NM 8 Gate and NMOS transistor NM 9 A gate electrode of (a); NMOS tube NM 8 Is of the drain and flip-flop DFF 2 Q end of (2) and PMOS tube PM 7 Is connected with the grid electrode; PMOS tube PM 7 Source electrode of (NMOS) tube NM 7 Drain electrode of (C) and PMOS tube PM 6 Is connected with the drain electrode of the transistor; NMOS tube NM 7 Source electrode of (NMOS) tube NM 8 Source electrode of (NMOS) tube NM 9 Source of (C), and capacitor C 1 Is connected to ground GND; NMOS tube NM 9 Drain electrode of PMOS tube PM 7 Drain of (C), and capacitor C 1 After the other end of the interface circuit is connected, an output end of the frequency-voltage conversion circuit, namely an output end V of the whole interface circuit out 。
In the above scheme, the flip-flop DFF 1 ～DFF 2 Is an edge-triggered D flip-flop.
Compared with the prior art, the invention has the following specific characteristics:
1. the frequency-voltage conversion circuit can complete conversion from frequency to voltage in one signal period, so that the signal processing time is reduced, and the working efficiency and the reaction speed of the whole circuit system are improved;
2. the frequency modulation and frequency voltage conversion method based on capacitance change can detect the capacitance range to 1 pF-20 pF, and effectively inhibit the influence of low-frequency noise and external factors;
3. and based on a relaxation oscillator controlled by a switch, the automatic switching of the charging direction of the capacitor is realized, and a square wave with the duty ratio of 50% is generated.
Drawings
Fig. 1 is a block diagram of a capacitive sensor interface circuit based on frequency conversion.
FIG. 2 is a graph of the input/output relationship of the present invention.
Detailed Description
The invention will be further described in detail below with reference to specific examples and with reference to the accompanying drawings, in order to make the objects, technical solutions and advantages of the invention more apparent.
The invention provides a capacitive sensor interface circuit based on frequency conversion, which is composed of a frequency modulation circuit based on capacitance change and a frequency-voltage conversion circuit as shown in figure 1. The frequency modulation circuit based on capacitance change converts different capacitance values into square waves with different frequencies and 50% duty cycle. The frequency-voltage conversion circuit converts square waves with different frequencies into corresponding voltage signals through one input signal period, so that the generated voltage signals and the detected capacitor are in a certain proportional relation.
The frequency modulation circuit based on capacitance change includes: PMOS tube PM 1 、PM 2 NMOS tube NM 1 、NM 2 、NM 3 、NM 4 、NM 5 An inverter INV 1 External bias voltage V b1 Capacitance C to be measured sen . Wherein PM 1 Is connected with the power supply VDD, PM 1 Gate and PM of (C) 1 Is connected with NM after drain electrode of (C) 1 Drain-to-drain (NM) 1 Gate and NM of (2) 3 Drain-to-drain (NM) 1 Source and NM of (2) 2 Drain-to-drain (NM) 2 Gate and NM of (2) 1 Drain-to-drain (NM) 2 Source and NM of (2) 5 Drain-to-drain (NM) 5 Gate and V of (2) b1 Connected to NM 5 Is connected to ground GND. PM (particulate matter) 2 Is connected with the power supply VDD, PM 2 Gate and PM of (C) 2 Is connected with NM after drain electrode of (C) 3 Drain-to-drain (NM) 3 Gate and NM of (2) 1 Drain-to-drain (NM) 3 Source and NM of (2) 4 Drain-to-drain (NM) 4 Gate and NM of (2) 3 Is connected with the drain electrode of the inverter INV 1 Is connected with the input end of NM 4 Source and NM of (2) 5 Is connected to the drain of the transistor. Capacitance C to be measured sen Is one end of (2) and NM 1 Is connected with the source electrode of C sen Is connected with NM at the other end of (2) 3 Is connected to the source of (c).
The frequency-voltage conversion circuit includes: PMOS tube PM 3 、PM 4 、PM 5 、PM 6 、PM 7 NMOS tube NM 6 、NM 7 、NM 8 、NM 9 Two inverters INV 2 、INV 3 Two edge triggered D flip flop DFF 1 、DFF 2 Capacitance C 1 External bias voltage V b2 External reset signal RST, output terminal V out . Wherein, the inverter INV in the previous stage circuit 1 And two D flip-flop DFFs 1 、DFF 2 Is connected to the clock terminal CK. DFF (DFF) 1 D terminal of (1) is connected with SN terminal and then connected with power supply VDD, DFF 1 RN terminal of (A) is connected with an external reset signal RST, and DFF 1 Q terminal and NM of (2) 6 Is connected to the gate of (c). DFF (DFF) 2 D terminal of (1) is connected with SN terminal and then connected with power supply VDD, DFF 2 RN and NM of (2) 6 Is connected with the drain of the DFF 2 Q terminal and PM of (C) 7 Is connected to the gate of (c). PM (particulate matter) 3 Is connected with the power supply VDD, PM 3 Gate of (v) and inverter INV 2 Is connected with the output end of PM 3 Drain of (d) and inverter INV 2 Is connected with NM after the input terminal of (C) 6 Drain-to-drain (NM) 6 Is connected to ground GND. PM (particulate matter) 4 Is connected with the power supply VDD, PM 4 The gate of (2) is connected to an external reset signal RST, PM 4 Drain and NM of (2) 6 Is connected to the drain of the transistor. Inverter INV 3 An input end of (1) is connected with an external reset signal RST to form an inverter INV 3 Output terminal of (2) and NM 7 Is connected to the gate of (c). NM (NM) 8 、NM 9 Is connected with the grid electrode of the inverter INV 3 Is connected with the output end of NM 8 Drain and PM of (C) 7 Gate-to-gate (NM) 8 Is connected to ground GND. NM (NM) 9 Drain and PM of (C) 7 Is connected with the source electrode of NM 9 Is connected to ground GND. PM (particulate matter) 5 Is connected with the power supply VDD, PM 5 Gate and V of (2) b2 Connected to PM 5 Drain and PM of (C) 6 Is connected with the source of PM 6 Gate and NM of (2) 6 Is connected with the drain of PM 6 Drain and NM of (2) 7 Drain-to-drain (NM) 7 Is connected to ground GND, PM 7 Source and NM of (2) 7 Is connected with the drain of PM 7 Drain of (C) and capacitor C 1 Is connected at one end to the output terminal V of the rear circuit out Capacitance C 1 The other end of (2) is connected to ground GND.
The working principle of the invention is as follows: the measured capacitance value is converted into a frequency value through the frequency modulation circuit based on capacitance change, and then the frequency value is converted into a voltage value through the frequency voltage conversion circuit.
In a frequency modulation circuit based on capacitance change, a PMOS tube PM 1 、PM 2 NMOS tube NM as active load 1 、NM 2 、NM 3 、NM 4 As a switch, NMOS tube NM 5 NMOS tube NM as tail current source 1 、NM 4 When conducting, NMOS tube NM 2 、NM 3 Turn-off to realize the capacitor C sen Forward charging; NMOS tube NM 1 、NM 4 When turned off, NMOS transistor NM 2 、NM 3 Conducting to realize to the capacitor C sen Reverse charging; capacitor C sen In forward charging, with active resistance PM 1 Forming an RC relaxation oscillator; capacitor C sen And active resistor PM during reverse charging 2 Formation of RC sheetA relaxation oscillator; finally, through an inverter INV 1 Shaping and amplifying, wherein the output frequency of the frequency modulation circuit changes along with capacitance, and the duty ratio is 50% of full-swing square wave signal.
In the frequency-voltage conversion circuit, when RST signal is low level, PMOS tube PM 4 PM (particulate matter) 6 Is pulled high to the gate of NMOS transistor NM 7 PM (particulate matter) 7 Is pulled low to low level, NMOS transistor NM 8 PM (particulate matter) 7 Is pulled low to low level, NMOS transistor NM 9 Capacitance C 1 Pull low to low; d flip-flop DFF when RST signal is high 1 Start to work when D flip-flop DFF 1 Detecting rising edges of input signals, D flip-flop DFF 1 The output terminal Q of (1) outputs high level, and the NMOS transistor NM is at the same time 6 Conduction inverter INV 2 PMOS tube PM 3 For inserting NM 6 Is locked low to make NM 6 The drain level of (2) is always low when NM 6 When the drain electrode of the PMOS transistor is at a low level, the PMOS transistor PM 6 Conducting; when NM 6 D flip-flop DFF when drain of (C) is low 2 Start to work when D flip-flop DFF 2 Detecting rising edges of input signals, D flip-flop DFF 2 The output end Q of the PMOS tube PM outputs high level 7 Turning off; PM (particulate matter) 6 、PM 7 The common conduction time is one period of the input signal, and the bias current source PM 5 Is a capacitor C 1 Charging one period of electricity, the frequency of the input signal is different, the corresponding period is different, and the capacitor C 1 The charging time is different, and finally, the input signals with different frequencies correspond to the capacitor C 1 And different output voltages, thereby achieving frequency-to-voltage conversion.
The frequency at which the capacitance-change-based frequency modulation circuit generates an oscillating square wave can be expressed as formula (1):
wherein,,
for flowing through the capacitor C to be measured sen Current of V swing For the capacitance C to be measured sen Voltage difference across the two terminals.
The period of square waves can be expressed as formula (2):
after passing through the frequency-voltage conversion circuit, the final output voltage is:
wherein,,
is PMOS tube PM 5 The current generated.
The invention adopts the relaxation oscillator based on switch control to directly convert the change of the capacitor into the change of frequency, realizes the automatic switching of the charging direction of the capacitor, and generates square waves with the duty ratio of 50 percent, thereby effectively inhibiting the influence of noise at low frequency and effectively improving the precision of capacitor detection. The invention adopts the frequency-voltage conversion circuit, only one input signal period is needed, the frequency signal can be converted into the corresponding voltage signal, the output delay is reduced, the response speed of the capacitive sensor interface circuit is greatly improved, and the detection of the capacitance value is realized. The invention simplifies the circuit structure, improves the processing speed of the circuit to the input signal, reduces the power consumption, is only in the micro watt level, does not use a resistor, only uses a small amount of capacitance, effectively reduces the influence of thermal noise caused by temperature change, reduces the layout area, is more convenient to be compatible with the standard CMOS process, and reduces the production cost. The frequency modulation and frequency-voltage conversion method based on capacitance change is adopted, so that the influence of low-frequency noise is effectively inhibited, and high-speed and accurate capacitance detection can be realized. FIG. 2 is a graph of the input/output relationship of the present invention, and Cadence spectrum simulation based on a 0.18-um CMOS process shows that the detectable capacitance range is 1 pF-20 pF, the output voltage range is 500 mV-1.225V, the total power consumption under 1.8V power supply condition is 85.14uW, and the circuit delay can be 72.774nS at least.
The invention can solve the problems of longer signal processing time, longer time delay, lower sensitivity, narrower detection range, easiness in being influenced by noise, overlarge chip area and power consumption and the like of the traditional capacitive sensor interface circuit.
It should be noted that, although the examples described above are illustrative, this is not a limitation of the present invention, and thus the present invention is not limited to the above-described specific embodiments. Other embodiments, which are apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein, are considered to be within the scope of the invention as claimed.
Claims (3)
1. A capacitive sensor interface circuit based on frequency conversion, characterized by: the frequency modulation circuit is based on capacitance change, and the frequency voltage conversion circuit is composed of a frequency modulation circuit and a frequency voltage conversion circuit; the input end of the frequency modulation circuit based on capacitance change forms the input end of the whole interface circuit and the tested capacitor C sen Connecting; the output end of the frequency modulation circuit based on capacitance change is connected with the input end of the frequency-voltage conversion circuit; the output end of the frequency-voltage conversion circuit forms the output end V of the whole interface circuit out The method comprises the steps of carrying out a first treatment on the surface of the The measured capacitance value C is firstly measured by a frequency modulation circuit based on capacitance change sen Converting the frequency value into a frequency value, and converting the frequency value into a voltage value through a frequency-voltage conversion circuit;
the frequency-voltage conversion circuit is formed by PMOS (P-channel metal oxide semiconductor) tubes PM 3 ～PM 7 NMOS tube NM 6 ～NM 9 Inverter INV 2 ～INV 3 Flip-flop DFF 1 ～DFF 2 And capacitor C 1 Composition; flip-flop DFF 1 ～DFF 2 The clock end CK of the frequency-voltage conversion circuit is connected with the output end of the frequency modulation circuit based on capacitance change; flip-flop DFF 1 D-terminal and SN-terminal of (a) and flip-flop DFF 2 The D end and the SN end of the power supply are connected with the power supply VDD; flip-flop DFF 1 Q terminal of (2) and NMOS transistor NM 6 Is connected with the grid electrode; NMOS tube NM 6 Drain electrode of PMOS tube PM 3 Drain electrode of PMOS tube PM 4 Drain electrode of PMOS tube PM 6 Grid electrode of (C) and inverter INV 2 Input terminal of (a), and flip-flop DFF 2 Is connected with the RN end; NMOS tube NM 6 Is connected to ground GND; inverter INV 2 Output end of (2) and PMOS tube PM 3 Is connected with the grid electrode; PMOS tube PM 6 Source electrode of (C) and PMOS tube PM 5 Is connected with the drain electrode of the transistor; PMOS tube PM 3 Source electrode of PMOS tube PM 4 Source electrode of (C) and PMOS tube PM 5 Is connected with a power supply VDD; PMOS tube PM 4 Grid electrode of (C) and inverter INV 3 Is input to and flip-flop DFF 1 Is connected with an external reset signal RST after being connected with an RN end; inverter INV 3 The output end of (a) is connected with an NMOS tube NM 7 Grid electrode of (n-channel metal oxide semiconductor) NMOS (N-channel metal oxide semiconductor) tube NM 8 Gate and NMOS transistor NM 9 A gate electrode of (a); NMOS tube NM 8 Is of the drain and flip-flop DFF 2 Q end of (2) and PMOS tube PM 7 Is connected with the grid electrode; PMOS tube PM 7 Source electrode of (NMOS) tube NM 7 Drain electrode of (C) and PMOS tube PM 6 Is connected with the drain electrode of the transistor; NMOS tube NM 7 Source electrode of (NMOS) tube NM 8 Source electrode of (NMOS) tube NM 9 Source of (C), and capacitor C 1 Is connected to ground GND; NMOS tube NM 9 Drain electrode of PMOS tube PM 7 Drain of (C), and capacitor C 1 After the other end of the interface circuit is connected, an output end of the frequency-voltage conversion circuit, namely an output end V of the whole interface circuit out 。
2. A capacitive sensor interface circuit based on frequency conversion as claimed in claim 1, wherein: the frequency modulation circuit based on capacitance change is formed by PMOS (P-channel metal oxide semiconductor) tube PM 1 ～PM 2 NMOS tube NM 1 ～NM 5 Inverter INV 1 Composition;
PMOS tube PM 1 And PM 2 Is connected to a power supply VDD; PMOS tube PM 1 Grid electrode, drain electrode and NMOS tube NM 1 Drain of NMOS transistor NM 2 Gate of (c), and NMOS transistor NM 3 Gate phase of (c)Connecting; PMOS tube PM 2 Grid electrode, drain electrode and NMOS tube NM 3 Drain of NMOS transistor NM 1 Grid electrode of (n-channel metal oxide semiconductor) NMOS (N-channel metal oxide semiconductor) tube NM 4 Gate of (2), and inverter INV 1 Is connected with the input end of the power supply; inverter INV 1 The other end of the frequency modulation circuit based on capacitance change is connected with the input end of the frequency-voltage conversion circuit; NMOS tube NM 1 Source and NMOS transistor NM 2 After the drains of the capacitors are connected, an input end of the frequency modulation circuit based on capacitance change is formed to be connected with the capacitor C to be tested sen Is connected with one end of the connecting rod; NMOS tube NM 3 Source and NMOS transistor NM 4 After the drain electrode of the capacitor is connected, another input end of the frequency modulation circuit based on capacitance change is formed and connected with the tested capacitor C sen Is connected with the other end of the connecting rod; NMOS tube NM 2 Source electrode of (NMOS) tube NM 4 Source of (2), and NMOS transistor NM 5 Is connected with the drain electrode of the transistor; NMOS tube NM 5 Gate of (2) and external bias voltage V b1 Connecting; NMOS tube NM 5 Is connected to ground GND.
3. A capacitive sensor interface circuit based on frequency conversion as claimed in claim 1, wherein: flip-flop DFF 1 ～DFF 2 Is an edge-triggered D flip-flop.
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