CN107370696B

CN107370696B - Digital pre-distortion processing method and device

Info

Publication number: CN107370696B
Application number: CN201610320047.5A
Authority: CN
Inventors: 周丹; 王杰丽; 王静怡; 张永丽; 马静艳
Original assignee: Datang Mobile Communications Equipment Co Ltd
Current assignee: Datang Mobile Communications Equipment Co Ltd
Priority date: 2016-05-13
Filing date: 2016-05-13
Publication date: 2020-05-05
Anticipated expiration: 2036-05-13
Also published as: CN107370696A

Abstract

The invention discloses a digital pre-distortion processing method and a digital pre-distortion processing device, which are used for reducing the occurrence of abnormal conditions in the DPD processing process and ensuring the DPD effect. The method comprises the following steps: checking the working state of a lookup table LUT for executing DPD; and when the LUT is determined to work normally, calling the LUT to execute a DPD processing process.

Description

Digital pre-distortion processing method and device

Technical Field

The present invention relates to the field of communications technologies, and in particular, to a digital predistortion processing method and apparatus.

Background

With the rapid development of communication technology, spectrum resources are increasingly tense, and in order to fully and effectively utilize the spectrum resources, a plurality of complex modulation techniques are adopted, so that the peak-to-average ratio becomes high, and further higher requirements are put forward on the linearity of a power amplifier (power amplifier for short). At present, two common methods for improving the linearity of a power amplifier are available: power back-off and linearization techniques. The power backoff method may greatly reduce the efficiency of the power amplifier and increase the cost. The most common methods of linearization are feedforward technique and predistortion technique, which are more and more concerned by people because of their advantages of small size, high efficiency, good performance, etc.

Digital Pre-Distortion (DPD) technology is to perform predistortion processing on a transmission signal to compensate for Distortion of an amplifier, and ideally, an output signal through a power amplifier is the same as a signal before predistortion. The currently adopted digital predistortion technology is implemented in a Look-Up Table (LUT) manner for both in-band intermodulation information, inter-band intermodulation information, and out-of-band intermodulation information. The general look-up table based predistortion mathematical model expression is as follows:

wherein:

x (n) represents input signal, m represents memory depth, l represents cross term, q represents non-linear order, A_mRepresenting input signalsAmplitude, Q (·) represents a quantization factor; the input address of the LUT is the amplitude Q (A) quantized by the input signal_m) Of determination of w_m,q,lRepresenting the DPD coefficients calculated using the DPD model.

The LUT stores effective information for compensating the nonlinearity and the memorability of the power amplifier, so the LUT is also important for the predistortion module. And when the DPD module finishes DPD coefficient calculation once, the DPD parameters in the LUT table are updated once. When the DPD is executed, the address of the LUT may be searched abnormally, and if the address of the LUT is inaccurate or the information in the LUT is not reasonable, the DPD effect will be seriously affected, or even the power amplifier will be damaged.

Disclosure of Invention

The embodiment of the invention provides a digital pre-distortion processing method and a digital pre-distortion processing device, which are used for reducing the occurrence of abnormal conditions in the DPD processing process and ensuring the DPD effect.

The digital predistortion processing method provided by the embodiment of the invention comprises the following steps:

checking the working state of a lookup table LUT used for executing digital predistortion DPD;

and when the LUT is determined to work normally, calling the LUT to execute a DPD processing process.

According to the method provided by the embodiment of the invention, before the DPD processing process is executed, the working state of the LUT for executing the digital pre-distortion DPD is checked, and when the LUT is determined to work normally, the LUT is called to execute the DPD processing process, so that the reliability of the LUT design implementation process is improved, DPD failure caused by abnormal working state of the LUT is avoided, the DPD effect is ensured, and the occurrence of DPD abnormal conditions is reduced.

Preferably, the checking the operating state of the LUT for executing DPD specifically includes:

presetting a specific value for the LUT for executing DPD;

performing analog DPD operation processing on a preset specific training sequence according to the LUT preset with the specific value to obtain processed data;

and judging whether the working state of the LUT for executing the DPD is normal or not according to the processed data.

Preferably, the preset specific training sequence comprises a number sequence with 1 and 0 alternately arranged;

the LUT with preset specific values comprises at least one LUT, and a plurality of numerical values in the same LUT are the same specific values.

Preferably, the LUT for performing DPD is preset with a specific value as follows:

determining an arrangement mode of each LUT for executing DPD according to configuration parameters of a DPD model, wherein the configuration parameters comprise memory depth and cross item depth; wherein, for each LUT, the LUT is arranged in a manner comprising: the memory depth corresponding to the LUT and the cross item depth corresponding to the LUT under the memory depth corresponding to the LUT;

setting the numerical value in each LUT corresponding to each memory depth with even memory depth as a different specific value, and setting the numerical value in each LUT corresponding to each memory depth with odd memory depth as a different specific value.

Preferably, judging whether the working state of the LUT for executing DPD is normal according to the output data specifically includes:

judging whether the processed data is consistent with preset ideal data or not;

and if the LUT for executing the DPD is consistent with the DPD, determining that the working state of the LUT for executing the DPD is normal, otherwise, determining that the working state of the LUT for executing the DPD is abnormal.

Preferably, the preset ideal data is data obtained by performing analog DPD operation on a preset specific training sequence according to the LUT preset with the specific value under the condition that the working state of the LUT for executing DPD is normal.

Preferably, when it is determined that the processed data is inconsistent with the preset ideal data, the method further includes:

determining a difference value between the processed data and preset ideal data;

and determining that the working state of the LUT corresponding to the difference value is abnormal, wherein the specific value of the LUT corresponding to the difference value is equal to the difference value, or the sum of the specific values of the LUT corresponding to the difference value is equal to the difference value.

The embodiment of the invention provides a digital predistortion processing device, which comprises:

the checking unit is used for checking the working state of a lookup table LUT used for executing the digital predistortion DPD;

and the execution unit is used for calling the LUT to execute the DPD processing process when the LUT is determined to work normally.

Preferably, the verification unit is specifically configured to:

presetting a specific value for the LUT for executing DPD;

Preferably, the check unit presets a specific value for the LUT for executing DPD in the following manner:

Preferably, when the checking unit determines whether the working state of the LUT for executing DPD is normal according to the output data, the checking unit is specifically configured to:

judging whether the processed data is consistent with preset ideal data or not;

Preferably, when determining that the processed data is inconsistent with the preset ideal data, the checking unit is further configured to:

Drawings

Fig. 1 is a schematic diagram of LUT building information according to an embodiment of the present invention;

fig. 2 is a schematic flowchart of a digital predistortion processing method according to an embodiment of the present invention;

fig. 3 is a schematic diagram of a simulation result of time domain simulation of output data of analog predistortion according to an embodiment of the present invention;

fig. 4 is a schematic diagram of a time domain simulation result of another analog predistortion output data according to the embodiment of the present invention;

fig. 5 is a schematic structural diagram of a digital predistortion processing apparatus according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In the communication system, an output signal of the power amplifier passes through a feedback loop and then is input to a DPD calculation module, the DPD calculation module solves a DPD coefficient according to the output signal of the power amplifier and the signal input to the power amplifier, and the DPD coefficient is provided for a forward DPD module for use.

In the DPD processing, the address of the LUT is acquired according to the amplitude of the input signal, and then the information in the LUT is acquired according to the address of the LUT. The LUT building information is shown in fig. 1, each LUT can store 512 values, different values correspond to different signal amplitudes, and the corresponding relationship between different input signal amplitudes and LUT addresses can be determined according to LUT indexes (indexes), so that LUT addresses can be determined.

As can be seen from the above formula (1), the number of LUT is determined by the memory depth and the cross term depth of DPD model. Under different requirements, the configuration of the DPD model is different, and thus, the arrangement of the LUT is also different.

Table 1 shows the number of LUT sheets and their arrangement in a DPD model configuration, where the memory depth is 7 and the depth of cross term is 1, and the horizontal direction in table 1 represents the depth of cross term, denoted by CL, and the vertical direction represents the memory depth, denoted by ML. As can be seen from table 1, when the memory depth is 7 and the cross term depth is 1, the number of LUTs is 24, the numerical values in the LUTs indicate the number of LUTs, for example, the memory depth is 0, and the cross term depth is 0 corresponding to the 1 st LUT; the memory depth is 2, and the depth of the cross term is-1 and corresponds to the 8 th LUT; the memory depth is 7, the depth of the cross term is 1 corresponding to 24 th LUT, etc.

TABLE 1

In order to ensure that correct LUT information is obtained to execute a DPD processing procedure under different DPD model configurations, an embodiment of the present invention provides a digital predistortion processing method, which is shown in fig. 2 and includes:

s101, checking the working state of an LUT (look up table) for executing DPD (digital Pre-distortion);

and S102, when the LUT is determined to work normally, calling the LUT to execute a DPD processing process.

That is, before executing the DPD processing procedure, the working state of the LUT is checked, and when it is determined that the working state of the LUT is normal, the LUT is called to execute the DPD processing procedure; and if the working state of the LUT is determined to be abnormal, reporting an alarm, and after the working state of the LUT is normal, executing a DPD processing process according to the LUT with the normal working state, thereby avoiding DPD failure caused by the abnormal working state of the LUT and ensuring the DPD effect.

Preferably, step S101 specifically includes:

presetting a specific value for the LUT for executing DPD;

As can be seen from the above formula (1), the output value y after DPD operation is obtained by adding up the products of the input signal and the values in the LUT corresponding to the input signal, so that the preset specific training sequence is used as the input signal, and the processed data is obtained by performing the analog DPD operation on the preset specific training sequence according to the formula (1) according to the LUT preset with a specific value, or the processed data may be referred to as the current output value. Specifically, the current output values are: multiplying the current input value by the specific value of each LUT corresponding to the memory depth of 0, summing the product values, and adding the product value of the input value when the memory depth is m and the specific value of each LUT corresponding to the memory depth of m, wherein m belongs to {1,2, 3. For example, if the memory depth is 3, the current output value is: summing the product of the current input value and the specific value of each LUT corresponding to the memory depth of 0, adding the product of the input value when the memory depth is 1 and the specific value of each LUT corresponding to the memory depth of m, adding the product of the input value when the memory depth is 2 and the specific value of each LUT corresponding to the memory depth of m, and adding the product of the input value when the memory depth is 3 and the specific value of each LUT corresponding to the memory depth of m.

judging whether the processed data is consistent with preset ideal data or not;

Preferably, the preset specific training sequence may be, for example, a number sequence including alternating 1 and 0;

for example, the predetermined specific training sequence TR is 101010 …, or the predetermined specific training sequence TR is 010101 …. Of course, the training sequence may be set to other specific values, and is not limited to the above setting.

That is, the LUT with preset specific values may include one LUT or multiple LUTs, and specifically, the number of LUTs included in the LUT with preset specific values is determined by the memory depth and the cross term depth of the DPD model as described above. If each LUT can store 512 data, then for each LUT, the 512 values in the LUT are all the same specific value.

For example, in the DPD model, the memory depth is 7, and the cross term depth is 0, so that each memory depth corresponds to one LUT, and the values in the LUTs corresponding to the memory depths of 0, 2, 4, and 6 are set to 1,2, 4, and 8 in sequence; in this setting, the values in the LUTs corresponding to the memory depths 1, 3, 5, and 7 are set to 1,2, 4, and 8 in this order, and the values in the LUTs corresponding to the memory depths with even numbers are different specific values, the values in the LUTs corresponding to the memory depths with odd numbers are different specific values, and the values in the LUTs corresponding to the memory depths with even numbers may be the same as the values in the LUTs corresponding to the memory depths with odd numbers.

For another example, in the DPD model, the memory depth is 7, and the cross term depth is 0, so that each memory depth corresponds to one LUT, and the values in the LUTs corresponding to the memory depths of 0, 2, 4, and 6 are set to 1, 3, 9, and 27 in sequence; the values in the LUTs corresponding to the memory depths 1, 3, 5, and 7 are set to 1, 3, 9, and 27 in this order.

For another example, in the DPD model, the memory depth is 3 and the cross term depth is 1, so that each memory depth corresponds to three LUTs, which correspond to-1, 0, and 1, respectively, of the cross term depth. The numerical values of the three LUTs corresponding to the memory depths of 0 and 2 are set to 1,2, 4, 8, 16, and 32 in this order, and the numerical values of the three LUTs corresponding to the memory depths of 1 and 3 are set to 1,2, 4, 8, 16, and 32 in this order. Of course. The numerical values in the three LUTs with memory depths of 0 and 2 may be set to 2, 1, 4, 16, 8, and 32 in order, and the numerical values in the three LUTs with memory depths of 1 and 3 may be set to 2, 1, 4, 16, 8, and 32 in order, that is, the specific numerical values in the different LUTs may not be arranged in a strict order.

The specific values preset for the LUT in the embodiment of the present invention are not set arbitrarily, and these specific values have the following characteristics: according to the sum obtained by adding any specific values in the specific values of the LUTs corresponding to the memory depths with even numbers, the sum can be determined which specific values are added to obtain the sum; according to the sum obtained by adding any specific value of the specific values of the LUTs corresponding to the memory depths with odd memory depths, the sum can be determined which specific value is added to obtain the sum. For example, the values in the three LUTs with memory depths of 0 and 2 are set to 1,2, 4, 8, 16 and 32 in sequence according to the above example, so that the sum of 2, 4 and 8 is 14, and although there are a plurality of schemes that can add different numbers to obtain 14, according to the preset specific value, 14 can only be obtained by adding 2, 4 and 8 of the preset values.

That is, when the LUT corresponding to the difference is a LUT, the specific value of the LUT is equal to the difference, for example, the specific values of the preset LUTs are 1,2, 4, 8, 16, 32, 64 …, the difference between the processed data and the preset ideal data is 16, and since the difference 16 is equal to the preset specific value 16 and there is no case that any number of specific values in the preset specific values are added to be equal to 16, the LUT corresponding to the difference 16 is the LUT preset with the specific value of 16. When the LUT corresponding to the difference is a plurality of LUTs, the sum of the specific values of the LUTs is equal to the difference, for example, the preset specific values of the LUTs are 1,2, 4, 8, 16, 32, 64 …, the difference between the processed data and the preset ideal data is 48, and since the difference 48 is obtained by adding the specific values 16 and 32, the difference 48 corresponds to two LUTs, that is, the LUT with the preset specific value of 16 and the LUT with the preset specific value of 32.

A specific example is given below.

Assuming that in the parameter configuration of the DPD model, the memory depth is 7, the depth of the cross terms is 1, and the number of LUTs and their arrangement are as shown in table 1, based on the DPD model, the digital predistortion processing steps provided in the embodiments of the present invention include:

the method comprises the following steps: specific values are preset for the LUT for performing DPD.

Based on the DPD model of the embodiment of the present invention, the specific values preset for the LUTs are shown in table 2, and the arrangement order of the LUTs in table 2 is the same as that in table 1, for example, the data in the row corresponding to the memory depth 0 in table 2 is 2, 1, and 4 sequentially from left to right, where the specific value 2 is a numerical value in the 2 nd LUT, the specific value 1 is a numerical value in the 1 st LUT, and the specific value 4 is a numerical value in the 3 rd LUT; the data in the row corresponding to the memory depth 4 in table 2 are 128, 64 and 256 from left to right, wherein the specific value 128 is the value in the 14 th LUT, the specific value 64 is the value in the 13 th LUT, and the specific value 256 is the value in the 15 th LUT. In table 2, the current input value is 1 (i.e., the input value when the memory depth is 0).

TABLE 2

Step two: and sending a preset specific training sequence to the DPD processor, and carrying out analog DPD operation processing on the preset specific training sequence by the DPD processor according to the LUT preset with the specific value shown in the table 2.

Wherein the preset training sequence comprises a digit sequence with 1 and 0 alternately arranged.

As can be seen from the above formula (1), the output value y after DPD operation is obtained by adding up the products of the input signal and the values in the LUT corresponding to the input signal, so that when the preset specific training sequence is used as the input signal, the current output value is: summing the product value of the current input value and the specific value of each LUT corresponding to the memory depth of 0, and adding the product value of the input value when the memory depth is m and the specific value of each LUT corresponding to the memory depth of m, wherein m is equal to {1,2, 3.

An exemplary analysis of the ideal output value after performing the analog DPD operation on the preset specific training sequence under two configurations, namely, full-match and non-full-match, is given below:

the first situation is as follows: when the matching is full, if the memory depth is 7 and the cross term depth is 1:

(a) if the current input value x is equal to 1, the ideal output value y should be:

y＝1+2+4+8+16+32+64+128+256+512+1024+2048＝4095；

(b) if the current input value x is equal to 0, the ideal output value y should be:

y＝1+2+4+8+16+32+64+128+256+512＝1023。

case two: in case of non-full matching, such as memory depth of 5 and depth of cross term of 1:

y＝1+2+4+8+16+32+64+128+256＝511；

y＝1+2+4+8+16+32+64＝127。

step three: extracting output data after operation processing of a DPD processor, comparing the output data with an ideal output value, if the output data is consistent with the ideal output value, determining that the working state of the LUT is normal, and then switching to the fourth step; and if the two are not consistent, determining that the working state of the LUT is abnormal.

Assuming that the 15 th LUT in table 1 has abnormal operating conditions, the abnormal output values are:

(a) if the current input value x is equal to 1, the output data y' after the computation processing by the DPD processor is:

y′＝1+2+4+8+16+32+64+128+512+1024+2048＝3839；

(b) if the current input value x is equal to 0, the output data y' after the operation processing by the DPD processor is:

y′＝1+2+4+8+16+32+64+128+256+512＝1023。

it can be seen that, when the current input value x is 1, the output data y 'after the operation processing by the DPD processor is not consistent with the ideal output value y, the difference between the two values is y-y' ═ 4095-.

Fig. 3 is a schematic diagram of a time domain simulation result of simulated predistortion output data when full timing. It can be seen that the output value Y is 4095 when the input value X is 21 in the normal case, and 3839 when the input value X is 21 in the abnormal operation of the LUT.

y′＝1+2+4+8+16+32+64+128＝255；

y′＝1+2+4+8+16+32+64＝127。

it can be seen that, when the current input value x is 1 in the non-full case, the output data y 'after the operation processing by the DPD processor is not consistent with the ideal output value y, the difference between the two values is y-y' 511-255-256, and the LUT corresponding to the specific value 256 is the 15 th LUT in table 1 (i.e. the LUT corresponding to the memory depth of 4 and the depth of the cross term of 1), so that it can be determined that the operating state of the 15 th LUT is abnormal.

Fig. 4 is a schematic diagram of a time domain simulation result of the analog predistortion output data when the data is not full. It can be seen that the output value Y is 511 when the input value X is 19 in the normal case, and 255 when the input value X is 19 in the abnormal operation of the LUT.

The above assumptions are all the cases where the operating state of one LUT is abnormal, and the following gives the cases where the operating states of a plurality of LUTs are abnormal.

Take the case of non-full match, e.g. memory depth of 5, and cross term depth of 1 as an example:

(1) if the current input value x is equal to 1, the output data y' after the computation processing by the DPD processor is:

y′＝1+2+4+8+16+32+64+128+256＝511；

(2) if the current input value x is equal to 0, the output data y' after the operation processing by the DPD processor is:

y′＝1+2+16+32+64＝115。

it can be seen that, when the current input value x is 0, the output data y 'after the operation processing by the DPD processor is not consistent with the ideal output value y, and the difference between the two is y-y' 127-.

Step four: and calling a normal numerical value in the LUT to execute a DPD processing process.

Specifically, normal service data and a training sequence are sent to a predistortion processor, a numerical value in an LUT is updated after a DPD coefficient is calculated, and forward digital predistortion is carried out to make up for the nonlinearity and the memory characteristic of a power amplifier.

Referring to fig. 5, an embodiment of the present invention provides a digital predistortion processing apparatus, including:

a checking unit 11, configured to check an operating state of a lookup table LUT for performing digital predistortion DPD;

and the execution unit 12 is configured to, when it is determined that the LUT works normally, invoke the LUT to execute a DPD processing procedure.

Preferably, the verification unit 11 is specifically configured to:

presetting a specific value for the LUT for executing DPD;

Preferably, the checking unit 11 presets a specific value for the LUT for executing DPD in the following manner:

Preferably, when the checking unit 11 determines whether the working state of the LUT for executing DPD is normal according to the output data, it is specifically configured to:

judging whether the processed data is consistent with preset ideal data or not;

Preferably, the checking unit 11, when determining that the processed data is inconsistent with the preset ideal data, is further configured to:

In the embodiment of the present invention, each of the functional units may be implemented by a specific physical device such as a hardware processor.

As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, optical storage, and the like) having computer-usable program code embodied therein.

The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims

1. A digital predistortion processing method, the method comprising:

when the LUT works normally, calling the LUT to execute a DPD processing process;

the checking the working state of the LUT for executing DPD specifically includes:

presetting a specific value for the LUT for executing DPD;

judging whether the working state of the LUT for executing the DPD is normal or not according to the processed data;

wherein the preset specific training sequence comprises a digit sequence with 1 and 0 alternately arranged;

2. The method of claim 1, wherein the LUT for DPD execution is preset with specific values as follows:

3. The method according to claim 1, wherein determining whether the working state of the LUT for executing DPD is normal according to the processed data specifically includes:

judging whether the processed data is consistent with preset ideal data or not;

4. The method according to claim 3, wherein the preset ideal data is obtained by performing an analog DPD operation on a preset specific training sequence according to the LUT preset with the specific value under a condition that the working state of the LUT for executing DPD is normal.

5. The method of claim 3, wherein when it is determined that the processed data is inconsistent with preset ideal data, the method further comprises:

6. A digital predistortion processing apparatus, the apparatus comprising:

the execution unit is used for calling the LUT to execute a DPD processing process when the LUT is determined to work normally;

wherein the verification unit is specifically configured to:

presetting a specific value for the LUT for executing DPD;

7. The apparatus of claim 6, wherein the checking unit presets a specific value for the LUT for performing DPD as follows:

setting the numerical value in each LUT corresponding to each memory depth with even memory depth as different specific numerical value, and setting the numerical value in each LUT corresponding to each memory depth with odd memory depth as different specific numerical value.

8. The apparatus according to claim 6, wherein when the checking unit determines, according to the processed data, whether the operating state of the LUT for executing DPD is normal, the checking unit is specifically configured to:

judging whether the processed data is consistent with preset ideal data or not;

and if the LUT is consistent with the DPD, determining that the working state of the LUT is normal, otherwise, determining that the working state of the LUT for executing the DPD is abnormal.

9. The apparatus of claim 8, wherein the preset ideal data is obtained by performing an analog DPD operation on a preset specific training sequence according to the LUT preset with the specific value under a condition that the working state of the LUT for executing DPD is normal.

10. The apparatus of claim 8, wherein the checking unit, when determining that the processed data is inconsistent with preset ideal data, is further configured to: