CN107369689A - The method for manufacturing storage device - Google Patents
The method for manufacturing storage device Download PDFInfo
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- CN107369689A CN107369689A CN201610972352.2A CN201610972352A CN107369689A CN 107369689 A CN107369689 A CN 107369689A CN 201610972352 A CN201610972352 A CN 201610972352A CN 107369689 A CN107369689 A CN 107369689A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
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Abstract
There is provided herein a kind of method for manufacturing storage device.The method of the manufacture storage device comprises the following steps：Compensation layer is formed above the channel layer, wherein, the incubation time for the nucleation of the compensation layer is shorter than the incubation time of the channel layer；And perform Technology for Heating Processing for making channel layer crystallization.
Description
Technical field
The various embodiments of the disclosure are related to a kind of method for manufacturing storage device, and are made more particularly, to one kind
The method for making three-dimensional memory devices.
Background technology
Usually, storage device can be classified as volatile storage and Nonvolatile memory devices.Volatibility is deposited
Storage device can lose the data wherein stored when power supply is cut off.On the other hand, Nonvolatile memory devices are even in electricity
Source can also keep the data wherein stored when being cut off.Thus, Nonvolatile memory devices have been widely used as portable
Storage device.
Storage device can include the memory cell array for data storage, for being performed to memory cell array
Programming operation, the peripheral circuit of read operation and erasing operation and the control logic for Control peripheral circuit.
Memory cell array can include multiple memory blocks.Recently, due to the increase of integrated level, having developed has
The memory block of three-dimensional structure.Three-dimensional storage block includes vertical cell string, and each vertical cell string includes being laminated in and base
Multiple memory cells in the vertical vertical direction of plate.
Vertical cell string can be arranged between bit line and source electrode line.Each vertical cell string can include vertical-channel
(channel) layer and accumulation layer, and can couple with along the wordline of storage layer stackup.Memory cell is arranged on storage
Between layer and wordline.
The content of the invention
The various embodiments of the disclosure are deposited for a kind of electric charge for the memory cell that can improve three-dimensional memory devices
The method for storing up the manufacture storage device of capacity.
A kind of embodiment of the disclosure provides a kind of method for manufacturing storage device, and this method comprises the following steps：
Channel layer is formed on fabric；Compensation layer is formed above the channel layer, wherein, the nucleation for the compensation layer
Incubation time is shorter than the incubation time of the channel layer；And perform Technology for Heating Processing for making channel layer crystallization.
Another embodiment of the disclosure provides a kind of method for manufacturing storage device, and this method comprises the following steps：
Alternately insulating barrier and sacrifice layer between layer laminate on fabric；Formation extends perpendicularly through the interlayer insulating film and described sacrificial
The upright opening of domestic animal layer；Along the side exposed by the side surface of the upright opening of the interlayer insulating film and the sacrifice layer
Wall forms accumulation layer；Channel layer is formed along the inner surface of the accumulation layer；Formed along the inner surface of the channel layer
Compensation layer, wherein, the incubation time for the nucleation of the compensation layer is shorter than the incubation time of the channel layer；And perform use
In the Technology for Heating Processing for making the channel layer crystallization.
Another embodiment of the disclosure provides a kind of method for manufacturing storage device, and this method comprises the following steps：
Alternately insulating barrier and sacrifice layer between layer laminate on fabric；Formed through the interlayer insulating film and the sacrifice layer
Upright opening；Formed along the side wall exposed by the side surface of the upright opening of the interlayer insulating film and the sacrifice layer
Accumulation layer；Amorphous silicon layer is formed to be used as channel layer along the inner surface of the accumulation layer；Along the inner side of the channel layer
Surface forms germanium-silicon layer to be used as compensation layer；And perform Technology for Heating Processing for making channel layer crystallization.
Brief description of the drawings
Illustrative embodiments are described more fully hereinafter with now with reference to accompanying drawing；However, the exemplary implementation
Mode can implement in different forms, and should not be construed as limited to embodiment described in this paper.Phase
Instead, there is provided these embodiments be in order that the disclosure will be thorough and complete, and by the model of illustrative embodiments
Enclose and be fully conveyed to those skilled in the art.
In the accompanying drawings, for the sake of illustrating and understanding, it may be exaggerated size.It will be appreciated that when an element is referred to as
" " two elements " between " when, one element can be the sole component between the two elements, or can also deposit
In one or more intermediary elements.Throughout in full, identical reference number refers to identical element.
Fig. 1 is the diagram for illustrating the storage system according to the disclosure；
Fig. 2 is the detailed view of the memory chip shown in Fig. 1；
Fig. 3 and Fig. 4 is the stereogram for the embodiment for illustrating three-dimensional storage block；
Fig. 5 A and Fig. 5 B are the sectional views for the method for illustrating the manufacture channel layer according to embodiment of the present disclosure；
Fig. 6 A and Fig. 6 B are the sectional views for the method for illustrating the manufacture channel layer according to embodiment of the present disclosure；
Fig. 7 A, Fig. 7 B, Fig. 7 C, Fig. 7 D, Fig. 7 E, Fig. 7 F, Fig. 7 G, Fig. 7 H and Fig. 7 I are to illustrate the embodiment party according to the disclosure
The sectional view of the method for the manufacture storage device of formula；
Fig. 8 is the diagram for illustrating the storage system according to embodiment of the present disclosure；And
Fig. 9 is the diagram for illustrating the computing system according to embodiment of the present disclosure.
Embodiment
Hereinafter, embodiment is more fully described with reference to the accompanying drawings.Herein with reference to as embodiment (in and
Between structure) the section example of schematic example embodiment is described.Therefore, it is contemplated that from for example as manufacturing technology
And/or the change of the shape of the example of the result of tolerance limit.Therefore, embodiment should not be construed as limited to area illustrated herein
The given shape in domain, but the form variations for example as caused by manufacture can be included.In the accompanying drawings, for the sake of clarity, may
Exaggerate the length and size in layer and region.Identical reference represents identical element in accompanying drawing.
Such as term of " first " and " second " can be used for describing various assemblies, but they should not limit various assemblies.
Those terms are only used for the purpose for mutually distinguishing a component with other components.For example, spirit and scope of the present disclosure are not being departed from
In the case of, first assembly can be referred to as the second component, and the second component can be referred to as first assembly etc..Moreover,
"and/or" can include any one or combination in mentioned component.
As long as moreover, not referred to especially in sentence, singulative can also include plural form.Moreover, in specification
The "comprises/comprising" used or " include/include " represent there is or add one or more components, step, operation
And element.
Moreover, unless otherwise defined, what is otherwise used in this specification includes all terms tool of technology and scientific terminology
There is the implication identical implication being generally understood with various equivalent modifications.Term defined in usually used dictionary should
The implication identical implication for being interpreted as having and being explained under the background of association area, and it is unless another in this manual
It is clearly defined outside, otherwise the term should not be interpreted as having the implication of idealization or overly formal.
It should also be noted that in this manual, " connection/connection " refers to that a component not only directly couples another group
Part, and another component can also be coupled indirectly by intermediate module.On the other hand, " it is directly connected to/directly connection " and refers to one
Individual component directly couples another component, and intermediate module is not present.
Fig. 1 is the diagram for illustrating the storage system according to the disclosure.
Reference picture 1, storage system 1000 can include being configured to store the storage device 1100 of data and for controlling
The storage control 1200 of storage device 1100.
Storage device 1100 can include multiple memory chips 1110.Memory chip 1110 can include DDR
SDRAM (double data speed synchronous dynamic RAM), LPDDR4 (low-power Double Data Rate 4) SDRAM,
GDDR (graphics double data rate) SDRAM, LPDDR (low-power DDR), RDRAM (Rambus dynamic random access memory)
Or flash memory.In following embodiment, explanation by way of example is included to the storage of NAND flash
Device chip 1110.
Storage control 1200 can control all operationss of storage device 1100, and can be in response to from main frame 2000
The order of reception, order, address and the data for controlling storage device 1100 are exported to storage device 1100, or from storage
Device 1100 receives data.
Main frame 2000 can pass through such as PCI-E (periphery component interconnection-quick), ATA (Advanced Technology Attachment), SATA
(serial ATA), PATA (Parallel ATA) or SAS (serial attached SCSI) interface protocol and communicated with storage system 1000.
Fig. 2 is the detailed view of the memory chip 1110 shown in Fig. 1.
Reference picture 2, memory chip 1110 can include data storage memory cell array 110, can to storage
Device cell array 110 perform programming operation, read operation or erasing operation peripheral circuit 120 and can be with Control peripheral circuit
120 control logic 130.
Memory cell array 110 can be including the substantially first memory block with same configuration to K memories
Block (K is positive integer).First memory block to K memory blocks can be attached to First partial line LL1 to K parts respectively
Line LLK.Each memory block in first memory block to K memory blocks can with three-dimensional structure and substantially with
Identical constructs.
Peripheral circuit 120 can include voltage generation circuit 21, row decoder 22, page buffer 23, column decoder 24
With input/output circuitry 25.
Voltage generation circuit 21 can produce the operating voltage Vop with various level in response to operation signal OPSIG,
And caused operating voltage Vop is optionally applied to global lines.If voltage generation circuit 21 receives and program,
Read or erasing operation corresponding to operation signal OPSIG, then voltage generation circuit 21 can produce for it is described programming, read or
The operating voltage Vop with various level needed for erasing operation.
Row decoder 22 in response to row address RADD, to First partial line LL1 to K local lines LLK among it is coupled
Local line to selected memory block sends operating voltage Vop.For example, row decoder 22 is attached to electricity by global lines
Generation circuit 21 is pressed, and the operation electricity received by global lines is sent to the local line for being attached to selected memory block
Press Vop.
Page buffer 23 is attached to memory cell array 110 by bit line.In response to page buffer control signal
Bit line is precharged to positive voltage by PBSIGNALS, page buffer 23, during programming or read operation with selected storage
Device block exchanges data, or provisionally stores received data.
Column decoder 24 exchanges number in response to column address CADD between page buffer 23 and input/output circuitry 25
According to DATA.
The order CMD received from storage control 1200 and address AD D can be sent to control by input/output circuitry 25
Logic 130, the data received from external device (ED) are sent to column decoder 24, or the data received from column decoder 24 are defeated
Go out to external device (ED).
Control logic 130 carrys out Control peripheral circuit 120 in response to order CMD and address AD D.For example, control logic 130 can
In response to ordering CMD and address AD D, to export the operation signal OPSIG, row address RADD, page for Control peripheral circuit 120
Face buffer control signal PBSIGNALS and column address CADD.
Above-mentioned each first memory block with three-dimensional structure substantially constructs to K memory blocks with identical.
Therefore, any one memory block in first memory block to K memory blocks is illustrated by by way of example.
Fig. 3 and Fig. 4 is the stereogram for the embodiment for illustrating three-dimensional storage block.
Reference picture 3, there is the memory block of three-dimensional structure can include vertically (Z-direction) being disposed on substrate
And it is implemented as the string ST of I shapes.String ST can be arranged between bit line BL and source electrode line SL.Aforementioned structure can be
Refer to BiCS (position cost is expansible) structure.For example, when source electrode line SL is horizontally formed at surface, there is BiCS structures
String ST can vertically be formed on above source electrode line SL.More specifically, string ST can include being disposed in first party
On to (that is, Y-direction) and it is laminated into drain selection line SSL, the wordline WL being spaced apart from each other and drain electrode selection line DSL.Source electrode
Selection line SSL, wordline WL and drain electrode selection line DSL quantity are not limited to the quantity shown in Fig. 3, and can be filled according to storage
Put and change.String ST can include the vertical-channel for extending perpendicularly through drain selection line SSL, wordline WL and the selection line DSL that drains
The layer CH and vertical furrow channel layer CH with being stretched out upwards from drain electrode selection line DSL upper end is contacted and is disposed in vertical
Bit line BL in the second direction (that is, X-direction) of first direction (that is, Y-direction).Memory cell can be formed on wordline
Between WL and vertical furrow channel layer CH.Contact plunger CT can also be formed between bit line BL and vertical furrow channel layer CH.Joined
It is connected among different string ST memory cell, a page can be referred to by being attached to the storage stack unit of same wordline
Face.
Reference picture 4, vertically (that is, Z-direction) quilt can be included by being implemented as the memory block of three-dimensional structure
It is arranged on substrate and is implemented as the string ST_S and ST_D of U-shaped.String ST_S and ST_D can include being attached to source
The polar curve SL source electrode string ST_S and drain electrode string ST_D for being attached to bit line BL.Source electrode string ST_S can pass through with drain electrode string ST_D
Pipe trench road PG is coupled to each other and is formed U-shaped.Pipe trench road PG can be formed in pipeline PL.Specifically, source electrode string ST_
S is disposed vertically between source electrode line SL and pipeline PL.Drain electrode string ST_D be disposed vertically on bit line BL and pipeline PL it
Between.Aforementioned structure can refer to P-BiCS (tubular position cost is expansible) structure.
More specifically, drain electrode string ST_D can include being disposed on first direction (that is, Y-direction) and tegillum builds up that
This wordline WL spaced apart with drain electrode selection line DSL and extend perpendicularly through wordline WL and drain electrode selection line DSL drain electrode it is vertical
Channel layer D_CH.Source electrode string ST_S can include being disposed on first direction (that is, Y-direction) and tegillum builds up and is spaced
The wordline WL and drain selection line SSL that open and the source electrode vertical furrow channel layer for extending perpendicularly through wordline WL and drain selection line SSL
S_CH.Draining vertical furrow channel layer D_CH and source electrode vertical furrow channel layer S_CH can be by the pipe trench channel layer PG in pipeline PL each other
Connection.Bit line BL can be contacted simultaneously with the drain electrode vertical furrow channel layer D_CH stretched out upwards from drain electrode selection line DSL upper end
And it is disposed in the second direction (that is, X-direction) vertical with first direction (that is, Y-direction).Memory cell can be formed
Between wordline WL and vertical furrow channel layer S_CH or D_CH.
Each channel layer in reference picture 3 and channel layer CH, D_CH, S_CH and PG of Fig. 4 descriptions can be by polysilicon layer
Formed.Electric current in string can be changed according to channel layer CH, D_CH, S_CH and PG impedance, and specifically, can basis
Channel layer CH, D_CH, S_CH and PG crystallite dimension come change string in electric current.For example, channel layer CH, D_CH, S_CH and PG
Crystallite dimension increase more, then channel layer CH, D_CH, S_CH and PG impedance is lower.Thus, enter to storage arrangement
During row operation, flowing through the electric current of memory cell can increase.In embodiment of the present disclosure, a kind of energy has been set forth below
Enough increase the manufacture method of the crystallite dimension of channel layer.
Fig. 5 A and Fig. 5 B are the sectional views for the method for illustrating the manufacture channel layer according to embodiment of the present disclosure.
Reference picture 5A, channel layer 52 are formed on fabric 50.Fabric 50 can be by semiconductor substrate, storage
Device layer, conductive layer or insulating barrier are formed.Channel layer 52 can be formed by amorphous silicon layer.Channel layer 52 can not tied in silicon layer
It is formed at brilliant temperature.For example, channel layer 52 can be formed at a temperature of scope is from 500 DEG C to 600 DEG C.
Then, compensation layer 54 is formed on channel layer 52.Compensation layer 54 can be used for the crystal grain chi for increasing channel layer 52
It is very little.Incubation time (incubation time) for being nucleated to compensation layer 54 is shorter than the incubation time of channel layer 52.Example
Such as, compensation layer 54 can be formed by germanium-silicon layer.The concentration increase of germanium must be bigger in SiGe, the raceway groove during following crystallization process
The crystallite dimension can increase of layer 52 must be bigger.However, increase with the crystallite dimension of channel layer 52, the form of channel layer 52
Feature may degenerate.In view of this point, the concentration of germanium in germanium-silicon layer can be controlled.For example, the concentration of germanium can have from
20% to 80% scope.
Reference picture 5B, performed after compensation layer 54 is formed on channel layer 52 for being crystallized to channel layer 52
Crystallization process.Crystallization process can be implemented by Technology for Heating Processing.The crystallite dimension of channel layer 52 can be according to heat
The temperature and time of handling process and change.Therefore, the temperature and time of Technology for Heating Processing is suitably adapted to increase raceway groove
The crystallite dimension of layer 52.For example, during Technology for Heating Processing, temperature can have a scope from 350 DEG C to 650 DEG C, and when
Between can have scope from two hours to four hours.Furthermore, it is possible in nitrogen (N2) Technology for Heating Processing is performed under environment.
If performing Technology for Heating Processing under these conditions, compensation layer 54 is more quickly crystallized and become than channel layer 52
Into crystallization compensation layer 54a.When compensation layer 54 becomes to crystallize compensation layer 54a, crystallization compensation layer 54a can be by compensation layer 54
Surface on grow crystal grain and be formed.When crystal grain is growing on the surface of compensation layer 54, channel layer 52 can pass through extension
Grow and become crystalline channel layer 52a.
If performing crystallization process under these conditions, crystalline channel layer 52a crystal grain GR size can be formed
Obtain larger.
Fig. 6 A and Fig. 6 B are the sectional views for the method for illustrating the manufacture channel layer according to another embodiment of the disclosure.
Reference picture 6A, crystal seed layer 61 and channel layer 62 are formed on fabric 60.Fabric 60 can be by partly leading
Structure base board, memory layer, conductive layer or insulating barrier are formed.Crystal seed layer 61 can promote the growth of channel layer 62, and can be
It is formed on before forming channel layer 62 on the surface of fabric 60.Crystal seed layer 61 can be by identical with the material of channel layer 62
Material formed.Crystal seed layer 61 can be formed at various temperatures, and for example, within the temperature range of from 350 DEG C to 400 DEG C
It is formed.Channel layer 62 can be formed by amorphous silicon layer.Channel layer 62 can be formed at various temperatures, and for example, in model
It is formed at a temperature of enclosing from 500 DEG C to 600 DEG C.
Then, compensation layer 64 is formed on channel layer 62.Compensation layer 64 can be used for the crystal grain chi for increasing channel layer 62
It is very little.Incubation time for being nucleated to compensation layer 64 is shorter than the incubation time of channel layer 62.For example, compensation layer 64 can be by
Germanium-silicon layer is formed.The concentration of germanium can have the scope from 20% to 80% in germanium-silicon layer.The concentration increase of germanium must be bigger, under
The crystallite dimension of channel layer 62 is increased by bigger during the crystallization process in face.However, increase with the concentration of germanium, channel layer 62
Morphological feature may degenerate.In view of this point, the temperature and time of following crystallization process will be controlled.
Reference picture 6B, performed after compensation layer 64 is formed on channel layer 62 for being crystallized to channel layer 62
Crystallization process.The crystallization process can perform according to the crystallization process identical mode described with reference picture 5B；Therefore, will
Description is omitted.Crystalline channel layer 62a crystal grain GR size can by referring to Fig. 5 B describe crystallization process and by
Formed larger.
Reference picture 5A, Fig. 5 B, Fig. 6 A and Fig. 6 B description crystallization process can be applied to manufacture two-dimensional storage device or
The method of three-dimensional memory devices.
Fig. 7 A to Fig. 7 I are the sectional views for the method for illustrating the manufacture three-dimensional memory devices according to embodiment of the present disclosure.
Reference picture 7A, interlayer insulating film 71a to 71d and sacrifice layer 72a to 72c are alternately laminated in fabric 70
On.Fabric 70 can include semiconductor substrate, insulating barrier or pipe grid.Each layer in interlayer insulating film 71a to 71d can be with
Formed by oxide skin(coating).Each layer in sacrifice layer 72a to 72c can be formed by nitride layer.The interlayer insulating film 71a of stacking
It can be changed to 71d and sacrifice layer 72a to 72c quantity according to storage device.
Reference picture 7B, upright opening VH are formed to extend perpendicularly through interlayer insulating film 71a to 71d and sacrifice layer 72a extremely
72c.For example, upright opening VH can be formed according to following this mode：By in the position correspondence with upright opening VH to be formed
The mask pattern with opening is formed on interlayer insulating film 71a to 71d and sacrifice layer 72a to 72c top in its region, and
And then perform etch process.
Reference picture 7C, accumulation layer ML along interlayer insulating film 71a to 71d and sacrifice layer 72a to 72c be exposed on it is vertical
Side wall on hole VH side surface is formed.Accumulation layer ML can be formed cylindrical shape in upright opening VH.Accumulation layer ML can
With including barrier layer 73, electric charge capture layer 74 and tunnel insulation layer 75.Barrier layer 73 can be formed by oxide skin(coating).Electric charge capture
Layer 74 can be formed by nitride layer, and tunnel insulation layer 75 can be formed by oxide skin(coating).Etch process can be performed
To expose the fabric 70 at upright opening VH bottom.
Reference picture 7D, channel layer 76 and compensation layer 77 are one after the other formed along accumulation layer ML inner surface.Channel layer
76 and compensation layer 77 in each layer can be formed cylindrical shape along accumulation layer ML inner surface in upright opening VH.Ditch
Channel layer 76 can be formed by amorphous silicon layer.For example, channel layer 76 can be formed at a temperature of silicon layer is not crystallized.One
In kind embodiment, channel layer 76 can be formed at a temperature of scope is from 500 DEG C to 600 DEG C.For promoting channel layer 76
The crystal seed layer (not shown) of growth can also be formed before channel layer 76 is formed along accumulation layer ML inner surface.Can be with
The method to form crystal seed layer (not shown) is performed according to the method identical mode described with reference picture 6A, and therefore, will
Description is omitted.Compensation layer 77 can be used for the crystallite dimension for increasing channel layer 76 and can be by with than channel layer 76
The material of shorter incubation time incubation time formed.For example, compensation layer 77 can be formed by germanium-silicon layer.Germanium in germanium-silicon layer
Concentration increase must be bigger, and the crystallite dimension can increase of channel layer 76 must be bigger during following crystallization process.However, with
The crystallite dimension increase of channel layer 76, the morphological feature of channel layer 76 may degenerate.In view of this point, SiGe can be controlled
The concentration of germanium in layer, and for example, the concentration of germanium can have the scope from 20% to 80%.Moreover, forming compensation
After layer 77, inner liner 78 can also be formed along the inner surface of compensation layer 77.Inner liner 78 can be formed by oxide skin(coating).
Etch process can be performed to expose the fabric 70 at upright opening VH bottom.
Reference picture 7E, the crystallization process for being crystallized to channel layer 76 are performed.Crystallization process can by heat at
Science and engineering skill implements.During Technology for Heating Processing, temperature and time can contemplate the crystallite dimension and form of channel layer 76
Feature is adjusted.For example, can be within two hours to four hours in nitrogen (N2) under environment from 350 DEG C to 650
Technology for Heating Processing is performed within the temperature range of DEG C.If performing Technology for Heating Processing under these conditions, channel layer 76 is crystallized
And become crystalline channel layer 76a.Crystalline channel layer 76a is used as the raceway groove CH of string.Specifically, if in above-mentioned condition
Lower execution Technology for Heating Processing, then increase the size for the crystal grain to form crystalline channel layer 76a so that raceway groove CH resistance can be reduced
It is anti-.When inner liner 78 is formed on the side surface of compensation layer 77, inner liner 78 can prevent from wrapping during Technology for Heating Processing
The germanium included in compensation layer 77 is moved out of from compensation layer 77.
Reference picture 7F, after crystalline channel layer 76a has been formed, compensation layer (77 in Fig. 7 E) can be unnecessary
's.Therefore, etch process can be performed to remove compensation layer 77., can during etch process if having formed inner liner 78
To remove inner liner 78 and compensation layer 77 together.Etch process can be implemented by wet etching process.It can use
Etch-rate with SiGe (SiGe) performs wet method erosion higher than the etchant of the etching selectivity of the etch-rate of silicon (Si)
Carving technology.It is, for example, possible to use silicon is about 1 to the etching selectivity of SiGe：50 etchant.
Reference picture 7G, vertically insulated layer 79 are formed so that the inside for being formed as columnar crystalline channel layer 76a is empty
Between (in other words, upright opening VH other regions) be filled with vertically insulated layer 79.Vertically insulated layer 79 can be by oxide skin(coating)
Formed.
Reference picture 7H, sacrifice layer (72a to 72c in Fig. 7 G) are removed so that in interlayer insulating film 71a between 71d
Form recess.
Reference picture 7I, interlayer insulating film 71a is formed on to each recess between 71d and is filled with conductive layer 80.Lead
Electric layer 80 can be formed by tungsten to be used as wordline WL.
Fig. 8 is the diagram for illustrating the storage system 3000 according to embodiment of the present disclosure.
Reference picture 8, storage system 3000 can include the storage device 1100 and control storage device 1100 of data storage
Storage control 1200.Communication between the control main frame 2000 of storage control 1200 and storage device 1100.Storage control
Device 1200 can include buffer storage 1210, CPU 1220, SRAM 1230, HPI 1240, ECC (error correction circuit)
1250 and memory interface 1260.
When storage control 1200 controls storage device 1100, the provisionally data storage of buffer storage 1210.CPU
1220 can be to the data exchange executive control operation of storage control 1200.SRAM 1230 is used as CPU's 1220
Working storage.HPI 1240 can include the data exchange agreement for being attached to the main frame 2000 of storage system 3000.
ECC 1250 as error correction unit can detect and correct the mistake in the data for being included in and being read from storage device 1100.Deposit
Storage interface 1260 can be connected with the interface of storage device 1100.Although not illustrated in Fig. 8, storage system 3000 can also wrap
Include the ROM (not shown) for storing coded data to be connected with the interface of main frame 2000.
Can use can include computer, UMPC according to the targeted main frame 2000 of the storage system 3000 of the disclosure
(super mobile PC), work station, net book, PDA (personal digital assistant), portable computer, online flat board computer, radio
Words, mobile phone, smart phone, digital camera, digital audio recorder, digital audio-frequency player, digital picture logger, number
Word picture players, digital video recorder, video frequency player ,/the dress of receive information can be sent in the wireless context
Put or for forming the various devices of home network.
Fig. 9 is the diagram for illustrating the computing system 4000 according to embodiment of the present disclosure.
Reference picture 9, computing system 4000 can include storage device 1100, the storage control for being electrically coupled to bus
1200th, microprocessor 4100, user interface 4200 and modem 4400.When computing system 4000 is mobile device,
Battery 4300 can additionally be included to provide the operating voltage of computing system 4000.Although being not shown in the drawings, calculate
System 4000 can also include application chip group, camera image processor (CIS), mobile DRAM etc..The He of storage control 1200
Storage device 1100 can form SSD (solid-state drive/disk).
Computing system 4000 of the various forms of encapsulation to install according to the disclosure can be used.It is it is, for example, possible to use all
Such as PoP (stacked package), ball grid array (BGA), wafer-level package (CSP), plastic leaded chip carrier (PLCC), plastics biserial
Straight cutting encapsulation (PDIP), the nude film of Waffle components, the nude film of wafer format, chip on board (COB), the encapsulation of ceramic double-row straight cutting
(CERDIP), plastics measurement quad flat package (MQFP), slim quad flat package (TQFP), small profile (SOIC), diminution
Outline packages (SSOP), Thin Small Outline (TSOP), system in package (SIP), multi-chip package (MCP), wafer scale manufacture envelope
Dress (WFP) and the packing forms of wafer-level processes stacked package (WSP) install computing system 4000.
As described above, in the three-dimensional memory devices according to the disclosure, the crystallite dimension of channel layer is increased, so as to
The electric current of raceway groove is flowed through in increase.Therefore, the electrical characteristics of storage device can be improved.
Illustrative embodiments, and particular term despite the use of, but these particular term quilts have been disclosed herein
Using and will be understood as that only there is general and descriptive meaning, rather than limitation purpose.In some instances,
Such as those of ordinary skill in the art will become apparent to, from the submission of the application, unless specifically indicate in addition, otherwise with
Particular implementation about the feature, characteristic and/or the element that describe can be used individually or with other embodiment party
Formula about the feature, characteristic and/or the element that describe use in combination.Therefore, it will be appreciated by those skilled in the art that not
In the case of departing from the spirit and scope of the present invention as illustrated in appended claims, it can make in form and details
Various changes.
The cross reference of related application
This application claims the Korean Patent Application No. 10-2016-0058347 submitted on May 12nd, 2016 priority,
Entire contents are incorporated herein by reference.
Claims (20)
1. a kind of method for manufacturing storage device, this method comprise the following steps：
Channel layer is formed on fabric；
Compensation layer is formed above the channel layer, wherein, the incubation time for the nucleation of the compensation layer is shorter than the ditch
The incubation time of channel layer；And
Perform the Technology for Heating Processing for making the channel layer crystallization.
2. according to the method for claim 1, wherein, the channel layer is formed by amorphous silicon layer.
3. according to the method for claim 1, wherein, the compensation layer is formed by germanium-silicon layer.
4. according to the method for claim 3 comprising the concentration of germanium in the germanium-silicon layer have about from 20% to
80% scope.
5. according to the method for claim 1, wherein, in the range of about performing at a temperature of from 350 DEG C to 650 DEG C at the heat
Science and engineering skill.
6. according to the method for claim 1, wherein, the Technology for Heating Processing is performed in a nitrogen environment.
7. according to the method for claim 1, this method is further comprising the steps of：
Before the step of forming the channel layer, crystal seed layer is formed on the fabric.
8. according to the method for claim 7, wherein, the crystal seed layer is by the material identical material shape with the channel layer
Into.
9. a kind of method for manufacturing storage device, this method comprise the following steps：
Alternately insulating barrier and sacrifice layer between layer laminate on fabric；
Form the upright opening for extending perpendicularly through the interlayer insulating film and the sacrifice layer；
Formed and deposited along the side wall exposed by the side surface of the upright opening of the interlayer insulating film and the sacrifice layer
Reservoir；
Channel layer is formed along the inner surface of the accumulation layer；
Compensation layer is formed along the inner surface of the channel layer, wherein, the incubation time for the nucleation of the compensation layer is short
In the incubation time of the channel layer；And
Perform the Technology for Heating Processing for making the channel layer crystallization.
10. according to the method for claim 9, wherein, the channel layer is formed by amorphous silicon layer.
11. according to the method for claim 9, wherein, the compensation layer is formed by germanium-silicon layer.
12. according to the method for claim 11 comprising the concentration of the germanium in the germanium-silicon layer has about from 20%
To 80% scope.
13. according to the method for claim 9, wherein, in the range of about performing the heat at a temperature of from 350 DEG C to 650 DEG C
Handling process is up to two hours to four hours.
14. according to the method for claim 9, wherein, the Technology for Heating Processing is performed in a nitrogen environment.
15. according to the method for claim 9, this method is further comprising the steps of：
After the step of performing the Technology for Heating Processing, the etch process for removing the compensation layer is performed.
16. according to the method for claim 15, wherein, the etch process is including the use of the etching with the compensation layer
Speed is higher than the wet etching process that the etchant of the etching selectivity of the etch-rate of the channel layer performs.
17. according to the method for claim 9, this method is further comprising the steps of：
Before the step of forming the channel layer, crystal seed layer is formed along the inner surface of the accumulation layer.
18. according to the method for claim 17, wherein, the crystal seed layer is by the material identical material with the channel layer
Formed.
19. a kind of method for manufacturing storage device, this method comprise the following steps：
Alternately insulating barrier and sacrifice layer between layer laminate on fabric；
Formed through the interlayer insulating film and the upright opening of the sacrifice layer；
Formed and deposited along the side wall exposed by the side surface of the upright opening of the interlayer insulating film and the sacrifice layer
Reservoir；
Amorphous silicon layer is formed to be used as channel layer along the inner surface of the accumulation layer；
Germanium-silicon layer is formed to be used as compensation layer along the inner surface of the channel layer；And
Perform the Technology for Heating Processing for making the channel layer crystallization.
20. according to the method for claim 19, this method is further comprising the steps of：
After the step of performing the Technology for Heating Processing, the etch process for removing the compensation layer is performed.
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| CN201610972352.2A CN107369689A (en) | 2016-05-12 | 2016-11-03 | The method for manufacturing storage device |
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| KR10-2016-0058347 | 2016-05-12 | ||
| KR1020160058347A KR20170127785A (en) | 2016-05-12 | 2016-05-12 | Manufacturing method of memory device |
| CN201610972352.2A CN107369689A (en) | 2016-05-12 | 2016-11-03 | The method for manufacturing storage device |
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| CN107369689A8 CN107369689A8 (en) | 2018-02-23 |
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