CN107359947A - Circuit delay self-test device and system - Google Patents

Circuit delay self-test device and system Download PDF

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Publication number
CN107359947A
CN107359947A CN201610978228.7A CN201610978228A CN107359947A CN 107359947 A CN107359947 A CN 107359947A CN 201610978228 A CN201610978228 A CN 201610978228A CN 107359947 A CN107359947 A CN 107359947A
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CN
China
Prior art keywords
signal
analog signal
main control
connection end
control chip
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Granted
Application number
CN201610978228.7A
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Chinese (zh)
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CN107359947B (en
Inventor
李东声
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Tendyron Corp
Tendyron Technology Co Ltd
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Tendyron Technology Co Ltd
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Application filed by Tendyron Technology Co Ltd filed Critical Tendyron Technology Co Ltd
Priority to CN201610978228.7A priority Critical patent/CN107359947B/en
Priority to EP17867642.5A priority patent/EP3537631B1/en
Priority to US16/346,530 priority patent/US10659180B2/en
Priority to PCT/CN2017/100212 priority patent/WO2018082391A1/en
Publication of CN107359947A publication Critical patent/CN107359947A/en
Application granted granted Critical
Publication of CN107359947B publication Critical patent/CN107359947B/en
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B17/00—Monitoring; Testing
    • H04B17/30—Monitoring; Testing of propagation channels
    • H04B17/309—Measuring or estimating channel quality parameters
    • H04B17/364—Delay profiles

Abstract

The present invention provides circuit delay self-test device and system, wherein, circuit delay self-test device includes：First communication interface, for receiving the first analog signal；Receiving circuit module, for carrying out first processing the first data signal of generation to the first analog signal；Main control chip, the second analog signal is generated for carrying out second processing to the first data signal；First switch module, for when main control chip finishes receiving the first data signal, the first not moved end and the first connection end is disconnected, and turn on the first not moved end and second connection end；Main control chip, it is additionally operable to when first moved end does not turn on second connection end, the second analog signal is sent to receiving circuit module；Receiving circuit module, it is additionally operable to carry out the second analog signal first processing the second data signal of generation；Main control chip, be additionally operable to determine receiving circuit module circuit delay for receive the second data signal at the time of and send the second analog signal at the time of between difference.

Description

Circuit delay self-test device and system
Technical field
The present invention relates to circuit delay detection field, more particularly to circuit delay self-test device and system.
Background technology
At present, near-field communication modes are applied to every field (such as pay), using near-field communication modes (for example, RFID, NFC, infrared or bluetooth etc.) the device A that is communicated and device B there may be potential safety hazard, for example, as shown in figure 1, The data channel that device A and device B is established is by third-party involvement so that the data in whole communication process are not known in legal both sides In the case of feelings, equipment that the other end is all just arrived at via third party ultimately results in the leakage of data.
At present, can whether communication data be held as a hostage between judgment means A and device B by the following method：Device A is to device After B sends command signal, device A is just waiting reception device B response signal, and device A sends a command signal to reception certainly Time to device B response signal is the stand-by period, as long as the stand-by period is within preset time, then it is assumed that device A with Communication data between device B is not kidnapped by third party.
But the device B response signal that device A is received is analog signal, i.e., the analog signal that device A is received is Response signal after response data modulation, after device A receives response signal, as shown in Fig. 2 first having to by receiving circuit pair The response signal received is demodulated generation response data, but receiving circuit is present to filter out the low of high frequency signal components Bandpass filter, there is circuit delay in low pass filter and the circuit delay be can not ignore relative to the stand-by period.Because device A is obtained Response data is taken to be handled by the main control chip in device A, so, device A can accurately obtain response data by main control chip Time, in the case where receiving circuit has circuit delay, device A obtains the time of response data and receives response signal Time can not be considered identical, and device A still can not accurately obtain the time for receiving response signal.To accurately measure dress A stand-by period is put, needs a kind of method for the circuit delay for measuring receiving circuit badly.
The content of the invention
One of present invention seek to address that above mentioned problem/.
It is a primary object of the present invention to provide a kind of circuit delay self-test device；
Another object of the present invention is to provide another circuit delay self-test device；
Another object of the present invention is to provide a kind of circuit delay self-check system.
To reach above-mentioned purpose, what technical scheme was specifically realized in：
One aspect of the present invention provides a kind of circuit delay self-test device, including：Main control chip, the first communication interface, First switch module and receiving circuit module, wherein, main control chip comprises at least：First signal output part and signal input part； First switch module includes：First not moved end, the first connection end and second connection end；First not moved end and receiving circuit module electricity Connection；First connection end electrically connects with the first communication interface；Second connection end electrically connects with the first signal output part；First communication Interface, sent for when first moved end does not turn on the first connection end, receiving the first analog signal, and to receiving circuit module First analog signal；Receiving circuit module, for receiving the first analog signal, and the first processing is carried out to the first analog signal and is given birth to The first data signal is sent into the first data signal, and to the signal input part of main control chip；Main control chip, for receiving first Data signal, and second processing is carried out to the first data signal and generates the second analog signal；First switch module, in master control When chip finishes receiving the first data signal, the first not moved end and the first connection end is disconnected, and turns on the first not moved end and second Connection end；Main control chip, it is additionally operable to when first moved end does not turn on second connection end, by the first signal output part to reception Circuit module sends the second analog signal；Receiving circuit module, it is additionally operable to receive the second analog signal and to the second analog signal First processing the second data signal of generation is carried out, the second data signal and the first data signal are identical signal；Main control chip, It is additionally operable to receive the second data signal, and obtained for the first processing time T1, the first processing time T1 is the second data signal of reception At the time of and at the time of send the second analog signal between difference, and determine the circuit delay of receiving circuit module at first Manage time T1.
In addition, also include：Second switch module, transtation mission circuit module and the second communication interface, wherein, second switch module Including：Second not moved end, the 3rd connection end and the 4th connection end；Second connection end electrically connects specific bag with the first signal output part Include：Second connection end electrically connects with the 3rd connection end；3rd connection end with second not moved end turn on；Second not moved end with first letter The electrical connection of number output end；4th connection end electrically connects with transtation mission circuit module；Second switch module, for being received in main control chip Before first data signal, conducting second not moved end and the 4th connection end, it is additionally operable to receive the first numeral letter in main control chip After number, the second not moved end and the 4th connection end is disconnected, and turns on the second not moved end and the 3rd connection end；Main control chip, also use In before the first communication interface receives the first analog signal, the 3rd analog signal is sent to transtation mission circuit module；Transtation mission circuit Module, for receiving the 3rd analog signal and the 3rd processing the 4th analog signal of generation being carried out to the 3rd analog signal, and pass through Second communication interface is sent out the 4th analog signal, wherein, the first analog signal fills to receive the response of the 4th analog signal Put and fourth process generation is carried out to the 4th analog signal.
In addition, also include：Transtation mission circuit module and the second communication interface；Main control chip also includes：Secondary signal output end； One end of transtation mission circuit module electrically connects with secondary signal output end, and the other end electrically connects with the second communication interface；Main control chip, It is additionally operable to before the first communication interface receives the first analog signal, is sent by secondary signal output end to transtation mission circuit module 3rd analog signal；Transtation mission circuit module, given birth to for receiving the 3rd analog signal and the 3rd processing being carried out to the 3rd analog signal The 4th analog signal is sent out into the 4th analog signal, and by the second communication interface, wherein, the first analog signal is reception The answering device of 4th analog signal carries out fourth process generation to the 4th analog signal.
In addition, also include：Control terminal；Control terminal electrically connects with first switch module；Main control chip, for finishing receiving During the first data signal, control signal is sent to control terminal；Control terminal, for upon the reception of control signals, control first to be opened Close module and disconnect the first not moved end and the first connection end, and control first switch module conducting first moved end is not connected with second End.
In addition, main control chip also includes：Control terminal；Control terminal, electrically connected with first switch module and with second switch mould Block electrically connects；Main control chip, for when finishing receiving the first data signal, control signal to be sent to control terminal；Control terminal, use In upon the reception of control signals, control first switch module disconnects the first not moved end and the first connection end, and control first to open Close module the first not moved end and second connection end of conducting, and control second switch module disconnect second not moved end be connected with the 4th End, and control second switch module conducting second not moved end and the 3rd connection end.
In addition, main control chip, is additionally operable to obtain second processing time T2, second processing time T2 believes to receive the first numeral Number at the time of and to transtation mission circuit module send three analog signals at the time of between difference；When being additionally operable to judge second processing Between time difference between T2 and the first processing time T1 whether be less than preset value, be then determine circuit delay self-test device with Communication data between answering device is not held as a hostage.
Another aspect of the present invention provides another circuit delay self-test device, including：Main control chip, the first communication connect Mouth, first switch module, receiving circuit module and modulation module, wherein, main control chip comprises at least：First signal output part and Signal input part；First switch module includes：First not moved end, the first connection end and second connection end；Modulation module at least wraps Include：Modulated signal input and modulated signal output end；Modulated signal input electrically connects with the first signal output part；First is not Moved end electrically connects with receiving circuit module；First connection end electrically connects with the first communication interface；Second connection end and modulated signal Output end electrically connects；First communication interface, for when first moved end does not turn on the first connection end, receiving the first simulation letter Number, and send simulation No. the first to receiving circuit module；Receiving circuit module, for receiving the first analog signal, and to first Analog signal carries out first processing the first data signal of generation, and sends the first numeral to the signal input part of main control chip and believe Number；Main control chip, the first data signal is sent for receiving the first data signal, and to modulation module；First switch module, use In when main control chip finishes receiving the first data signal, the first not moved end and the first connection end, and it is motionless to turn on first is disconnected End and second connection end；Modulation module, generation second is modulated for receiving the first data signal, and to the first data signal Analog signal, and the second analog signal is sent to receiving circuit module by modulated signal output end；Receiving circuit module, also use In receive the second analog signal and to the second analog signal carry out first processing generation the second data signal, the second data signal with First data signal is identical signal；Main control chip, it is additionally operable to receive the second data signal, and obtained for the first processing time T1, the first processing time T1 be receive the second data signal at the time of and send the first data signal at the time of between difference, And determine that the circuit delay of receiving circuit module is very first time difference T1.
In addition, also include：Second switch module, transtation mission circuit module and the second communication interface, wherein, second switch module Including：Second not moved end, the 3rd connection end and the 4th connection end；Second connection end electrically connects specific bag with modulated signal output end Include：Second connection end electrically connects with the 3rd connection end；3rd connection end with second not moved end turn on；Second not moved end and modulated letter The electrical connection of number output end；4th connection end electrically connects with transtation mission circuit module；Second switch module, for being received in main control chip Before first data signal, conducting second not moved end and the 4th connection end, it is additionally operable to receive the first numeral letter in main control chip After number, the second not moved end and the 4th connection end is disconnected, and turns on the second not moved end and the 3rd connection end；Main control chip, also use In before the first communication interface receives the first analog signal, the 3rd data signal is sent to modulation module；Modulation module, also use In receiving the 3rd data signal, and the 3rd analog signal of generation is modulated to the 3rd data signal, and to transtation mission circuit module Send the 3rd analog signal；Transtation mission circuit module, for receiving the 3rd analog signal and being carried out to the 3rd analog signal at the 3rd Reason the 4th analog signal of generation, and the 4th analog signal is sent out by the second communication interface, wherein, the first analog signal is The answering device for receiving the 4th analog signal carries out fourth process generation to the 4th analog signal.
In addition, main control chip also includes：Control terminal；Control terminal electrically connects with first switch module；Main control chip, for When finishing receiving the first data signal, control signal is sent to control terminal；Control terminal, for upon the reception of control signals, controlling First switch module processed disconnects the first not moved end and the first connection end, and controls the not moved end and the of first switch module conducting first Two connection ends.
In addition, main control chip also includes：Control terminal；Control terminal, electrically connected with first switch module and with second switch mould Block electrically connects；Main control chip, for when finishing receiving the first data signal, control signal to be sent to control terminal；Control terminal, use In upon the reception of control signals, control first switch module disconnects the first not moved end and the first connection end, and control first to open Close module the first not moved end and second connection end of conducting, and control second switch module disconnect second not moved end be connected with the 4th End, and control second switch module realize second not moved end turned on the 3rd connection end.
In addition, main control chip, is additionally operable to obtain second processing time T2, second processing time T2 believes to receive the first numeral Number at the time of and to modulation module send three data signals at the time of between difference；It is additionally operable to judge second processing time T2 Whether the time difference between the first processing time T1 is less than preset value, is then to determine circuit delay self-test device and response Communication data between device is not held as a hostage.
Another aspect of the present invention additionally provides a kind of circuit delay self-check system, including：Foregoing circuit delay Autonomous test Device and answering device；Answering device, fourth process generation is carried out for receiving the 4th analog signal, and to the 4th analog signal First analog signal, and send the first analog signal to the first communication interface of circuit delay self-test device.
In addition, answering device, is additionally operable to obtain the 3rd processing time T3, the 3rd processing time T3 is to circuit delay self-test Survey device the first communication interface send the first analog signal at the time of and receive four analog signals at the time of between difference； Preset value is more than the 3rd processing time T3.
As seen from the above technical solution provided by the invention, the invention provides circuit delay self-test device, one Aspect can detect the circuit delay of receiving circuit module, on the other hand can determine that circuit delay self-test device fills with response Whether the communication data between putting is held as a hostage.
Present invention also offers a kind of circuit delay system, on the one hand can detect and be received in circuit delay self-test device The circuit delay of circuit module, it on the other hand can determine the communication data between circuit delay self-test device and answering device Whether it is held as a hostage.
Brief description of the drawings
In order to illustrate the technical solution of the embodiments of the present invention more clearly, required use in being described below to embodiment Accompanying drawing be briefly described, it should be apparent that, drawings in the following description are only some embodiments of the present invention, for this For the those of ordinary skill in field, on the premise of not paying creative work, other can also be obtained according to these accompanying drawings Accompanying drawing.
Fig. 1 is system signal when communication data is kidnapped by third party between device A and device B in background of invention Figure；
Fig. 2 is communication data between circuit delay device A and device B be present in background of invention to be kidnapped by third party When system structure diagram；
Fig. 3 is the structural representation for the circuit delay self-test device that the embodiment of the present invention 1 provides；
Fig. 4 is the structural representation for another circuit delay self-test device that the embodiment of the present invention 1 provides；
Fig. 5 is the structural representation for another circuit delay self-test device that the embodiment of the present invention 1 provides；
Fig. 6 is the structural representation for another circuit delay self-test device that the embodiment of the present invention 1 provides；
Fig. 7 is the structural representation for also a kind of circuit delay self-test device that the embodiment of the present invention 1 provides；
Fig. 8 is a kind of structural representation for circuit delay self-test device that the embodiment of the present invention 2 provides；
Fig. 9 is the structural representation for another circuit delay self-test device that the embodiment of the present invention 2 provides；
Figure 10 is the structural representation for the circuit delay self-check system that the embodiment of the present invention 3 provides.
Embodiment
With reference to the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete Ground describes, it is clear that described embodiment is only part of the embodiment of the present invention, rather than whole embodiments.Based on this The embodiment of invention, the every other implementation that those of ordinary skill in the art are obtained under the premise of creative work is not made Example, belongs to protection scope of the present invention.
In the description of the invention, it is to be understood that term " " center ", " longitudinal direction ", " transverse direction ", " on ", " under ", The orientation or position relationship of the instruction such as "front", "rear", "left", "right", " vertical ", " level ", " top ", " bottom ", " interior ", " outer " are Based on orientation shown in the drawings or position relationship, it is for only for ease of the description present invention and simplifies description, rather than instruction or dark Show that the device of meaning or element there must be specific orientation, with specific azimuth configuration and operation, thus it is it is not intended that right The limitation of the present invention.In addition, term " first ", " second " are only used for describing purpose, and it is not intended that instruction or hint are relative Importance or quantity or position.
In the description of the invention, it is necessary to illustrate, unless otherwise clearly defined and limited, term " installation ", " phase Even ", " connection " should be interpreted broadly, for example, it may be being fixedly connected or being detachably connected, or be integrally connected；Can To be mechanical connection or electrical connection；Can be joined directly together, can also be indirectly connected by intermediary, Ke Yishi The connection of two element internals.For the ordinary skill in the art, with concrete condition above-mentioned term can be understood at this Concrete meaning in invention.
The embodiment of the present invention is described in further detail below in conjunction with accompanying drawing.
Embodiment 1
The present embodiment provides a kind of circuit delay self-test device 10, as shown in Figure 3 and Figure 4, circuit delay Autonomous test dress Putting 10 includes：Main control chip 104, the first communication interface 101, first switch module 102 and receiving circuit module 103, wherein, it is main Control chip 104 comprises at least：First signal output part and signal input part；First switch module 102 includes：First not moved end 1021st, the first connection end 1022 and second connection end 1023；First not moved end 1021 electrically connected with receiving circuit module 103；The One connection end 1022 electrically connects with the first communication interface 101；Second connection end 1023 electrically connects with the first signal output part；First Communication interface 101, for first not the connection end 1022 of moved end 1021 and first turn on when, receive the first analog signal, and to Receiving circuit module 103 sends the first analog signal；Receiving circuit module 103, for receiving the first analog signal, and to first Analog signal carries out first processing the first data signal of generation, and sends the first numeral to the signal input part of main control chip 104 Signal；Main control chip 104, for receiving the first data signal, and second processing is carried out to the first data signal and generates the second mould Intend signal；First switch module 102, for when main control chip 104 finishes receiving the first data signal, disconnect the first not moved end 1021 and first connection end 1022, and turn on the first not moved end 1021 and second connection end 1023；Main control chip 104, is additionally operable to When first moved end 1021 does not turn on second connection end 1023, sent out by the first signal output part to receiving circuit module 103 Send the second analog signal；Receiving circuit module 103, it is additionally operable to receive the second analog signal and first is carried out to the second analog signal Processing the second data signal of generation, the second data signal and the first data signal are identical signal；Main control chip 104, is also used In receiving the second data signal, and the first processing time T1 is obtained, with sending the second mould at the time of to receive the second data signal Difference between at the time of intending signal, and determine that the circuit delay of receiving circuit module 103 is the first processing time T1.
In the present embodiment, circuit delay self-test device 10 can be card reader, smart card etc., and the present embodiment, which is not done, to be had Body limits.
In the present embodiment, the first communication interface 101 can be wired communication interface (such as USB interface or COBBAIF Deng) or wireless communication interface (such as antenna etc.), the present embodiment is not specifically limited.
In the present embodiment, as shown in figure 4, first switch module 102 is three-terminal element, wherein one end is the first not moved end 1021, both ends are the first connection end 1022 and second connection end 1023 in addition, the first not moved end 1021 and receiving circuit module 103 Electrical connection, the first connection end 1022 electrically connects with the first communication interface 101, and the of second connection end 1023 and main control chip 104 One signal output part electrically connects, and first switch module 102 disconnects or turned on the first not connection end 1022 of moved end 1021 and first, the Two connection ends 1023.When first the connection end 1022 of moved end 1021 and first does not turn on, the first communication interface 101 receives the first mould Intend signal, and the first analog signal is sent to receiving circuit module 103.First switch module 102 in the present embodiment can be Physical switch, or virtual switch, as long as can realize the switch of above-mentioned function within protection scope of the present invention.
As a kind of optional embodiment of the present embodiment, first the first numeral of processing generation is carried out to the first analog signal Signal includes：The first data signal of generation is demodulated to the first analog signal.Specifically, receiving circuit module 103 receives the After one analog signal, the first data signal of generation is demodulated to the first analog signal received, and to main control chip 104 Signal input part sends the first data signal.It can be seen that receiving circuit module 103 is the circuit for realizing demodulation function, demodulation is realized Low pass filter in the receiving circuit module 103 of function be present, signal has circuit delay and can not when passing through low pass filter Ignore, the circuit delay detected in the present invention is the circuit delay for the receiving circuit module 103 for realizing demodulation function.
In the present embodiment, main control chip 104 is in order to the second analog signal of generation is sent to receiving circuit module 103, first switch module 102 disconnects the first not moved end 1021 and the when main control chip 104 finishes receiving the first data signal One connection end 1022, and turn on the first not moved end 1021 and second connection end 1023, thus, main control chip 104 can be by the One signal output part sends the second analog signal to receiving circuit module 103, while avoids the first communication interface 101 from receiving outside Signal the second analog signal is interfered.
As a kind of optional embodiment of the present embodiment, main control chip 104 also includes：Control terminal；Control terminal, with first Switch module 102 electrically connects；Main control chip 104, for when finishing receiving the first data signal, control letter to be sent to control terminal Number；Control terminal, for upon the reception of control signals, controlling not moved end 1021 and first of the disconnection of first switch module 102 first Connection end 1022, and control the conducting of first switch module 102 first not moved end 1021 and second connection end 1023.The present embodiment Main control chip 104 controls the disconnection or conducting of first switch module 102 by control terminal, realizes to first switch module 102 Automatically control.
In the present embodiment, although it is understood that the circuit delay of circuit delay self-test device 10 is simulated to first Circuit delay caused by receiving circuit module 103 during signal demodulation the first data signal of generation, but due to master control core Piece 104 simultaneously can not accurately determine to receive the time of the first analog signal, therefore, it is impossible to accurately detect to the first analog signal solution Circuit delay caused by receiving circuit module 103 during tune the first data signal of generation.To determine that receiving circuit receives mould Intend the time of signal, main control chip 104 carries out second processing to the first data signal of reception and generates the second analog signal, and will Second analog signal is sent to receiving circuit module 103, so, main because the second analog signal is that main control chip 104 is sent Control chip 104 can determine send the second analog signal at the time of (i.e. receiving circuit module 103 reception the second analog signal when Carve), in addition, main control chip 104 can determine receive the second data signal at the time of (i.e. receiving circuit module 103 is to the second mould At the time of plan signal carries out the first processing completion), main control chip 104 can determine that reception electricity in circuit delay self-test device 10 The circuit delay of road module 103.
As a kind of optional embodiment of the present embodiment, the simulation of second processing generation second is carried out to the first data signal Signal includes：First modulation the second analog signal of generation is carried out to the first data signal.Specifically, main control chip 104 receives the One data signal, and first modulation the second analog signal of generation is carried out to the first data signal, wherein, the modulation methods of the first modulation Formula the present embodiment is not specifically limited, such as can be amplitude modulation(PAM), phase-modulation or frequency modulation(PFM).
In the present embodiment, first processing the second data signal of generation is carried out to second analog signal to be included：To institute State the second analog signal and be demodulated the second data signal of generation；Main control chip 104 receives the second data signal.Specifically, connect After receiving the second analog signal that circuit module 103 receives the transmission of main control chip 104, receiving circuit module 103 is simulated to second Signal is demodulated the second data signal of generation, because the second analog signal is that the first modulation generation is carried out to the first data signal , therefore, identical with the first data signal to the second data signal of the second analog signal demodulation generation, receiving circuit module 103 pair of second analog signal carries out the first time for handling the second data signal of generation and electric receiving circuit module 103 to first The time that analog signal carries out first processing the first data signal of generation is identical.Circuit delay self-test device 10 passes through master control core Piece 104 sends the second analog signal, and carries out the first processing to the second analog signal received by receiving circuit module 103 Generating the second data signal can determine that receiving circuit module 103 carries out first the first numeral of processing generation to the first analog signal The circuit delay of signal.
As optional embodiment, the first processing time T1 can be with sending out at the time of starting to receive the second data signal Difference between sending at the time of completing the second analog signal, or with starting to send out at the time of starting to receive the second data signal Difference between at the time of sending the second analog signal, or with being sent completely the at the time of finishing receiving the second data signal Difference between at the time of two analog signals, it is of course also possible to be with starting to send at the time of finishing receiving the second data signal Difference between at the time of second analog signal, the present embodiment are not specifically limited.
As a kind of optional embodiment of the present embodiment, second is sent to receiving circuit module 103 in main control chip 104 Start timing at the time of analog signal, and record the numerical value that timing reaches at the time of main control chip 104 receives the second data signal, The numerical value is the circuit delay of receiving circuit module 103.Circuit delay self-test device 10 in the present embodiment can determine The circuit delay of receiving circuit module 103.
During being communicated with answering device, communication data is possible to circuit delay self-test device 10 in the present embodiment Kidnapped by third party, can to determine whether the communication data between circuit delay self-test device 10 and answering device is held as a hostage To be accomplished by the following way：
Mode one：
As a kind of optional embodiment of the present embodiment, as shown in Figure 5 and Figure 6, circuit delay self-test device 10 is also Including second switch module 105, the module of 106 and second communication interface of transtation mission circuit module 107, wherein, second switch module 105 Including：Second not moved end 1051, the 3rd connection end 1052 and the 4th connection end 1053；Second connection end 1023 and the first signal are defeated Go out to hold electrical connection to specifically include：Second connection end 1023 electrically connects with the 3rd connection end 1052；3rd connection end 1052 and second Moved end 1051 does not turn on；Second not moved end 1051 electrically connected with the first signal output part；4th connection end 1053 and transtation mission circuit Module 106 electrically connects；Second switch module 105, for before main control chip 104 receives the first data signal, turning on second The not connection end 1053 of moved end 1051 and the 4th, is additionally operable to after main control chip 104 receives the first data signal, disconnects second The not connection end 1053 of moved end 1051 and the 4th, and turn on the second not connection end 1052 of moved end 1051 and the 3rd；Main control chip 104, It is additionally operable to before the first communication interface 101 receives the first analog signal, sending the 3rd simulation to transtation mission circuit module 106 believes Number；Transtation mission circuit module 106, for receiving the 3rd analog signal and the 3rd processing the 4th mould of generation being carried out to the 3rd analog signal Intend signal, and the 4th analog signal is sent out by the second communication interface 107, wherein, the first analog signal is reception the 4th The answering device of analog signal carries out fourth process generation to the 4th analog signal.
In concrete application, whether the communication data between detection circuit delay self-test device 10 and answering device is robbed Hold, the main control chip 104 in circuit delay self-test device 10 the first communication interface 101 receive the first analog signal before, The 3rd analog signal is sent to transtation mission circuit module 106, transtation mission circuit module 106 receives the 3rd analog signal and simulated to the 3rd Signal carries out the 3rd processing the 4th analog signal of generation.Circuit delay self-test device 10 in the present embodiment passes through sending module The 3rd analog signal that main control chip 104 is sent is sent to answering device, circuit delay self-test device 10 and answering device Communication system is formed, so that whether the communication data detected between circuit delay self-test device 10 and answering device is held as a hostage.
In concrete application, as shown in fig. 6, second switch module 105 is three-terminal element, wherein one end is the second not moved end 1051, both ends are the 3rd connection end 1052 and the 4th connection end 1053 in addition；Main control chip 104 receive the first data signal it Before, the connection end 1053 of moved end 1051 and the 4th, main control chip 104 can not pass through second for the conducting of second switch module 105 second Switch module 105 sends the 3rd analog signal to transtation mission circuit module 106.Wherein, the 3rd analog signal is that main control chip 104 is right 3rd data signal is modulated generation.The 3rd data signal in the present embodiment can be command signal, e.g. circuit The self-test device 10 that is delayed reads the command signal of answering device.Second switch module 105 in the present embodiment can be physics Switch, or virtual switch, as long as the second switch module 105 of above-mentioned function can be realized in protection scope of the present invention Within.
In concrete application, transtation mission circuit module 106 carries out the 3rd processing the 4th analog signal of generation to the 3rd analog signal, Comprise at least：Transtation mission circuit module 106 is amplified the 4th analog signal of generation to the 3rd analog signal.Certainly, to ensure the Four analog signals are sent out away by the second communication interface 107 with larger power, and transtation mission circuit module 106 is to the 3rd mould Intend signal and carry out the 3rd processing the 4th analog signal of generation, including：Transtation mission circuit module 106 is put to the 3rd analog signal Greatly, the 4th analog signal is generated after matching.Sent out after being amplified in the present embodiment by transtation mission circuit module 106 to the 3rd analog signal Answering device is delivered to, ensure that the power for the 4th analog signal that circuit delay self-test device 10 is sent.
It is outside by the second communication interface 107 after transtation mission circuit module 106 generates the 4th analog signal in concrete application Send the 4th analog signal.Wherein, the second communication interface 107 can be wired communication interface (such as USB interface or COBBAIF Deng) or wireless communication interface (such as antenna etc.), the present embodiment is not specifically limited.Preferably, the second communication interface 107 be wireless communication interface, can be sent out the 4th analog signal by modes such as NFC, infrared or bluetooths.In the present embodiment Second communication interface 107 and the first communication interface 101 can be same communication interface, or two independent communications connect Mouthful, the present embodiment is not specifically limited.
In concrete application, transtation mission circuit module 106 is sent out the 4th analog signal, and answering device receives the 4th simulation letter Number, and fourth process is carried out to the 4th analog signal and generates the first analog signal.Wherein, the is carried out to the 4th analog signal everywhere Reason the first analog signal of generation, is comprised at least：The 3rd data signal of generation is demodulated to the 4th analog signal, and according to the 3rd Data signal response the first data signal of generation, and second modulation the first analog signal of generation is carried out to the first data signal, its In, the modulation system of the first modulation is identical with the modulation system of the second modulation.Answering device is believed the 4th simulation in the present embodiment Number carry out fourth process generate the first analog signal after, be sent out the first analog signal as the response to the 4th analog signal Signal.
In concrete application, second switch module 105 disconnects the after main control chip 104 receives the first data signal Two not connection ends 1053 of moved end 1051 and the 4th, the not connection end 1052 of moved end 1051 and the 3rd of conducting second, main control chip 104 can The electric pathway connected by the first signal output part, second switch module 105, first switch module 102 is to receiving circuit module 103 send the second analog signal.
In concrete application, main control chip 104 also includes：Control terminal；Control terminal, electrically connected with first switch module 102 and Electrically connected with second switch module 105；Main control chip 104, for when finishing receiving the first data signal, being sent to control terminal Control signal；Control terminal, for upon the reception of control signals, controlling not moved end 1021 of the disconnection of first switch module 102 first With the first connection end 1022, and the conducting of first switch module 102 first not moved end 1021 and second connection end 1023, and control are controlled Second switch module 105 processed disconnects the second not connection end 1053 of moved end 1051 and the 4th, and control second switch module 105 to turn on The second not connection end 1052 of moved end 1051 and the 3rd.Specifically, when main control chip 104 finishes receiving the first data signal, master control Chip 104 sends control signal to control terminal and controls not moved end 1021 of the disconnection of first switch module 102 first by control terminal With the first connection end 1022, the first not moved end 1021 and second connection end 1023, and second switch is controlled by control terminal is turned on Module 105 disconnects the second not connection end 1053 of moved end 1051 and the 4th, turns on the second not connection end 1052 of moved end 1051 and the 3rd. Main control chip 104 can by the first signal output part, second switch module 105, first switch module 102 connect electric pathway to Receiving circuit module 103 sends the second analog signal.The main control chip 104 of the present embodiment controls first switch mould by control terminal The disconnection or conducting of block 102, second switch module 105, realize to first switch module 102, second switch module 105 from Dynamic control.
In concrete application, main control chip 104, it is additionally operable to obtain second processing time T2, second processing time T2 is reception Difference at the time of first data signal and between at the time of three analog signal of transmission of transtation mission circuit module 106；It is additionally operable to Judge whether the time difference between second processing time T2 and the first processing time T1 is less than preset value, be, determine that circuit prolongs When self-test device 10 and answering device between communication data be not held as a hostage.Specifically, second processing time T2 can be out Begin receive the first data signal at the time of and to transtation mission circuit module 106 be sent completely three analog signals at the time of between difference Value, or send the 3rd analog signal to transtation mission circuit module 106 with starting at the time of starting to receive the first data signal At the time of between difference, or with having been sent to transtation mission circuit module 106 at the time of finishing receiving the first data signal Difference between at the time of three analog signals, it is of course also possible to be with starting at the time of finishing receiving the first data signal Difference between at the time of sending from three analog signals to transtation mission circuit module, the present embodiment are not specifically limited.In addition, circuit Delay self-test device 10 in main control chip 104 from send the 3rd analog signal to receive the first data signal total time be Second processing time T2, because the circuit delay of transtation mission circuit module 106 can be neglected, do not considering transtation mission circuit module 106 In the case of circuit delay, circuit delay self-test device 10 is from the 4th analog signal is sent out to the first data signal of reception Total time and main control chip 104 to send the 3rd analog signal identical to the total time for receiving the first data signal, be all second Processing time T2, the circuit delay caused by receiving circuit module 103 are the first processing time T1, then circuit delay Autonomous test Device 10 is second processing time T2 and the from the 4th analog signal to the time for receiving the first analog signal is sent out Time difference between one processing time T1.Main control chip 104 is judged between second processing time T2 and the first processing time T1 Time difference whether be less than preset value, if it is determined that time difference is less than preset value, it is determined that circuit delay self-test device Communication data between 10 and answering device is not held as a hostage.
Mode two：
As a kind of optional embodiment of the present embodiment, as shown in fig. 7, circuit delay self-test device 10 also includes： The communication interface 107 of transtation mission circuit module 106 and second；Main control chip 104 also includes：Secondary signal output end；Transtation mission circuit mould One end of block 106 electrically connects with secondary signal output end, and the other end electrically connects with the second communication interface 107；Main control chip 104, It is additionally operable to before the first communication interface 101 receives the first analog signal, by secondary signal output end to transtation mission circuit module 106 send the 3rd analog signal；Transtation mission circuit module 106, for receiving the 3rd analog signal and being carried out to the 3rd analog signal 3rd processing the 4th analog signal of generation, and the 4th analog signal is sent out by the second communication interface 107, wherein, first Analog signal carries out fourth process generation to receive the answering device of the 4th analog signal to the 4th analog signal.
In concrete application, whether the communication data between detection circuit delay self-test device 10 and answering device is robbed Hold, main control chip 104 is before the first communication interface 101 receives the first analog signal, by secondary signal output end to transmission Circuit module 106 sends the 3rd analog signal, and transtation mission circuit module 106 receives the 3rd analog signal and the 3rd analog signal is entered Processing the 4th analog signal of generation of row the 3rd.Wherein, the 3rd analog signal is that main control chip 104 is adjusted to the 3rd data signal System generation.The 3rd data signal in the present embodiment can be command signal, and e.g. circuit delay self-test device 10 is read Take the command signal of answering device.The present embodiment directly sends the 3rd simulation by secondary signal output end to transtation mission circuit to be believed Number, reduce the complexity that main control chip 104 controls.
In concrete application, answering device to the 4th analog signal carry out fourth process generate the first analog signal mode with The embodiment of aforesaid way one is identical, no longer specifically repeats.
In concrete application, main control chip 104, it is additionally operable to obtain second processing time T2, second processing time T2 is reception Difference at the time of first data signal and between at the time of three analog signal of transmission of transtation mission circuit module 106；It is additionally operable to Judge whether the time difference between second processing time T2 and the first processing time T1 is less than preset value, be, determine that circuit prolongs When self-test device 10 and answering device between communication data be not held as a hostage.Specifically, second processing time T2 can be out Begin receive the first data signal at the time of and to transtation mission circuit module 106 be sent completely three analog signals at the time of between difference Value, or send the 3rd analog signal to transtation mission circuit module 106 with starting at the time of starting to receive the first data signal At the time of between difference, or with having been sent to transtation mission circuit module 106 at the time of finishing receiving the first data signal Difference between at the time of three analog signals, it is of course also possible to be with starting at the time of finishing receiving the first data signal Difference between at the time of sending from three analog signals to transtation mission circuit module, the present embodiment are not specifically limited.In addition, circuit Delay self-test device 10 in main control chip 104 from send the 3rd analog signal to receive the first data signal total time be Second processing time T2, because the circuit delay of transtation mission circuit module 106 can be neglected, do not considering transtation mission circuit module 106 In the case of circuit delay, circuit delay self-test device 10 is from the 4th analog signal is sent out to the first data signal of reception Total time and main control chip 104 to send the 3rd analog signal identical to the total time for receiving the first data signal, be all second Processing time T2, the circuit delay caused by receiving circuit module 103 are the first processing time T1, then circuit delay Autonomous test Device 10 is second processing time T2 and the from the 4th analog signal to the time for receiving the first analog signal is sent out Time difference between one processing time T1.Main control chip 104 is judged between second processing time T2 and the first processing time T1 Time difference whether be less than preset value, if it is determined that time difference is less than preset value, it is determined that circuit delay self-test device Communication data between 10 and answering device is not held as a hostage.
By the circuit delay self-test device 10 of the present embodiment, receiving circuit module in the present apparatus on the one hand can be detected 103 circuit delay, it on the other hand can also determine the communication data between circuit delay self-test device 10 and answering device Whether it is held as a hostage.
Embodiment 2
The present embodiment provides another circuit delay self-test device 10, as shown in Fig. 8 and Fig. 4, including：Main control chip 104th, the first communication interface 101, first switch module 102, receiving circuit module 103 and modulation module 108, wherein, master control core Piece 104 comprises at least：First signal output part and signal input part；First switch module 102 includes：First not moved end 1021, First connection end 1022 and second connection end 1023；Modulation module 108 comprises at least：Modulated signal input and modulated signal are defeated Go out end；Modulated signal input electrically connects with the first signal output part；First not moved end 1021 be electrically connected with receiving circuit module 103 Connect；First connection end 1022 electrically connects with the first communication interface 101；Second connection end 1023 is electrically connected with modulated signal output end Connect；First communication interface 101, for when first the connection end 1022 of moved end 1021 and first does not turn on, receiving the first simulation letter Number, and send simulation No. the first to receiving circuit module 103；Receiving circuit module 103, for receiving the first analog signal, and First processing the first data signal of generation is carried out to the first analog signal, and the is sent to the signal input part of main control chip 104 One data signal；Main control chip 104, the first data signal is sent for receiving the first data signal, and to modulation module 108； First switch module 102, for when main control chip 104 finishes receiving the first data signal, disconnect first not moved end 1021 with First connection end 1022, and turn on the first not moved end 1021 and second connection end 1023；Modulation module 108, for receiving first Data signal, and the second analog signal of generation is modulated to the first data signal, and by modulated signal output end to reception Circuit module 103 sends the second analog signal；Receiving circuit module 103, it is additionally operable to receive the second analog signal and to the second mould Intend signal and carry out first processing the second data signal of generation, the second data signal and the first data signal are identical signal；It is main Chip 104 is controlled, is additionally operable to receive the second data signal, and obtained for the first processing time T1, the first processing time T1 is receives the Difference between at the time of at the time of two digital signal and sending the first data signal, and determines the electricity of receiving circuit module 103 Road delay is very first time difference T1.
As different from Example 1, the main control chip 104 in the present embodiment does not have modulation function, by modulation module 108 The second analog signal of generation is modulated to the first data signal；In addition, the second connection end 1023 of first switch module 102 with Modulated signal output end electrically connects, and modulation module 108 is by the modulated signal output end of modulation module 108 to receiving circuit module 103 send the second analog signal.
In the present embodiment, at the time of the first processing time T1 that main control chip 104 obtains is receives the second data signal Difference between at the time of with sending the first data signal.Circuit prolongs caused by wave filter is not present in modulation module 108 When, circuit delay caused by modulation module 108 can be neglected, in the case where not considering circuit delay caused by modulation module 108, The circuit delay of receiving circuit module 103 is the first processing time T1.Wherein, main control chip 104 specifically can be by following Mode obtains the first processing time T1：Opened at the time of main control chip 104 sends the first data signal to receiving circuit module 103 Beginning timing, and record the numerical value that reaches of timing at the time of main control chip 104 receives the second data signal, the numerical value are defined as the One processing time T1.
As optional embodiment, the first processing time T1 can be with sending out at the time of starting to receive the second data signal Difference between sending at the time of completing the second analog signal, or with starting to send out at the time of starting to receive the second data signal Difference between at the time of sending the second analog signal, or with being sent completely the at the time of finishing receiving the second data signal Difference between at the time of two analog signals, it is of course also possible to be with starting to send at the time of finishing receiving the second data signal Difference between at the time of second analog signal, the present embodiment are not specifically limited.
During circuit delay self-test device 10 is answering device communication in the present embodiment, communication data is possible to Kidnapped by third party, to determine whether the communication data between circuit delay self-test device 10 and answering device is held as a hostage, have Body is accomplished by the following way：
As a kind of optional embodiment of the present embodiment, as shown in Fig. 9 and Fig. 6, circuit delay self-test device 10 is also Including：Second switch module 105, the communication interface 107 of transtation mission circuit module 106 and second, wherein, second switch module 105 is wrapped Include：Second not moved end 1051, the 3rd connection end 1052 and the 4th connection end 1053；Second connection end 1023 exports with modulated signal End electrical connection specifically includes：Second connection end 1023 electrically connects with the 3rd connection end 1052；3rd connection end 1052 and second is not Moved end 1051 turns on；Second not moved end 1051 electrically connected with modulated signal output end；4th connection end 1053 and transtation mission circuit mould Block 106 electrically connects；Second switch module 105, for before main control chip 104 receives the first data signal, conducting second to be not The connection end 1053 of moved end 1051 and the 4th, is additionally operable to after main control chip 104 receives the first data signal, disconnects second not The connection end 1053 of moved end 1051 and the 4th, and turn on the second not connection end 1052 of moved end 1051 and the 3rd；Main control chip 104, also For before the first communication interface 101 receives the first analog signal, the 3rd data signal to be sent to modulation module 108；Modulation Module 108, it is additionally operable to receive the 3rd data signal, and the 3rd analog signal of generation is modulated to the 3rd data signal, and to Transtation mission circuit module 106 sends the 3rd analog signal；Transtation mission circuit module 106, for receiving the 3rd analog signal and to the 3rd Analog signal carries out the 3rd processing the 4th analog signal of generation, and is sent out the 4th simulation by the second communication interface 107 and believes Number, wherein, the first analog signal carries out fourth process life to receive the answering device of the 4th analog signal to the 4th analog signal Into.
Unlike the mode one in embodiment 1, main control chip 104 does not have modulation function, and main control chip 104 is logical Before believing the analog signal of interface first, the 3rd data signal is sent to modulation module 108.Modulation module 108 receives the 3rd Data signal, and the 3rd analog signal of generation is modulated to the 3rd data signal, modulation module 108 is realized to the 3rd numeral The modulation of signal.
As a kind of optional embodiment of the present embodiment, main control chip 104 also includes：Control terminal；Control terminal, with first Switch module 102 is electrically connected and electrically connected with second switch module 105；Main control chip 104, for finishing receiving the first numeral During signal, control signal is sent to control terminal；Control terminal, for upon the reception of control signals, controlling first switch module 102 Disconnect the first not connection end 1022 of moved end 1021 and first, and control the conducting of first switch module 102 first not moved end 1021 and Second connection end 1023, and control second switch module 105 to disconnect the second not connection end 1053 of moved end 1051 and the 4th, and controlling Second switch module 105 realize second not moved end 1051 turned on the 3rd connection end 1052.The main control chip 104 of the present embodiment The disconnection or conducting of first switch module 102, second switch module 105 are controlled by control terminal, is realized to first switch mould Block 102, second switch module 105 automatically control.
As a kind of optional embodiment of the present embodiment, main control chip 104, it is additionally operable to obtain second processing time T2, Second processing time T2 for receive the first data signal at the time of with to modulation module 108 send three data signals at the time of it Between difference；It is default to be additionally operable to judge whether the time difference between second processing time T2 and the first processing time T1 is less than Value, it is to determine that the communication data between circuit delay self-test device 10 and answering device is not held as a hostage.Specifically, at second Reason time T2 can be to believe at the time of starting to receive the first data signal with being sent completely the 3rd simulation to transtation mission circuit module 106 Number at the time of between difference, or start receive the first data signal at the time of with start to transtation mission circuit module 106 Difference between at the time of sending three analog signals, or at the time of finishing receiving the first data signal with to sending electricity Difference between at the time of road module 106 is sent completely three analog signals, it is of course also possible to finish receiving the first numeral letter Number at the time of and start to transtation mission circuit module send three analog signals at the time of between difference, the present embodiment do not do specifically Limit.In addition, the main control chip 104 in circuit delay self-test device 10 sends the 3rd data signal to modulation module 108 It is second processing time T2 to total time of the first data signal is received, due to modulation module 108 and transtation mission circuit module 106 Circuit delay can be neglected, and in the case where not considering the circuit delay of modulation module 108 and transtation mission circuit module 106, circuit prolongs When self-test device 10 from be sent out the 4th analog signal to receive total time and the main control chip 104 of the first data signal to The total time that modulation module 108 sends the 3rd data signal to the first data signal of reception is identical, is all second processing time T2, The circuit delay caused by receiving circuit module 103 is the first processing time T1, then circuit delay self-test device 10 to It is outer that to send the 4th analog signal to time of the first analog signal is received be second processing time T2 and the first processing time Time difference between T1.Main control chip 104 judges the time difference between second processing time T2 and the first processing time T1 Whether preset value is less than, if it is determined that time difference is less than preset value, it is determined that circuit delay self-test device 10 fills with response Communication data between putting is not held as a hostage.
By the circuit delay self-test device 10 of the present embodiment, receiving circuit module in the present apparatus on the one hand can be detected 103 circuit delay, it on the other hand can also determine the communication data between circuit delay self-test device 10 and answering device Whether it is held as a hostage.
Embodiment 3
The present embodiment provides a kind of circuit delay self-check system, and as shown in Figure 10, circuit delay self-check system includes： Circuit delay self-test device 10 and answering device 20；Wherein,
Circuit delay self-test device 10 is that the communication between answering device 20 can be determined in above-described embodiment 1 and 2 The circuit delay self-test device 10 whether data are held as a hostage.
Answering device 20, for receiving the 4th analog signal, and fourth process generation first is carried out to the 4th analog signal Analog signal, and send the first analog signal to the first communication interface of circuit delay self-test device 10.Specifically, response fills 20 pair of the 4th analog signal progress the first analog signal of fourth process generation is put to comprise at least：Answering device 20 is believed the 4th simulation The 3rd data signal of generation number is demodulated, and the first data signal of generation is responded according to the 3rd data signal, and is counted to first Word signal carries out second modulation the first analog signal of generation, wherein, the modulation system of the first modulation and the modulation methods of the second modulation Formula is identical.After answering device 20 carries out fourth process the first analog signal of generation to the 4th analog signal in the present embodiment, outwards The first analog signal is sent as the response signal to the 4th analog signal.
As an alternative embodiment, answering device 20, it is additionally operable to obtain the 3rd processing time T3, during the 3rd processing Between T3 be to circuit delay self-test device 10 the first communication interface send the first analog signal at the time of with receive the 4th mould Difference between at the time of plan signal；Preset value is more than the 3rd processing time T3.Specifically, the 3rd processing time T3 can be out Begin to circuit delay self-test device 10 the first communication interface send the first analog signal at the time of with finish receiving the 4th mould Difference between at the time of intending signal, or start to send the to the first communication interface of circuit delay self-test device 10 At the time of one analog signal and start receive four analog signals at the time of between difference, with that can be to circuit delay self-test At the time of at the time of first communication interface of survey device 10 is sent completely the first analog signal and finishing receiving four analog signals Between difference, it is of course also possible to be sent completely the first simulation to the first communication interface of circuit delay self-test device 10 Difference between at the time of at the time of signal and starting to receive four analog signals, the present embodiment is not specifically limited.In addition, the Three processing time T3 expression answering devices 20 are being answered from the 4th analog signal is received to the time sent needed for the first analog signal Answer device 20 and circuit delay self-test device 10 it is closer to the distance in the case of, can ignore answering device 20 and circuit delay from The transmission time of signal between detection means 10, ignoring the transmission between answering device 20 and circuit delay self-test device 10 In the case of time, then circuit delay self-test device 10 from send the 4th analog signal to receive the first analog signal when Between (i.e. second processing time T2 with the first processing time T1 time difference) it is identical with the 3rd processing time T3.Circuit delay is certainly Detection means 10 judges whether second processing time T2 and the first processing time T1 time difference is less than preset value, wherein default Value be more than the 3rd processing time T3, if it is determined that time difference is less than preset value, it is determined that circuit delay self-test device 10 and Communication data between answering device 20 is not held as a hostage.
It should be noted that to ensure the accuracy whether being held as a hostage to judging communication data, preset value should be greater than the 3rd Difference between processing time T3 and preset value and the 3rd processing time T3 should not be too big.
The circuit delay self-check system provided by the present embodiment, on the one hand can detect circuit delay self-test device The circuit delay of receiving circuit module in 10, on the other hand can also determine circuit delay self-test device 10 and answering device 20 During communication, whether communication data is held as a hostage.
Any process or method described otherwise above description in flow chart or herein is construed as, and represents to include Module, fragment or the portion of the code of the executable instruction of one or more the step of being used to realize specific logical function or process Point, and the scope of the preferred embodiment of the present invention includes other realization, wherein can not press shown or discuss suitable Sequence, including according to involved function by it is basic simultaneously in the way of or in the opposite order, carry out perform function, this should be of the invention Embodiment person of ordinary skill in the field understood.
It should be appreciated that each several part of the present invention can be realized with hardware, software, firmware or combinations thereof.Above-mentioned In embodiment, software that multiple steps or method can be performed in memory and by suitable instruction execution system with storage Or firmware is realized.If, and in another embodiment, can be with well known in the art for example, realized with hardware Any one of row technology or their combination are realized：With the logic gates for realizing logic function to data-signal Discrete logic, have suitable combinational logic gate circuit application specific integrated circuit, programmable gate array (PGA), scene Programmable gate array (FPGA) etc..
Those skilled in the art are appreciated that to realize all or part of step that above-described embodiment method carries Suddenly be can by program come instruct correlation hardware complete, program can be stored in a kind of computer-readable recording medium In, the program upon execution, including one or a combination set of the step of embodiment of the method.
In addition, each functional unit in each embodiment of the present invention can be integrated in a processing module, can also That unit is individually physically present, can also two or more units be integrated in a module.Above-mentioned integrated mould Block can both be realized in the form of hardware, can also be realized in the form of software function module.If integrated module with The form of software function module realize and be used as independent production marketing or in use, can also be stored in one it is computer-readable Take in storage medium.
Storage medium mentioned above can be read-only storage, disk or CD etc..
In the description of this specification, reference term " one embodiment ", " some embodiments ", " example ", " specifically show The description of example " or " some examples " etc. means specific features, structure, material or the spy for combining the embodiment or example description Point is contained at least one embodiment or example of the present invention.In this manual, to the schematic representation of above-mentioned term not Necessarily refer to identical embodiment or example.Moreover, specific features, structure, material or the feature of description can be any One or more embodiments or example in combine in an appropriate manner.
Although embodiments of the invention have been shown and described above, it is to be understood that above-described embodiment is example Property, it is impossible to limitation of the present invention is interpreted as, one of ordinary skill in the art is not departing from the principle and objective of the present invention In the case of above-described embodiment can be changed within the scope of the invention, change, replace and modification.The scope of the present invention By appended claims and its equivalent limit.

Claims (13)

1. a kind of circuit delay self-test device, it is characterised in that described device includes：Main control chip, the first communication interface, One switch module and receiving circuit module, wherein,
The main control chip comprises at least：First signal output part and signal input part；
The first switch module includes：First not moved end, the first connection end and second connection end；
Described first not moved end electrically connected with the receiving circuit module；First connection end and first communication interface electricity Connection；The second connection end electrically connects with first signal output part；
First communication interface, for when described first moved end does not turn on first connection end, receiving the first simulation Signal, and send first analog signal to the receiving circuit module；
The receiving circuit module, carried out for receiving first analog signal, and to first analog signal at first Reason the first data signal of generation, and send first data signal to the signal input part of the main control chip；
The main control chip, second processing life is carried out for receiving first data signal, and to first data signal Into the second analog signal；
The first switch module, for when the main control chip finishes receiving first data signal, disconnect described the One not moved end and first connection end, and turn on the described first not moved end and second connection end；
The main control chip, it is additionally operable to, when described first moved end does not turn on the second connection end, by described first believe Number output end sends second analog signal to the receiving circuit module；
The receiving circuit module, it is additionally operable to receive second analog signal and second analog signal is carried out at first Reason the second data signal of generation, second data signal and first data signal are identical signal；
The main control chip, it is additionally operable to receive second data signal, and obtained for the first processing time T1, first processing Difference between at the time of time T1 is at the time of receiving second data signal and sends second analog signal, and really The circuit delay of the fixed receiving circuit module is first processing time T1.
2. device according to claim 1, it is characterised in that described device also includes：Second switch module, transtation mission circuit Module and the second communication interface, wherein,
The second switch module includes：Second not moved end, the 3rd connection end and the 4th connection end；
The second connection end is electrically connected with first signal output part and specifically included：The second connection end and the described 3rd Connection end electrically connects；3rd connection end with described second not moved end turn on；Described second not moved end and first signal Output end electrically connects；
4th connection end electrically connects with the transtation mission circuit module；
The second switch module, for before the main control chip receives the first data signal, conducting described second to be motionless End and the 4th connection end, are additionally operable to after the main control chip receives first data signal, disconnect described the Two not moved end and the 4th connection ends, and turn on the described second not moved end and the 3rd connection end；
The main control chip, it is additionally operable to before first communication interface receives the first analog signal, to the transtation mission circuit Module sends the 3rd analog signal；
The transtation mission circuit module, for receiving the 3rd analog signal and the 3rd processing being carried out to the 3rd analog signal The 4th analog signal is generated, and the 4th analog signal is sent out by second communication interface, wherein, first simulation Signal carries out fourth process generation to receive the answering device of the 4th analog signal to the 4th analog signal.
3. device according to claim 1, it is characterised in that described device also includes：Transtation mission circuit module and second is led to Believe interface；
The main control chip also includes：Secondary signal output end；
One end of the transtation mission circuit module electrically connects with secondary signal output end, and the other end is electrically connected with second communication interface Connect；
The main control chip, it is additionally operable to before first communication interface receives the first analog signal, it is defeated by secondary signal Go out end and send the 3rd analog signal to the transtation mission circuit module；
The transtation mission circuit module, for receiving the 3rd analog signal and the 3rd processing being carried out to the 3rd analog signal The 4th analog signal is generated, and the 4th analog signal is sent out by second communication interface, wherein, first simulation Signal carries out fourth process generation to receive the answering device of the 4th analog signal to the 4th analog signal.
4. the device according to claim 1 or 3, it is characterised in that the main control chip also includes：Control terminal；
The control terminal electrically connects with the first switch module；
The main control chip, for when finishing receiving first data signal, control signal to be sent to the control terminal；
The control terminal, for after the control signal is received, controlling the first switch module to disconnect described first not Moved end and first connection end, and control the first switch module conducting described first not to be connected with described second moved end End.
5. device according to claim 2, it is characterised in that the main control chip also includes：Control terminal；
The control terminal, electrically connect with first switch module and electrically connected with the second switch module；
The main control chip, for when finishing receiving first data signal, control signal to be sent to the control terminal；
The control terminal, for after the control signal is received, controlling the first switch module to disconnect described first not Moved end and first connection end, and control the first switch module conducting described first not to be connected with described second moved end End, and control the second switch module to disconnect the described second not moved end and the 4th connection end, and control described second to open Close module conducting described second not moved end and the 3rd connection end.
6. according to the device described in any one of claim 2 to 5, it is characterised in that
The main control chip, it is additionally operable to obtain second processing time T2, second processing time T2 counts to receive described first Difference at the time of word signal and between at the time of transtation mission circuit module transmission three analog signal；It is additionally operable to sentence Whether disconnected time difference between second processing time T2 and first processing time T1 is less than preset value, is to determine Communication data between the circuit delay self-test device and the answering device is not held as a hostage.
7. a kind of circuit delay self-test device, it is characterised in that described device includes：Main control chip, the first communication interface, One switch module, receiving circuit module and modulation module, wherein,
The main control chip comprises at least：First signal output part and signal input part；
The first switch module includes：First not moved end, the first connection end and second connection end；
The modulation module comprises at least：Modulated signal input and modulated signal output end；
The modulated signal input electrically connects with first signal output part；
Described first not moved end electrically connected with the receiving circuit module；First connection end and first communication interface electricity Connection；The second connection end electrically connects with the modulated signal output end；
First communication interface, for when described first moved end does not turn on first connection end, receiving the first simulation Signal, and send the simulation No. first to the receiving circuit module；
The receiving circuit module, carried out for receiving first analog signal, and to first analog signal at first Reason the first data signal of generation, and send first data signal to the signal input part of the main control chip；
The main control chip, for receiving first data signal, and send first numeral to the modulation module and believe Number；
The first switch module, for when the main control chip finishes receiving first data signal, disconnect described the One not moved end and first connection end, and turn on the described first not moved end and second connection end；
The modulation module, for receiving first data signal, and generation is modulated to first data signal Two analog signals, and second analog signal is sent to the receiving circuit module by the modulated signal output end；
The receiving circuit module, it is additionally operable to receive second analog signal and second analog signal is carried out at first Reason the second data signal of generation, second data signal and first data signal are identical signal；
The main control chip, it is additionally operable to receive second data signal, and obtained for the first processing time T1, first processing Difference between at the time of time T1 is at the time of receiving second data signal and sends first data signal, and really The circuit delay of the fixed receiving circuit module is the very first time difference T1.
8. device according to claim 7, it is characterised in that described device also includes：Second switch module, transtation mission circuit Module and the second communication interface, wherein,
The second switch module includes：Second not moved end, the 3rd connection end and the 4th connection end；
The second connection end is electrically connected with the modulated signal output end and specifically included：The second connection end and the described 3rd Connection end electrically connects；3rd connection end with described second not moved end turn on；Described second not moved end and the modulated signal Output end electrically connects；
4th connection end electrically connects with the transtation mission circuit module；
The second switch module, for before the main control chip receives the first data signal, conducting described second to be motionless End and the 4th connection end, are additionally operable to after the main control chip receives first data signal, disconnect described the Two not moved end and the 4th connection ends, and turn on the described second not moved end and the 3rd connection end；
The main control chip, it is additionally operable to before first communication interface receives the first analog signal, to the modulation module Send the 3rd data signal；
The modulation module, it is additionally operable to receive the 3rd data signal, and generation is modulated to the 3rd data signal 3rd analog signal, and send the 3rd analog signal to the transtation mission circuit module；
The transtation mission circuit module, for receiving the 3rd analog signal and the 3rd processing being carried out to the 3rd analog signal The 4th analog signal is generated, and the 4th analog signal is sent out by second communication interface, wherein, first simulation Signal carries out fourth process generation to receive the answering device of the 4th analog signal to the 4th analog signal.
9. device according to claim 7, it is characterised in that the main control chip also includes：Control terminal；
The control terminal electrically connects with the first switch module；
The main control chip, for when finishing receiving first data signal, control signal to be sent to the control terminal；
The control terminal, for after the control signal is received, controlling the first switch module to disconnect described first not Moved end and first connection end, and control the first switch module conducting described first not to be connected with described second moved end End.
10. device according to claim 8, it is characterised in that the main control chip also includes：Control terminal；
The control terminal, electrically connect with the first switch module and electrically connected with the second switch module；
The main control chip, for when finishing receiving first data signal, control signal to be sent to the control terminal；
The control terminal, for after the control signal is received, controlling the first switch module to disconnect described first not Moved end and first connection end, and control the first switch module conducting described first not to be connected with described second moved end End, and control the second switch module to disconnect the described second not moved end and the 4th connection end, and control described second to open Close module realize described second not moved end turned on the 3rd connection end.
11. the device according to claim 8 or 10, it is characterised in that
The main control chip, it is additionally operable to obtain second processing time T2, second processing time T2 counts to receive described first Difference at the time of word signal and between at the time of modulation module transmission three data signal；It is additionally operable to judge institute State whether the time difference between second processing time T2 and first processing time T1 is less than preset value, be described in then determination Communication data between circuit delay self-test device and the answering device is not held as a hostage.
12. a kind of circuit delay self-check system, it is characterised in that the system includes：Described in the claim 6 or 11 Circuit delay self-test device and answering device；
The answering device, fourth process life is carried out for receiving the 4th analog signal, and to the 4th analog signal Into first analog signal, and send first simulation to the first communication interface of the circuit delay self-test device and believe Number.
13. system according to claim 12, it is characterised in that
The answering device, it is additionally operable to obtain the 3rd processing time T3, the 3rd processing time T3 is to circuit delay self-test Survey device the first communication interface send the first analog signal at the time of and receive four analog signal at the time of between Difference；
The preset value is more than the 3rd processing time T3.
CN201610978228.7A 2016-11-07 2016-11-07 Circuit time delay self-detection device and system Active CN107359947B (en)

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CN201610978228.7A CN107359947B (en) 2016-11-07 2016-11-07 Circuit time delay self-detection device and system
EP17867642.5A EP3537631B1 (en) 2016-11-07 2017-09-01 Circuit delay self-measurement method, device, and system
US16/346,530 US10659180B2 (en) 2016-11-07 2017-09-01 Circuit delay self-measurement method, device and system
PCT/CN2017/100212 WO2018082391A1 (en) 2016-11-07 2017-09-01 Circuit delay self-measurement method, device, and system

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