CN107346792B - Varactor structure for flash memory circuit and manufacturing method thereof - Google Patents
Varactor structure for flash memory circuit and manufacturing method thereof Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/92—Capacitors with potential-jump barrier or surface barrier
- H01L29/93—Variable capacitance diodes, e.g. varactors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/66174—Capacitors with PN or Schottky junction, e.g. varactors
Abstract
A varactor structure used in flash memory circuit and its manufacturing method, including a substrate, the first insulating layer formed on the substrate, a floating gate formed on the first insulating layer, a control gate arranged opposite to the floating gate, and the second insulating layer formed between the floating gate and the control gate; a source electrode and a drain electrode are formed on the substrate; the floating grid is separately led out of a first connecting line to serve as one polar plate of the variable capacitance diode capacitor, the outgoing line of the source electrode and the outgoing line of the drain electrode are electrically connected with the outgoing line of the control grid to form a second connecting line to serve as the other polar plate of the variable capacitance diode capacitor, and the first insulating layer and the second insulating layer are dielectric layers of the variable capacitance diode capacitor. The variable capacitance diode used in the flash memory circuit can meet the requirement of high-capacity capacitance and can well give consideration to the trend of chip miniaturization.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and relates to a varactor structure used in a flash memory circuit and a manufacturing method thereof.
Background
A Varactor diode (also called "variable reactance diode") is a diode that is made by using the dependence and principle of PN junction capacitance (barrier capacitance) and its reverse bias voltage. When a forward bias voltage is applied, a large amount of current is generated, a depletion region of a PN (positive and negative) junction is narrowed, capacitance is increased, and a diffusion capacitance effect is generated; when a reverse bias is applied, a transient capacitance effect is generated, but since a leakage current is generated when a forward bias is applied, a reverse bias is applied, as shown in fig. 1.
A varactor diode is also called a varicap, and is a semiconductor that changes junction capacitance according to a change in a supplied voltage, that is, it is applicable as a variable capacitor to a resonance circuit such as an FM tuner and a TV tuner, and an FM modulation circuit. In a Complementary Metal Oxide Semiconductor (CMOS) process, a varactor diode is formed by using a PN junction (N +/Pwell) or polysilicon and a well of the same doping type, and these two types of structures are sometimes used in the varactor diodes currently used in flash memory circuits.
Referring to fig. 2, fig. 2 shows a varactor structure of a gate transistor type in the prior art, which uses an N-type silicon wafer as a substrate, and utilizes a diffusion process to fabricate two highly doped N + regions, and two electrodes are led out and divided into a Source (Source) and a Drain (Drain); then, an oxide insulating layer is formed on the substrate, polysilicon is formed on the oxide insulating layer, an electrode is drawn out as a Gate (Gate), and the substrate and the source are usually connected together, so that the Gate and the substrate each correspond to a plate, and the oxide insulating layer is interposed therebetween, thereby forming a varactor structure. When the voltage of the grid electrode and the source electrode changes, the quantity of the induced charges at the position, close to the oxide layer, of the substrate is changed, and therefore the magnitude of the drain current is controlled.
It is clear to those skilled in the art that since some special circuits in flash memory circuits may require large capacitance, both varactors need to be satisfied by increasing the area. However, increasing the capacitance area in the limited chip area will cause additional work such as redesign of other circuit designs, and the increased area is not favorable for continuous reduction of the chip area, so the industry needs to design a varactor diode for flash memory circuit that can satisfy the requirement of large-capacity capacitance and also can well take into account the trend of chip miniaturization.
Disclosure of Invention
The invention aims to provide a varactor structure used in a flash memory circuit and a manufacturing method thereof, wherein the varactor is manufactured in a CMOS (complementary metal oxide semiconductor) process for manufacturing the flash memory, namely, a floating gate, a control gate and an insulating layer on a substrate of a flash memory transistor are utilized to form a capacitor structure connected in parallel, so that the effect of increasing the capacitance is achieved, and the flash memory structure and the varactor structure in the flash memory circuit can be simultaneously formed on the premise of not increasing the process steps.
In order to achieve the purpose, the technical scheme of the invention is as follows:
a varactor structure for use in a flash memory circuit that fabricates the varactor in a CMOS process that fabricates the flash memory, comprising:
a substrate;
a first insulating layer formed on the substrate;
a floating gate formed on the first insulating layer;
a control grid arranged opposite to the floating grid;
a second insulating layer formed between the floating gate and the control gate;
wherein, a source electrode and a drain electrode are formed on the substrate; the floating grid is separately led out to form a first connecting line to serve as one polar plate of the variable capacitance diode capacitor, the outgoing line of the source electrode, the outgoing line of the drain electrode and the outgoing line of the control grid are electrically connected together to form a second connecting line to serve as the other polar plate of the variable capacitance diode capacitor, and the first insulating layer and the second insulating layer are dielectric layers of the variable capacitance diode capacitor.
Further, the first connecting line is a contact hole; the second insulating layer and the control grid are provided with through holes which are concentric up and down, and contact holes of the floating grid sequentially penetrate through the through holes and are connected to the first metal layer; and a dielectric layer is arranged between the contact hole of the floating gate and the through hole.
Further, the first connecting line is a contact hole; the floating gate has a misaligned portion in horizontal projection with the control gate, and the contact hole of the first connection line is located between the misaligned portion of the floating gate and the first metal layer.
Further, the second connecting line is a contact hole; the source electrode, the drain electrode and the control grid electrode are respectively connected to the first metal layer through corresponding contact holes.
Further, the floating gate is doped in an N type, the substrate is an N-type trap, and the source electrode and the drain electrode are an N + type source electrode and an N + type drain electrode respectively.
Further, the material of the first insulating layer is silicon oxide, and/or the second insulating layer is a silicon oxide/silicon nitride/silicon oxide structure.
Further, the varactor capacitance is related to the thickness of the silicon oxide.
Further, the material of the floating gate and/or the control gate is polysilicon.
In order to achieve the purpose, the invention adopts the following technical scheme:
a method for manufacturing the varactor structure used in the flash memory circuit includes, in a CMOS process step for manufacturing the flash memory, simultaneously manufacturing a substrate formed with a source and a drain in the varactor structure, a first insulating layer formed on the substrate, a floating gate formed on the first insulating layer, a control gate disposed opposite to the floating gate, and a second insulating layer formed between the floating gate and the control gate; and by utilizing a connecting line technology of a CMOS (complementary metal oxide semiconductor) process, a first connecting line of the floating gate is used as one polar plate of the variable capacitance diode capacitor, a leading-out line of the source electrode, a leading-out line of the drain electrode and a leading-out line of the control gate are electrically connected together to form a second connecting line which is used as the other polar plate of the variable capacitance diode capacitor, and the first insulating layer and the second insulating layer are dielectric layers of the variable capacitance diode capacitor.
Further, the first connection line and the second connection line are formed by a contact hole making process; the source electrode, the drain electrode and the control grid electrode are respectively connected to the first metal layer through corresponding contact holes, and the floating grid electrode is connected to the first metal layer through the contact holes.
According to the technical scheme, the varactor structure can be used in a process flow with a CMOS structure, a floating gate originally used as an electronic storage medium in a flash memory structure is used as one polar plate, a control gate and a substrate are respectively used as the other polar plate, and an insulating layer between the floating gate and the substrate and an insulating layer between the floating gate shadow control gates are respectively used as interlayer dielectric layers of capacitors to form a parallel capacitor structure.
Compared with the conventional varactor, the unit-area capacitance C in the varactor structure of the present invention is changed from the capacitance C1 (C-C1) originally equal to the capacitance between the floating gate and the substrate to the sum (C' ═ C1+ C2) of the capacitance C1 between the floating gate and the substrate and the capacitance C2 between the floating gate and the control gate, so that the unit-area capacitance is increased, and the capacitance is enlarged.
Therefore, the capacitance is increased by the parallel capacitor structure, the original chip area is not influenced, and the effect of saving the chip area and simultaneously expanding the capacity is achieved by using the existing flash memory transistor structure.
Drawings
FIG. 1 is a schematic diagram for explaining the principle of a varactor in the prior art
FIG. 2 is a schematic diagram of a prior art gate transistor type varactor
FIG. 3 is a diagram of a prior art flash memory transistor structure in a flash memory circuit
FIG. 4 is a schematic diagram of a varactor structure used in a flash memory circuit according to a preferred embodiment of the present invention
FIG. 5 is a schematic diagram of another preferred embodiment of the varactor structure used in the flash memory circuit of the present invention
Detailed Description
The following describes the embodiments of the present invention in further detail with reference to fig. 3-5.
In the following detailed description of the embodiments of the present invention, in order to clearly illustrate the structure of the present invention and to facilitate explanation, the structure shown in the drawings is not drawn to a general scale and is partially enlarged, deformed and simplified, so that the present invention should not be construed as limited thereto.
It should be noted that, the invention idea of the varactor structure for use in a flash memory circuit of the present invention is to use a structure and a method for increasing a unit area capacitance by using a floating gate, and theoretically, the varactor structure can be used in any process flow with a CMOS structure, but if the varactor structure is manufactured in a circuit without a floating gate, in the CMOS process, due to the addition of the floating gate and the corresponding process, the advantages brought by the process cost and the chip area saving need to be considered.
Therefore, the present invention is particularly applicable to the fabrication of varactor structures in flash memory circuits or circuits having floating gate structures, such as 1.5T structures (1.5T junction is floating gate memory structure, programming and erasing are performed in different regions), and 2T structures (2T structure is a structure in which a select transistor is added beside the floating gate transistor, thereby providing the floating gate diode with immunity to interference).
In the following, we will describe information about a varactor structure used in a flash memory circuit and a method for manufacturing the same. Referring to fig. 3, fig. 3 is a schematic diagram illustrating a structure of a flash memory transistor in a flash memory circuit in the prior art. Flash memory is a long-lived, non-volatile memory that retains stored data information when power is removed and includes a substrate, source and drain electrodes, a floating gate, and a control gate. The floating gate is embedded between the control gate and the substrate as a charge storage medium, and is wrapped by insulating layers, such as an ONO (silicon oxide/silicon nitride/silicon oxide) layer and an oxide layer in fig. 3, and the insulating layers are used for protecting the charge in the floating gate from leaking, so that the flash memory has a memory function; the control gate is used to control the amount of charge in the floating gate. The erase and write principle of flash memory is based on tunneling, which allows current to pass through the insulating layer (also called tunneling oxide) between the floating gate and the silicon substrate to charge (write data) or discharge (erase data) the floating gate. It can be seen that existing flash memory transistor structures incorporate the first element of the varactor structure of the present invention, the "floating gate".
The invention relates to a varactor structure used in a flash memory circuit, which is manufactured and formed in the CMOS process step of manufacturing the flash memory. The varactor structure comprises a substrate, a first insulating layer, a floating gate, a control gate and a second insulating layer, wherein the substrate is provided with a source electrode and a drain electrode; and the first connecting wire of the floating gate can be used as one polar plate of the variable capacitance diode capacitor by utilizing the connecting wire technology of the CMOS process, the leading-out wire of the source electrode and the leading-out wire of the drain electrode are electrically connected with the leading-out wire of the control gate to form a second connecting wire which is used as the other polar plate of the variable capacitance diode capacitor, and the first insulating layer and the second insulating layer are dielectric layers of the variable capacitance diode capacitor.
In the embodiments of the present invention, the floating gate is doped N-type, the substrate is N-type well, and the source and drain can be N + type source and N + type drain, respectively. That is, for the N-type storage gate (equivalent to floating gate) and the capacitances of the N-type source drain and potential well, the polysilicon depletion is small, and the capacitance value is stable, and the use is suggested; for the P-type doped control gate and floating gate, there is a large depletion in the capacitor voltage range, and the capacitance is small and unstable, which is not recommended.
In addition, the material of the first insulating layer of the flash memory may be silicon oxide, and/or the second insulating layer may be a silicon oxide/silicon nitride/silicon oxide structure, in some embodiments of the present invention, the material of the first insulating layer of the varactor structure may also be silicon oxide, and/or the second insulating layer may be a silicon oxide/silicon nitride/silicon oxide structure.
It is clear to those skilled in the art that the flash memory generally uses three voltage devices, i.e. 1.8V, 3.3V, and 5.0V, as devices of the peripheral circuit, and the three voltage devices respectively correspond to different thicknesses of silicon oxide.
In the embodiment of the present invention, the first connection line and/or the second connection line are generally completed in a contact hole process. The contact hole connecting the floating gate and the first metal layer can be generally implemented by two schemes:
①, the first connecting line is a contact hole, the floating gate has a non-overlapping part on the horizontal projection with the control gate, the contact hole of the first connecting line is located between the non-overlapping part of the floating gate and the first metal layer, the second connecting line is a contact hole, and the source, the drain and the control gate are respectively connected to the first metal layer through the corresponding contact holes.
②, the first connection line is a contact hole, the second insulating layer and the control grid are provided with concentric through holes, the contact hole of the floating grid sequentially passes through the through holes in the second insulating layer and the control grid and is connected with the first metal layer, the second connection line is a contact hole, and the source electrode, the drain electrode and the control grid are respectively connected with the first metal layer through the corresponding contact holes.
The specific details of these two schemes are described below by way of two specific examples.
Example one
Referring to fig. 4, fig. 4 is a schematic diagram of a varactor structure used in a flash memory circuit according to a preferred embodiment of the present invention. The varactor includes a substrate 1, a first insulating layer 2 formed on the substrate 1, a floating gate 3 formed on the first insulating layer 2, a control gate 4 disposed opposite to the floating gate 3, and a second insulating layer 5 formed between the floating gate 3 and the control gate 4, wherein the first insulating layer 2 is also called a tunneling oxide layer, and a source and a drain are formed on the substrate 1.
In the present embodiment, the material of the first insulating layer 2 may be silicon dioxide, and the second insulating layer 5 may be a silicon oxide/silicon nitride/silicon oxide (ONO) structure.
The floating gate 3 is separately led out to be used as an electrode plate, fig. 3 illustrates a leading-out mode provided by the embodiment of the present invention, that is, the leading-out line is led out from the side surface of the floating gate, as can be seen from fig. 3, the leading-out line of the floating gate 3 is arranged in a staggered manner without intersection points with the second insulating layer 5 and the control gate 4, at this time, at least one part of the floating gate 3 which is not overlapped with the control gate 4 on the horizontal projection is required to exist, the insulating layer above the part of the floating gate 3 is etched to form a contact hole, and the electrode of the floating gate 3 is led out to the first metal layer at the; the second connection line is a contact hole, and the source, the drain and the control gate 4 are respectively connected to the first metal layer through the corresponding contact holes.
This design has the advantage of not affecting the capacitive area of the control gate and ONO layers, and has the disadvantage of requiring the length of the floating gate 3 to be varied to expose at least a portion of the face of the control gate 4.
The outgoing line of the source electrode, the outgoing line of the drain electrode and the outgoing line of the control grid 4 are electrically connected to be used as a polar plate, and the specific method can be as follows: three Contact holes (Contact) are respectively formed in the insulating layer above the source electrode, the drain electrode and the control grid electrode 4, and each metal Contact hole is led out upwards and is connected with the first metal layer above the metal Contact hole, so that the control grid electrode 4 and the substrate 1 are respectively used as the other electrode plate.
At this time, the floating gate 3, which is originally used as a charge storage medium in the flash memory, becomes one plate, the control gate 4 and the substrate 1 respectively serve as the other plate, and the ONO layer between the floating gate 3 and the control gate 4 and the tunnel oxide layer between the floating gate and the substrate 1 respectively serve as interlayer dielectric layers of the capacitor, thereby forming a parallel capacitor structure. The capacitance structure enables the capacitance C of a unit area to be equal to the sum of the capacitance C1 between the floating gate 3 and the substrate 1 and the capacitance C2 between the floating gate 3 and the control gate 4 (C is C1+ C2), namely the capacitance of the unit area is improved, the chip area is saved, and the capacity expansion effect is achieved.
Example two
Referring to fig. 5, fig. 5 is a schematic diagram of another preferred embodiment of the varactor structure used in the flash memory circuit according to the present invention.
The varactor structure for use in a flash memory circuit provided in this embodiment may include all the structural elements in the flash memory transistor structure of the first embodiment, except that the floating gate 3 of the varactor structure of the first embodiment may be led out from a side surface thereof, and in this embodiment of the present invention, the lead-out line of the floating gate 3 needs to pass through the second insulating layer 5 and the control gate 4. The forming process comprises the following steps:
forming through holes communicated in the vertical direction on the control grid 4 and the second insulating layer 5 respectively, and forming contact holes in the through holes through the insulating layers to be connected with the floating grid 3 so as to lead out the electrodes of the floating grid 3 to be connected with the first metal layer; the second connection line is a contact hole, and the source, the drain and the control gate 4 are respectively connected to the first metal layer through the corresponding contact holes.
The disadvantage of this design is that vias need to be formed on the control gate 4 and the ONO layer, thereby reducing the capacitance area of the control gate layer to some extent, but in general, the capacitance added by the parallel capacitance structure is larger than the capacitance lost by the formation of vias on the control gate 4, and does not have any impact on the chip area.
In summary, from the perspective of improving capacitance, the floating gate, the control gate and the tunneling oxide layer on the substrate are utilized to form a parallel capacitor structure to improve the capacitance of the varactor in unit area, so as to achieve the purpose of saving area in the circuit.
The above description is only for the preferred embodiment of the present invention, and the embodiment is not intended to limit the scope of the present invention, so that all the equivalent structural changes made by using the contents of the description and the drawings of the present invention should be included in the scope of the present invention.
Claims (10)
1. A varactor structure for use in a flash memory circuit, wherein the varactor is fabricated in a CMOS process for fabricating the flash memory, comprising:
a substrate;
a first insulating layer formed on the substrate;
a floating gate formed on the first insulating layer;
a control grid arranged opposite to the floating grid;
a second insulating layer formed between the floating gate and the control gate;
wherein, a source electrode and a drain electrode are formed on the substrate; the floating grid is separately led out to form a first connecting line to serve as one polar plate of the variable capacitance diode capacitor, the outgoing line of the source electrode, the outgoing line of the drain electrode and the outgoing line of the control grid are electrically connected together to form a second connecting line to serve as the other polar plate of the variable capacitance diode capacitor, and the first insulating layer and the second insulating layer are dielectric layers of the variable capacitance diode capacitor.
2. The varactor structure of claim 1, in which the first connection line is a contact hole; the second insulating layer and the control grid are provided with through holes which are concentric up and down, and contact holes of the floating grid sequentially penetrate through the through holes and are connected to the first metal layer; and a dielectric layer is arranged between the contact hole of the floating gate and the through hole.
3. The varactor structure of claim 1, in which the first connection line is a contact hole; the floating gate has a misaligned portion in horizontal projection with the control gate, and the contact hole of the first connection line is located between the first metal layer and above the misaligned portion of the floating gate.
4. The varactor structure of claim 1, 2 or 3, characterized in that the second connection line is a contact hole; the source electrode, the drain electrode and the control grid electrode are respectively connected to the first metal layer through three corresponding contact holes formed in the upper portions of the source electrode, the drain electrode and the control grid electrode.
5. The varactor structure of claim 1, in which the floating gate is N-doped, the substrate is an N-well, and the source and drain are an N + source and an N + drain, respectively.
6. The varactor structure of claim 1, characterized in that the material of the first insulating layer is silicon oxide and/or the second insulating layer is a silicon oxide/silicon nitride/silicon oxide structure.
7. The varactor structure of claim 6, in which the varactor capacitance is related to the thickness of the silicon oxide.
8. The varactor structure of claim 1, in which the material of the floating gate and/or the control gate is polysilicon.
9. A method of manufacturing the varactor structure of any one of claims 1-8, characterized in that in the CMOS process steps for manufacturing the flash memory, a substrate formed with a source and a drain in the varactor structure, a first insulating layer formed on the substrate, a floating gate formed on the first insulating layer, a control gate disposed opposite to the floating gate, and a second insulating layer formed between the floating gate and the control gate are simultaneously manufactured; and by utilizing a connecting line technology of a CMOS (complementary metal oxide semiconductor) process, a first connecting line of the floating gate is used as one polar plate of the variable capacitance diode capacitor, a leading-out line of the source electrode, a leading-out line of the drain electrode and a leading-out line of the control gate are electrically connected together to form a second connecting line which is used as the other polar plate of the variable capacitance diode capacitor, and the first insulating layer and the second insulating layer are dielectric layers of the variable capacitance diode capacitor.
10. The method according to claim 9, wherein the first connection line and the second connection line are formed by a contact hole making process; the source electrode, the drain electrode and the control grid electrode are respectively connected to the first metal layer through three corresponding contact holes formed in the upper portions of the source electrode, the drain electrode and the control grid electrode, and the floating grid electrode is connected to the first metal layer through the contact holes.
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| CN106062954A (en) * | 2014-03-07 | 2016-10-26 | 赫姆霍兹-森德拉姆德雷斯顿-罗森多夫研究中心 | Variable capacitance diode, method for producing a variable capacitance diode, and storage device and detector comprising such a variable capacitance diode |
| CN206134667U (en) * | 2014-04-03 | 2017-04-26 | 株式会社村田制作所 | Variable capacitor |
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