CN107342275A - The manufacture method of the insulating metal substrate of substrate, power module package and patterning - Google Patents
The manufacture method of the insulating metal substrate of substrate, power module package and patterning Download PDFInfo
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- CN107342275A CN107342275A CN201610559866.5A CN201610559866A CN107342275A CN 107342275 A CN107342275 A CN 107342275A CN 201610559866 A CN201610559866 A CN 201610559866A CN 107342275 A CN107342275 A CN 107342275A
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- patterning
- support plate
- insulating barrier
- metal support
- conductive layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4825—Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
- H01L23/49582—Metallic layers on lead frames
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
- H01L23/49586—Insulating layers on lead frames
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
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- H01L2924/19107—Disposition of discrete passive components off-chip wires
Abstract
A kind of substrate, include the conductive layer of a metal support plate, the insulating barrier of a patterning and a patterning, wherein the insulating barrier patterned is arranged on metal support plate, and partly cover metal support plate, and the conductive layer patterned is arranged on the insulating barrier of patterning.The present invention also provides a kind of manufacture method of the power module package including aforesaid base plate and aforesaid base plate.The power module package of insulating metal substrate (PIMS) provided by the invention including a patterning, because the insulating barrier of the patterning in the insulating metal substrate of patterning will not obstruct transmission hot caused by the semiconductor power chip being installed on substrate, therefore power module package can have more preferable heat-sinking capability and higher reliability.
Description
Technical field
The present invention relates to a kind of semiconductor packaging；More particularly to a kind of insulating metal substrate including a patterning
Power module package, and the manufacture method of the insulating metal substrate of the patterning.
Background technology
Power module package (Power module packages) has been widely used in automobile, industrial equipment and family
Electrical appliance.In general, in power module package, one or more semiconductor power chips can be installed in a metal support plate
On, and by an epoxy molding material (epoxy molding compound, abbreviation EMC) it is packaged with protect its internal zero
Part.
Fig. 1 shows the diagrammatic cross-section of normal power module encapsulation 1.As shown in figure 1, the master of normal power module encapsulation 1
To include a metal support plate 10, (full-faced) insulating barrier 11 in one on metal support plate 10 whole face, positioned at insulating barrier
(aforementioned metal support plate 10, insulating barrier 11 and conductive layer 12 form normal power module envelope to the conductive layer 12 of a patterning on 11
Fill the substrate in 1) and multiple power dies 13, can be electrically connected with conductive layer 12 part and can by multiple wires 14 that
This is electrically connected with.
However, due to the structure design of aforesaid base plate, (metal support plate 10, insulating barrier 11 and conductive layer 12 are to stack mutually
), normal power module encapsulation 1 generally has the problem of heat-sinking capability difference, causes its reliability to be also affected.
The content of the invention
In view of problem point, one embodiment of the invention provides a kind of (insulated metal of patterning) substrate, including one
The conductive layer of metal support plate, the insulating barrier of a patterning and a patterning, wherein the insulating barrier patterned is arranged at metal support plate
On, and metal support plate is partly covered, and the conductive layer patterned is arranged on the insulating barrier of patterning.
In one embodiment of the invention, metal support plate has a hole, a groove or a long and narrow hole, the insulation not being patterned
Layer is covered.
In one embodiment of the invention, metal support plate has an opening, and the insulating barrier not being patterned is covered.
In one embodiment of the invention, metal support plate is a lead frame, and material includes copper.
The present invention separately provides a kind of power module package, including (insulated metal of a patterning) substrate, one first chip,
And one second chip.Substrate includes the conductive layer of a metal support plate, the insulating barrier of a patterning and a patterning, wherein pattern
The insulating barrier of change is arranged on metal support plate, and partly covers metal support plate, and the conductive layer patterned is arranged at patterning
Insulating barrier on.First chip is arranged on the metal support plate that the insulating barrier not being patterned is covered.Second chip is arranged at
On the conductive layer of patterning, and it is electrically connected with the first chip.
In one embodiment of the invention, metal support plate has a hole, a groove or a long and narrow hole, and the first chip is arranged at
Wherein.
In one embodiment of the invention, metal support plate has an opening, and the first chip is disposed therein.
In one embodiment of the invention, the insulating barrier of patterning has one first patterning insulated part and one second patterning
Insulated part, some for the conductive layer that the first patterning insulated part is patterned is covered, and the second chip is arranged at figure
In the part of the conductive layer of case.
In one embodiment of the invention, the insulating barrier of patterning has one first patterning insulated part and one second patterning
Insulated part, some for the conductive layer that the first patterning insulated part is patterned is covered, and the second patterning insulation division
The another part for the conductive layer being patterned is divided to be covered, and another portion of the conductive layer of the first wafer electrical connecting pattern
Point.
In one embodiment of the invention, the first chip is directly connected to metal support plate.
In one embodiment of the invention, metal support plate is a lead frame, and material includes copper.
In one embodiment of the invention, the first chip is a horizontal semiconductor element.
In one embodiment of the invention, the second chip is a vertical type semiconductor element.
In one embodiment of the invention, the first chip has a relative drive end and a bottom end, and drive end is provided with more
Individual electrode, and the first chip is arranged on metal support plate by bottom end.
The present invention provides a kind of manufacture method of the insulating metal substrate of patterning again, including：One substrate is provided, has one
The conductive layer of insulating barrier and a patterning, and a upper surface of the conductive layer covering insulating barrier patterned；Formed a bonding plane in
A lower surface of insulating barrier；An opening is formed, through insulating barrier；And the metal support plate of the patterning of pressing one is in the viscous of insulating barrier
Face.
The present invention also provides a kind of manufacture method of the insulating metal substrate of patterning, including：One substrate is provided, has one
The conductive layer of insulating barrier and a patterning, and a upper surface of the conductive layer covering insulating barrier patterned；Formed a bonding plane in
A lower surface of insulating barrier；An opening is formed, through insulating barrier；A metal support plate is pressed in the bonding plane of insulating barrier；And figure
Metal support plate after the above-mentioned pressing of caseization.
The power module package of insulating metal substrate (PIMS) provided by the invention including a patterning, due to patterning
Insulating metal substrate in the insulating barrier of patterning will not obstruct caused by the semiconductor power chip being installed on substrate
The transmission of heat, therefore power module package can have more preferable heat-sinking capability and higher reliability.
For above and other objects of the present invention, feature and advantage can be become apparent, it is cited below particularly go out preferable implementation
Example, and coordinate accompanying drawing, it is described in detail below.
Brief description of the drawings
Fig. 1 shows the diagrammatic cross-section of normal power module encapsulation.
Fig. 2 shows the schematic perspective view of power module package according to an embodiment of the invention.
Fig. 3 shows the explosive view of the power module package in Fig. 2.
Fig. 4 shows the diagrammatic cross-section of the power module package in Fig. 2.
Fig. 5 shows the diagrammatic cross-section of power module package according to another embodiment of the present invention.
Fig. 6 shows the diagrammatic cross-section of power module package according to another embodiment of the present invention.
Fig. 7 shows the schematic perspective view of power module package according to another embodiment of the present invention.
Fig. 8 shows the schematic perspective view of power module package according to another embodiment of the present invention.
Fig. 9 A to Fig. 9 E show the insulated metal of the patterning in power module package according to an embodiment of the invention
The diagrammatic cross-section of the manufacture method of substrate.
Wherein, description of reference numerals is as follows：
1~normal power module encapsulates；
2nd, 3,4,5,6~power module package；
10~metal support plate；
11~insulating barrier；
12~conductive layer；
13~power die；
14~wire；
The insulating metal substrate of 20~patterning；
22~support plate, metal support plate；
24~insulating barrier；
26~conductive layer；
30~the first semiconductor power chips；
The drain connection pad of 30D~first；
The gate connection pad of 30G~first；
The source electrode connection pad of 30S~first；
32~upper surface；
34~lower surface；
40~the second semiconductor power chips；
The gate connection pad of 40G~second；
The source electrode connection pad of 40S~second；
42~upper surface；
44~lower surface；
50~passive device；
52~the first terminal；
54~Second terminal；
60~wire；
100~insulating barrier；
100A~upper surface；
100B~lower surface；
101~conductive layer；
102~bonding plane；
103~opening；
104~metal support plate；
221~Part I；
222~Part II；
222A~hole；
222B~opening；
223~Part III；
224~Part IV；
241~the first patterning insulated parts；
242~opening；
243~the second patterning insulated parts；
261~the first patterned conductive portions；
262~the second patterned conductive portions；
P~dielectric surface material；
S~substrate.
Embodiment
Illustrate presently preferred embodiments of the present invention below.The purpose of this explanation is to provide the overall concept of the invention and be not
To limit to the scope of the present invention.
In the embodiment of the present invention described below, alleged orientation " on ", " under ", it is intended merely to represent institute's accompanying drawings
In relative position close, be not used for limiting the present invention.
In the following drawings or specification description, similar or identical part uses identical symbol.In addition, in accompanying drawing
In, the shape or thickness of embodiment can expand, to simplify or conveniently indicate.It is to be understood that it is not shown or says in the accompanying drawings
The element not described in bright book, form known to those skilled in the art.
Fig. 2 to Fig. 4 is refer to, wherein Fig. 2 shows the three-dimensional signal of power module package 2 according to an embodiment of the invention
Figure, Fig. 3 show that the explosive view of the power module package 2 in Fig. 2, and Fig. 4 show that the section of the power module package 2 in Fig. 2 shows
It is intended to.According to one embodiment of the invention, power module package 2 includes the insulating metal substrate (patterned of a patterning
Insulation metal substrate, abbreviation PIMS) 20, one first semiconductor power chip 30, one second semiconductor work(
40, two passive devices 50 of rate chip and a plurality of wire 60.It is to be understood that Fig. 2 only omits an encapsulated layer into Fig. 4, such as
One epoxy molding material (epoxy molding compound, abbreviation EMC), to cover the insulated metal for being located at patterning
The first semiconductor power chip 30, the second semiconductor power chip 40, passive device 50 and wire 60 on substrate 20.
As shown in Figures 2 to 4, it is conductive to include a support plate 22, an insulating barrier 24 and one for the insulating metal substrate 20 of patterning
Layer 26.In the present embodiment, support plate 22 is a lead frame (lead frame), with multiple patternings and separated part.
Specifically, support plate 22 can be made up of metal material (such as alloy of copper or other cuprics), and with a Part I 221,
One Part II 222, a Part III 223 and a Part IV 224.The material of insulating barrier 24 may include glass fibre
(fiberglass), epoxy resin steel plate (epoxy fiberglass), epoxy resin (epoxies), silicones
(silicones), polyurethane (urethanes) or acrylate (acrylates), and aluminum oxide (aluminum can be added
Oxide), boron nitride (boron nitride), zinc oxide (zinc oxide) or aluminium nitride (aluminum nitride) etc.
Filler is to increase its thermal conductivity.Insulating barrier 24 is formed on support plate 22.It is noted that insulating barrier 24 is a patterning
(patterned) insulating barrier, it partly covers the Part II 222 of metal support plate 22.In the present embodiment, patterning is exhausted
Edge layer 24 has at least one opening 242, and at least a portion that may be such that the Part II 222 of metal support plate 22 is exposed.This
Outside, conductive layer 26 also can be by metal material (such as copper, or can further form material in copper surface and for example plate NiPdAu or titanium
The surface-treated layer of gold) it is made, and be formed on insulating barrier 24.It is noted that conductive layer 26 is the conduction of a patterning
Layer, it partly covers insulating barrier 24.In the present embodiment, the conductive layer 26 of patterning is L fonts, adjacent to the more of insulating barrier 24
Individual edge, and partially around the opening 242 (refer to Fig. 3) of insulating barrier 24, but the present invention is not limited thereto.
As shown in Figures 2 to 4, the first semiconductor power chip 30 is arranged at the metal support plate not covered by insulating barrier 24
On 22 Part II 222.More specifically, the first semiconductor power chip 30 is arranged in the opening 242 of insulating barrier 24, and
It is directly connected to metal support plate 22.Thus, from caused by the first semiconductor power chip 30 heat can by metal support plate 22 (not
Covered by insulating barrier 24) bottom surface effectively loss.On the contrary, in the normal power module encapsulation 1 shown in Fig. 1, from
Heat then can not be by the effectively loss of metal support plate 10, because (full-faced) by whole face caused by power die 13
The barrier of insulating barrier 11.Therefore, can have by the design of the insulating barrier 24 of patterning, the power module package 2 of the present embodiment
More preferable heat-sinking capability, so as to improve its reliability.
As shown in Figures 2 to 4, the second semiconductor power chip 40 is arranged on conductive layer 26.Furthermore foregoing first,
Two semiconductor power chips 30 and 40 can be installed on metal support plate 22 and conductive layer 26 by a dielectric surface material P respectively, wherein
Dielectric surface material P may include metal alloy, tin cream, elargol or other conductive adhesives.
In the present embodiment, the first semiconductor power chip 30 is a horizontal (lateral) semiconductor element, is, for example,
One high-voltage switch (High-Voltage switch, abbreviation HV switch), and the second semiconductor power chip 40 is one vertical
Straight (vertical) semiconductor element, a for example, low-voltage switches (Low-Voltage switch, abbreviation LV
switch)。
As shown in Figures 2 and 3, the first semiconductor power chip 30 have a relative drive end (that is, upper surface 32) and
One bottom end (that is, lower surface 34), wherein drive end are provided with multiple electrodes (including one first drain connection pad (first
Drain pad) 30D, one first source electrode connection pad (first source pad) 30S and one first gate connection pad (first gate
Pad) 30G), and the first semiconductor power chip 30 is arranged on metal support plate 22 by bottom surface.It is noted that metal carries
The Part II 222 of plate 22 is not electrically connected with the first semiconductor power chip 30 (horizontal semiconductor element), and only have with
The bottom surface identical of first semiconductor power chip 30 is electrical.Thus, the bottom surface of the Part II 222 of metal support plate 22 can be direct
Exposed to outer, so as to be advantageous to radiate, and be not necessary to because misgivings in insulation and using an insulating barrier to cover.In addition, the
Two semiconductor power chips 40 have a relative upper surface 42 and a lower surface 44, and wherein upper surface 42 is provided with multiple electrodes
(including one second source electrode connection pad (second source pad) 40S and one second gate connection pad (second gate pad)
40G), and lower surface 44 is provided with an electrode (one second drain connection pad (not shown)), and the second semiconductor power chip 40 is logical
Lower surface 44 is crossed to be arranged on conductive layer 26.
As shown in Fig. 2 in the present embodiment, the first drain connection pad 30D of the first semiconductor power chip 30 passes through at least
One wire 60 is electrically connected with the first part 221 of metal support plate 22, and the first source electrode connection pad 30S is electrically connected by an at least wire 60
Connect conductive layer 26, and the first gate connection pad 30G is electrically connected with the of the second semiconductor power chip 40 by an at least wire 60
Two source electrode connection pad 40S.In addition, the second source electrode connection pad 40S of the second semiconductor power chip 40 is electrical by an at least wire 60
The Part III 223 of metal support plate 22 is connected, the second gate connection pad 40G is electrically connected with metal support plate 22 by an at least wire 60
Part IV 224, and the second drain connection pad on the lower surface 44 of the second semiconductor power chip 40 is electrically connected with and leads
Electric layer 26 (that is, the second drain connection pad is also electrically connected with the first source electrode connection pad 30S of the first semiconductor power chip 30).
Furthermore in the present embodiment, there are the first semiconductor power chip 30 multiple high voltage electric crystals in parallel (to scheme not
Show), each of which high voltage electric crystal, the vague and general type of a for example, horizontal (Depletion mode, abbreviation D-mode) electricity
Crystal, there is one first source electrode (first source electrode) and first being electrically connected with the first source electrode connection pad 30S
Drain connection pad 30D be electrically connected with one first drain (first drain electrode) and with the first gate connection pad 30G electricity
Property connection one first gate (first gate electrode).It is in addition, foregoing in the first semiconductor power chip 30
Each high voltage electric crystal is nitrogenous (nitride-based) electric crystal, and for example, one has gallium nitride (Gallium
Nitride) the high electron mobility electric crystal (High Electron Mobility Transistor, HEMT) of material).Separately
On the one hand, in the present embodiment, the second semiconductor power chip 40 has multiple low-voltage electric crystal (not shown) in parallel, its
In each low-voltage electric crystal, for example, one rectilinear enhanced (Enhancement mode, abbreviation E-mode) electric crystal,
With one second source electrode (second source electrode) being electrically connected with the second source electrode connection pad 40S and the second drain
One second drain (second drain electrode) and be electrically connected with the second gate connection pad 40G that connection pad is electrically connected with
One second gate (second gate electrode).In addition, each foregoing low-voltage electric crystal is one siliceous
(silicon-based) electric crystal.
As shown in Figures 2 and 3, two passive devices 50 are arranged on the insulating metal substrate 20 of patterning.Wherein, it is each
Individual passive device 50 can be a resistor, capacitor or inductor, and have a first terminal 52 and a Second terminal 54.
In the present embodiment, wherein the first part 221 and conductive layer 26 of a passive device 50 electric connection metal support plate 22, and another quilt
Dynamic element 50 is then electrically connected with the Part III 223 of conductive layer 26 and metal support plate 22.In addition, both of the aforesaid passive device 50 is also
It can be installed on respectively by a dielectric surface material P on the insulating metal substrate 20 of patterning, and dielectric surface material P may include that metal closes
Gold, tin cream, elargol or other conductive adhesives.
Designed by aforementioned structure, can be achieved include the first semiconductor power chip 30, the second semiconductor power chip 40,
An and series connection on-off circuit (cascade switch circuit) of two passive devices 50.Compared to a single on-off circuit
(single switch circuit), tandem tap circuit is suitable to carry larger voltage and switch speed is very fast.
It is noted that aforementioned power module encapsulation 2 can be used in the related product of a power (power), such as
Transformer or power supply unit.In addition, 1 (Fig. 1) is encapsulated compared to normal power module, due to the insulated metal with patterning
The design of substrate (PIMS) 20, power module package 2 can have more preferable heat-sinking capability and higher reliability.
Although the first semiconductor power chip 30 in previous embodiment is a horizontal semiconductor element, the present invention is not
As limit.In certain embodiments, the first semiconductor power chip 30 also can be a vertical type semiconductor element, as long as metal
The bottom surface of support plate 22 can be covered by an insulating barrier.In addition, in certain embodiments, first, second semiconductor power chip 30
And 40 also can be other active members or driver (drivers), rather than a high-voltage switch and a low-voltage switches.
Then, some for introducing different embodiments of the invention have the power module package of different structure.
Fig. 5 shows the diagrammatic cross-section of power module package 3 according to another embodiment of the present invention.Wherein, power model
Encapsulation 3 and the difference of the power module package 2 of previous embodiment (Fig. 2 to Fig. 4) is, the Part II 222 of metal support plate 22
Also there is a hole 222A (or a groove or a long and narrow hole), be formed thereon, and do not covered by insulating barrier 24 (that is,
Hole 222A is formed in opening 242), in addition, the first semiconductor power chip 30 is arranged in hole 222A.Thus, first
Semiconductor power chip 30 can abut hole 222A side wall and bottom surface so that from caused by the first semiconductor power chip 30
Heat can be transferred to metal support plate 22 more easily, then pass through the effectively loss of metal support plate 22 again.
Fig. 6 shows the diagrammatic cross-section of power module package 4 according to another embodiment of the present invention.Wherein, power model
Encapsulation 4 and the difference of the power module package 2 of previous embodiment (Fig. 2 to Fig. 4) is, the Part II 222 of metal support plate 22
Also there is an opening 222B, through the upper and lower surface of Part II 222, and do not covered by insulating barrier 24 (that is, opening 222B
It is formed in opening 242), in addition, the first semiconductor power chip 30 is arranged in opening 222B.Thus, the first semiconductor work(
Rate chip 30 can abutment openings 222B side wall, and be directly exposed to by the bottom surface of metal support plate 22 outer so that led from the first half
Heat caused by body power die 30 can more effectively loss.
Fig. 7 shows the schematic perspective view of power module package 5 according to another embodiment of the present invention.Wherein, power model
Encapsulation 5 and the difference of the power module package 2 of previous embodiment (Fig. 2 to Fig. 4) are that insulating barrier 24 can be patterned to have
Separated one first patterning insulated part 241 and 1 second patterns insulated part 243.In addition, the first semiconductor work(
Rate chip 30 is arranged between first, second patterning insulated part 241 and 243 that (that is, the first semiconductor power chip 30 is set
It is placed in 242 (exposed regions) of opening between first, second patterning insulated part 241 and 243).In other words,
First, the second patterning insulated part 241 and 243 is configured in two opposite sides (relatively, the figure of the first semiconductor power chip 30
The insulating barrier 24 of patterning in 2 illustrated embodiments then surrounds the first semiconductor power chip 30), and the first semiconductor power is brilliant
Piece 30 is directly connected to the Part II 222 of metal support plate 22.
Furthermore in the present embodiment (Fig. 7), conductive layer 26 can be patterned to have separated one first patterning
The patterned conductive portions 262 of current-carrying part 261 and 1 second, and first, second patterned conductive portions 261 and 262 are set respectively
Be placed on first, second patterning insulated part 241 and 243 and partly covering first, second patterning insulated part 241 and
243.In addition, the second semiconductor power chip 40 is arranged on the first patterned conductive portions 261 and is electrically connected.It is worth
One is mentioned that, in the present embodiment, the first drain connection pad 30D of the first semiconductor power chip 30 is first electrically connected with positioned at the
The second patterned conductive portions 262 on two patterning insulated parts 243, metal is electrically connected with then through a plurality of wire 60
The first part 221 of support plate 22, rather than embodiment as shown in Figure 2, the first drain of its first semiconductor power chip 30
Connection pad 30D is the first part 221 that metal support plate 22 is directly electrically connected with by an at least wire 60.
Fig. 8 shows the schematic perspective view of power module package 6 according to another embodiment of the present invention.Wherein, power model
Encapsulation 6 and the difference of the power module package 2 of previous embodiment (Fig. 2 to Fig. 4) are that conductive layer 26 can be patterned to have
The separated patterned conductive portions 262 of one first patterned conductive portions 261 and one second, and first, second patterning
Current-carrying part 261 and 262 is configured in the two opposite sides of the first semiconductor power chip 30.In addition, the second semiconductor power is brilliant
Piece 40 is arranged on the first patterned conductive portions 261 and is electrically connected.It is noted that in the present embodiment, the
First drain connection pad 30D of semiconductor power die 30 is the second pattern conductive being first electrically connected with insulating barrier 24
Part 262, then through the first part 221 of a plurality of wire 60 electric connection metal support plate 22, rather than as shown in Figure 2
Embodiment, the first drain connection pad 30D of its first semiconductor power chip 30 are directly to be electrically connected with by an at least wire 60
The first part 221 of metal support plate 22.
Furthermore although the insulating barrier 24 of the patterning in the present embodiment (Fig. 8) is to surround the first semiconductor power chip 30
Configuration, but it can also be partially around the first semiconductor power chip 30, that is to say, that the first semiconductor power chip 30
The insulating barrier 24 that at least side can not be patterned is surrounded.
Then, according to one embodiment of the invention, the one of preceding patterning insulating metal substrate 20 (Fig. 2 to Fig. 8) is introduced
Kind manufacture method.Please sequentially reference picture 9A to Fig. 9 E.
As shown in Figure 9 A, a substrate S is provided first, there is an insulating barrier 100 and be formed at the upper surface of insulating barrier 100
A conductive layer 101 on 100A.In the present embodiment, the material of insulating barrier 100 may include glass fibre (fiberglass), ring
Oxygen tree fat steel plate (epoxy fiberglass), epoxy resin (epoxies), silicones (silicones), polyurethane
(urethanes) or acrylate (acrylates), and aluminum oxide (aluminum oxide), boron nitride (boron can be added
Nitride), the filler such as zinc oxide (zinc oxide) or aluminium nitride (aluminum nitride) to be to increase its thermal conductivity, and
Conductive layer 101 can be by metal material (such as copper, or in copper surface can further form material as plating NiPdAu or the table of titanium
Face process layer) it is made.Then, as shown in Figure 9 B, a light lithography (photolithography) technique, including exposure are performed
(exposure), develop (developing) and etch steps such as (etching), to cause the conductive layer on insulating barrier 100
101 are patterned.
As shown in Figure 9 C, after conductive layer 101 is patterned, a bonding plane (adhesive side) 102 is formed in exhausted
The lower surface 100B of edge layer 100.In the present embodiment, bonding plane 102 with apply a two-sided sticker in the following table of insulating barrier 100
Face 100B mode and formed.Then, as shown in fig. 9d, a chemical etching or drilling (drill) technique, such as thunder are performed
Penetrate or machine drilling, 103 are open to be formed through at least the one of insulating barrier 100.It is to be understood that the conductive layer 101 of patterning,
By chemical etching or the insulating barrier 100 and opening 103 of bore process, that is, correspond respectively to preceding patterning insulated metal
The conductive layer 26 of patterning in substrate 20 (Fig. 2~Fig. 8), the insulating barrier 24 of patterning and opening 242.
As shown in fig. 9e, after the opening 103 through insulating barrier 100 is formed, there is provided the metal support plate of a patterning
104 (alloys of material such as copper or other cuprics), such as a lead frame (lead frame), then, press (laminate)
The metal support plate 104 of patterning is in the bonding plane 102 of insulating barrier 100, and wherein metal support plate 104 corresponds to preceding patterning exhausted
Metal support plate 22 in edge metal substrate 20 (Fig. 2~8), so complete the system of the insulating metal substrate (PIMS) of a patterning
Make, and the insulating metal substrate patterned includes a metal support plate, is arranged on metal support plate and partly covers metal support plate
One patterning insulating barrier and be arranged on the insulating barrier of patterning one patterning conductive layer.
It is to be understood that in some embodiments of the invention, (the figure after the opening 103 through insulating barrier 100 is formed
9D), non-patterned (non-patterned) metal support plate 104 also can first be pressed in the bonding plane 102 of insulating barrier 100, with
Afterwards, recycle and the metal after pressing is carried such as Laser drill or lithography process (including step exposing, develop and etching)
Plate 104 is patterned (Fig. 9 E), to complete the manufacture of the insulating metal substrate (PIMS) of a patterning, and the insulation patterned
Metal substrate includes a metal support plate, is arranged on metal support plate and partly covers the insulation of a patterning of metal support plate
The conductive layer of layer and the patterning being arranged on the insulating barrier of patterning.
In summary, the present invention provides a kind of power model envelope of insulating metal substrate (PIMS) including a patterning
Dress.Because the insulating barrier of the patterning in the insulating metal substrate of patterning will not obstruct the semiconductor power being installed on substrate
Hot transmission caused by chip, therefore power module package can have more preferable heat-sinking capability and higher reliability.
Although the present invention is disclosed as above with foregoing embodiment, so it is not limited to the present invention.People in the art
Member, without departing from the spirit and scope of the present invention, when a little change and retouching can be done.Therefore protection scope of the present invention is worked as
Define and be defined depending on appended claims.
Claims (16)
- A kind of 1. substrate, it is characterised in that including：One metal support plate；The insulating barrier of one patterning, is arranged on the metal support plate, and partly cover the metal support plate；AndThe conductive layer of one patterning, is arranged on the insulating barrier of the patterning.
- 2. substrate as claimed in claim 1, it is characterised in that the metal support plate has a hole, a groove or a long and narrow hole, Do not covered by the insulating barrier of the patterning.
- 3. substrate as claimed in claim 1, it is characterised in that the metal support plate has an opening, not by the exhausted of the patterning Edge layer is covered.
- 4. substrate as claimed in claim 1, it is characterised in that the metal support plate is a lead frame, and material includes copper.
- A kind of 5. power module package, it is characterised in that including：One substrate, there is the conductive layer of a metal support plate, the insulating barrier of a patterning and a patterning, the insulation of the patterning Layer is arranged on the metal support plate, and partly covers the metal support plate, and the conductive layer of the patterning is arranged at the patterning On insulating barrier；One first chip, it is arranged on the metal support plate not covered by the insulating barrier of the patterning；And one second chip, It is arranged on the conductive layer of the patterning, and is electrically connected with first chip.
- 6. power module package as claimed in claim 5, it is characterised in that the metal support plate have a hole, a groove or One long and narrow hole, and first chip is disposed therein.
- 7. power module package as claimed in claim 5, it is characterised in that the metal support plate have one opening, and this first Chip is disposed therein.
- 8. power module package as claimed in claim 5, it is characterised in that the insulating barrier of the patterning has one first pattern Change insulated part and one second patterning insulated part, the first patterning insulated part is by one of the conductive layer of the patterning Part is covered, and second chip is arranged in the part of the conductive layer of the patterning.
- 9. power module package as claimed in claim 5, it is characterised in that the insulating barrier of the patterning has one first pattern Change insulated part and one second patterning insulated part, the first patterning insulated part is by one of the conductive layer of the patterning Part is covered, and the second patterning insulated part is covered by another part of the conductive layer of the patterning, and first crystalline substance Piece is electrically connected with the another part of the conductive layer of the patterning.
- 10. power module package as claimed in claim 5, it is characterised in that first chip is directly connected to the metal support plate.
- 11. power module package as claimed in claim 5, it is characterised in that the metal support plate is a lead frame, and material includes Copper.
- 12. power module package as claimed in claim 5, it is characterised in that first chip is a horizontal semiconductor element Part.
- 13. power module package as claimed in claim 5, it is characterised in that second chip is vertical type semiconductor member Part.
- 14. power module package as claimed in claim 5, it is characterised in that first chip has a relative drive end And a bottom end, the drive end is provided with multiple electrodes, and first chip is arranged on the metal support plate by the bottom end.
- A kind of 15. manufacture method of the insulating metal substrate of patterning, it is characterised in that including：A substrate is provided, the conductive layer with an insulating barrier and a patterning, the conductive layer of the patterning covers the insulating barrier One upper surface；A bonding plane is formed in a lower surface of the insulating barrier；An opening is formed, through the insulating barrier；AndThe metal support plate of the patterning of pressing one is in the bonding plane of the insulating barrier.
- A kind of 16. manufacture method of the insulating metal substrate of patterning, it is characterised in that including：A substrate is provided, the conductive layer with an insulating barrier and a patterning, the conductive layer of the patterning covers the insulating barrier One upper surface；A bonding plane is formed in a lower surface of the insulating barrier；An opening is formed, through the insulating barrier；A metal support plate is pressed in the bonding plane of the insulating barrier；AndThe metal support plate after patterning pressing.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US15/142,458 US9905439B2 (en) | 2016-04-29 | 2016-04-29 | Power module package having patterned insulation metal substrate |
| US15/142,458 | 2016-04-29 | ||
| US15/142,588 US9865531B2 (en) | 2016-04-29 | 2016-04-29 | Power module package having patterned insulation metal substrate |
| US15/142,588 | 2016-04-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107342275A true CN107342275A (en) | 2017-11-10 |
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|---|---|---|---|
| CN201610559866.5A Pending CN107342275A (en) | 2016-04-29 | 2016-07-15 | The manufacture method of the insulating metal substrate of substrate, power module package and patterning |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN107342275A (en) |
| TW (1) | TWI650843B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11239211B2 (en) | 2019-08-28 | 2022-02-01 | Industrial Technology Research Institute | Electronic device having a curved portion between a plurality of conductive portions on a substrate |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10818568B1 (en) * | 2019-06-28 | 2020-10-27 | Alpha And Omega Semiconductor (Cayman) Ltd. | Super-fast transient response (STR) AC/DC converter for high power density charging application |
| TWI716075B (en) | 2019-08-19 | 2021-01-11 | 尼克森微電子股份有限公司 | Power module |
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| JP2002246515A (en) * | 2001-02-20 | 2002-08-30 | Mitsubishi Electric Corp | Semiconductor device |
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| CN102017135A (en) * | 2008-04-28 | 2011-04-13 | 罗伯特·博世有限公司 | Substrate-mounted circuit module comprising components in a plurality of contact planes |
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| US7683477B2 (en) * | 2007-06-26 | 2010-03-23 | Infineon Technologies Ag | Semiconductor device including semiconductor chips having contact elements |
| CN103855914B (en) * | 2012-12-03 | 2017-04-05 | 台达电子工业股份有限公司 | Power-supply system and power model therein and the method for making power model |
| CN201845773U (en) * | 2010-08-27 | 2011-05-25 | 苏州科医世凯半导体技术有限责任公司 | High-power LED (Light Emitting Diode) packaging module |
| US9142426B2 (en) * | 2011-06-20 | 2015-09-22 | Cyntec Co., Ltd. | Stack frame for electrical connections and the method to fabricate thereof |
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| JP2002246515A (en) * | 2001-02-20 | 2002-08-30 | Mitsubishi Electric Corp | Semiconductor device |
| CN101236963A (en) * | 2007-01-31 | 2008-08-06 | 雅马哈株式会社 | Semiconductor device and packaging structure therefor |
| CN102017135A (en) * | 2008-04-28 | 2011-04-13 | 罗伯特·博世有限公司 | Substrate-mounted circuit module comprising components in a plurality of contact planes |
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| US11239211B2 (en) | 2019-08-28 | 2022-02-01 | Industrial Technology Research Institute | Electronic device having a curved portion between a plurality of conductive portions on a substrate |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201742229A (en) | 2017-12-01 |
| TWI650843B (en) | 2019-02-11 |
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Application publication date: 20171110 |