CN107342215B - III-nitride and silicon heterogeneous integrated substrate and manufacturing method thereof - Google Patents
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Abstract
The present invention provides a group III nitride and silicon heterogeneous integrated substrate and a method for manufacturing the same, the group III nitride and silicon heterogeneous integrated substrate comprising: a silicon substrate; the III-nitride laminated structure is formed on the surface of the first preset area of the silicon substrate; a silicon-based laminated structure formed on the surface of a second preset area of the silicon substrate; the silicon-based laminated structure sequentially comprises a first insulating layer, a silicon layer and a second insulating layer from bottom to top; the silicon-based laminated structure and the III-nitride laminated structure are isolated by an isolation structure; and the cap layer covers the surfaces of the silicon-based laminated structure and the III-nitride laminated structure. According to the III-nitride and silicon heterogeneous integrated substrate and the manufacturing method thereof, the silicon-based laminated structure and the III-nitride laminated structure are integrated on the same silicon substrate, and the obtained novel heterogeneous integrated substrate is compatible with CMOS (complementary metal oxide semiconductor), so that an important technical innovation platform can be provided for realizing products exceeding Moore's law.
Description
Technical Field
The invention belongs to the field of semiconductors, and relates to a III-nitride and silicon heterogeneous integrated substrate and a manufacturing method thereof.
Background
The semiconductor industry, which is centered on moore's law, has driven the wave forward of both computing (PC) and communications (internet) information technologies in the past half century. However, as silicon CMOS device sizes are increasingly approaching the physical limits of the atomic scale, moore's law development has met with bottlenecks due to significant research and development efforts and manufacturing difficulties. The "mmm" industry refers to the mature semiconductor and its extended technologies without the need for device scaling, including Micro-Electro-Mechanical systems (MEMS), Electro-optical, radio frequency, power, analog, microfluidic, Micro-energy, and the like.
Compared with bulk silicon materials, group III nitride (also called III-N compound) materials have unique advantages in the fields of photoelectricity, power, radio frequency, MEMS and the like due to the characteristics of direct band gap, extremely large built-in electric field and the like. Wherein III denotes at least one element of group III of the periodic Table of the elements.
Bulk silicon is a platform for substrate materials that implement moore's law. And a novel III-nitride and silicon heterogeneous integrated substrate is also an important new technological innovation platform for realizing 'exceeding Moore' law.
Since the group III nitride crystal is mainly a hexagonal lattice, it can generally grow only on the six-axis symmetric Si (111) crystal plane; whereas CMOS silicon processes mostly use silicon substrates with Si (100) crystal orientation.
Therefore, how to provide a III-nitride and silicon heterogeneous integrated substrate and a method for manufacturing the same to integrate III-nitride with a Si (100) substrate that can be used in CMOS processes to provide a CMOS compatible high quality III-nitride and silicon heterogeneous integrated substrate for various products exceeding moore's law becomes an important technical problem to be solved by those skilled in the art.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, it is an object of the present invention to provide a group III nitride and silicon hetero-integrated substrate and a method for manufacturing the same, which solve the problem of the prior art that beyond the lack of CMOS compatible high quality group III nitride and silicon hetero-integrated substrates.
To achieve the above and other related objects, the present invention provides a group III nitride and silicon hetero-integrated substrate comprising:
a silicon substrate;
the III-nitride laminated structure is formed on the surface of the first preset area of the silicon substrate;
a silicon-based laminated structure formed on the surface of a second preset area of the silicon substrate; the silicon-based laminated structure sequentially comprises a first insulating layer, a silicon layer and a second insulating layer from bottom to top; the silicon-based laminated structure and the III-nitride laminated structure are isolated by an isolation structure;
And the cap layer covers the surfaces of the silicon-based laminated structure and the III-nitride laminated structure.
Optionally, the silicon substrate adopts (111) crystal orientation silicon, and the silicon layer adopts (100) crystal orientation silicon.
Optionally, the first insulating layer and the second insulating layer each include a silicon dioxide material.
Optionally, the cap layer comprises a silicon dioxide material.
Optionally, the group III nitride stacked structure sequentially includes, from bottom to top, a buffer layer, an unintentionally doped GaN layer, an N-type GaN layer, an InGaN quantum well layer, and a P-type GaN layer.
Optionally, the group III nitride stacked structure sequentially includes, from bottom to top, a buffer layer, a first unintentionally doped GaN layer, an N-type GaN layer, a second unintentionally doped GaN layer, and a P-type GaN layer.
Optionally, the group III nitride stacked structure sequentially includes, from bottom to top, a buffer layer, an unintentionally doped GaN layer, an N-type GaN layer, and an AlGaN cap layer.
Optionally, the group III nitride stacked structure sequentially includes, from bottom to top, a buffer layer, an unintentionally doped GaN layer, an AlGaN layer, an N-type GaN layer, an InGaN quantum well layer, a P-type AlGaN layer, and a P-type GaN layer.
The invention also provides a manufacturing method of the III-nitride and silicon heterogeneous integrated substrate, which comprises the following steps:
S1: providing an SOI substrate which sequentially comprises a silicon substrate, a first insulating layer and a silicon layer from bottom to top;
s2: forming a second insulating layer on the surface of the silicon layer, and etching to obtain an epitaxial window; the epitaxial window sequentially penetrates through the second insulating layer, the silicon layer and the first insulating layer from top to bottom and exposes out of the silicon substrate;
s3: forming a side wall serving as an isolation structure on the side wall of the epitaxial window;
s4: epitaxially growing a group III nitride stack structure within the epitaxial window; the first insulating layer, the silicon layer and the second insulating layer form a silicon-based laminated structure;
s5: and forming a cap layer covering the surfaces of the silicon-based laminated structure and the III-nitride laminated structure.
Optionally, the SOI substrate is a hybrid crystal orientation substrate, wherein the silicon substrate is (111) crystal orientation silicon, and the silicon layer is (100) crystal orientation silicon.
Optionally, the SOI substrate is obtained by using a bonding technique.
Optionally, in step S2, when the epitaxial window is formed, the first insulating layer is etched by using a wet etching process.
Optionally, the group III nitride stacked structure sequentially includes, from bottom to top, a buffer layer, an unintentionally doped GaN layer, an N-type GaN layer, an InGaN quantum well layer, and a P-type GaN layer.
Optionally, the group III nitride stacked structure sequentially includes, from bottom to top, a buffer layer, a first unintentionally doped GaN layer, an N-type GaN layer, a second unintentionally doped GaN layer, and a P-type GaN layer.
Optionally, the group III nitride stacked structure sequentially includes, from bottom to top, a buffer layer, an unintentionally doped GaN layer, an N-type GaN layer, and an AlGaN cap layer.
Optionally, the group III nitride stacked structure sequentially includes, from bottom to top, a buffer layer, an unintentionally doped GaN layer, an AlGaN layer, an N-type GaN layer, an InGaN quantum well layer, a P-type AlGaN layer, and a P-type GaN layer.
As described above, the group III nitride and silicon hetero-integrated substrate and the manufacturing method thereof of the present invention have the following advantageous effects: according to the III-nitride and silicon heterogeneous integrated substrate and the manufacturing method thereof, the silicon-based laminated structure and the III-nitride laminated structure are integrated on the same silicon substrate, wherein the silicon-based laminated structure can be used for manufacturing a traditional circuit, and various applications beyond molar can be realized by combining the III-nitride laminated structure. The III-nitride and silicon heterogeneous integrated substrate and the novel heterogeneous integrated substrate obtained by the manufacturing method thereof are compatible with CMOS, and can provide an important technical innovation platform for realizing products exceeding Moore's law.
Drawings
FIG. 1 is a schematic cross-sectional view of a substrate for heterogeneous integration of group III nitride and silicon according to the present invention.
Fig. 2-5 are schematic cross-sectional views of the III-nitride stack structure in various applications.
Fig. 6 is a process flow diagram of the manufacturing method of the group III nitride and silicon hetero-integrated substrate of the present invention.
Fig. 7 shows a schematic cross-sectional structure of an SOI substrate provided for the manufacturing method of the group III nitride and silicon hetero-integrated substrate of the present invention.
Fig. 8 is a schematic diagram showing that a second insulating layer is formed on the surface of the silicon layer and an epitaxial window is obtained by etching according to the manufacturing method of the group III nitride and silicon heterogeneous integrated substrate.
Fig. 9 is a schematic view showing that the manufacturing method of the III-nitride and silicon hetero-integrated substrate of the present invention forms a side wall as an isolation structure on the side wall of the epitaxial window.
Fig. 10 shows a schematic view of a group III nitride stack structure epitaxially grown in the epitaxial window for the fabrication method of a group III nitride and silicon hetero-integrated substrate of the present invention.
Description of the element reference numerals
1 silicon substrate
2 III-nitride stack structure
201, 206, 211, 215 buffer layer
202, 207, 209, 212, 216 unintentionally doped GaN layer
203, 208, 213, 218N type GaN layer
204,219 InGaN Quantum well layers
205, 210, 221P-type GaN layer
214 AlGaN cap layer
217 AlGaN layer
220P type AlGaN layer
3 silicon-based laminated structure
301 first insulating layer
302 silicon layer
303 second insulating layer
4 isolation structure
5 capping layer
6 epitaxial window
S1-S5 steps
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 10. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
Example one
The present invention provides a group III nitride and silicon heterogeneous integrated substrate, referring to fig. 1, which is a schematic cross-sectional structure diagram of the group III nitride and silicon heterogeneous integrated substrate, including:
a silicon substrate 1;
a group III nitride stacked structure 2 formed on the surface of a first predetermined region of the silicon substrate 1;
a silicon-based laminated structure 3 formed on the surface of a second preset area of the silicon substrate 1; the silicon-based laminated structure 3 sequentially comprises a first insulating layer 301, a silicon layer 302 and a second insulating layer 303 from bottom to top; the silicon-based laminated structure 3 is isolated from the group III nitride laminated structure 2 through an isolation structure 4;
and the cap layer 5 covers the surfaces of the silicon-based laminated structure 3 and the III-nitride laminated structure 2.
Since the conventional circuit is mostly fabricated on Si (100), in this embodiment, the silicon layer 302 preferably adopts (100) crystal orientation silicon. While the group III nitride is grown on Si (111), in the present embodiment, the silicon substrate 1 preferably employs (111) crystal orientation silicon.
Specifically, the first insulating layer 301 serves to isolate the silicon substrate 2 from the silicon layer 302, and a silicon dioxide material is usually used. The second insulating layer 303 serves to protect the surface of the silicon layer 302, including but not limited to silicon dioxide materials. The cap layer 5 protects the silicon-based stack structure and the group III nitride stack structure, including but not limited to silicon dioxide materials.
In the III-nitride and silicon heterogeneous integrated substrate, a silicon-based laminated structure 3 and the III-nitride laminated structure 2 are integrated on the same silicon substrate 1, wherein the silicon-based laminated structure 3 can be used for manufacturing a traditional circuit, and various applications exceeding Moore can be realized by combining the III-nitride laminated structure 2.
In one application example, the group III nitride and silicon heterogeneous integrated substrate can be used for realizing integrated light emitting diodes and driving. Among them, a Light Emitting Diode (LED) is a semiconductor Light Emitting device, and is manufactured by using the principle of semiconductor P-N junction electroluminescence. Gallium nitride (GaN) -based compounds are direct band gap wide bandgap semiconductors, whose band gap is continuously adjustable from 1.8-6.2eV and which have very high breakdown voltages, and thus are widely used in high-brightness blue-green light emitting diodes, blue-violet Laser Diodes (LDs).
As an example, as shown in fig. 2, for a group III nitride and silicon hetero-integrated substrate applied to an integrated LED and driver, the group III nitride stacked structure 2 includes, from bottom to top, a buffer layer 201, an unintentionally doped GaN layer 202, an N-type GaN layer 203, an InGaN quantum well layer 204, and a P-type GaN layer 205. The buffer layer 201 is made of GaN material, and its function is to reduce lattice mismatch between subsequent epitaxial materials and the silicon substrate 1.
In another application example, the group III nitride and silicon heterogeneous integrated substrate can also be used for realizing an integrated ultraviolet sensor and ASIC. Among them, an asic (application Specific Integrated circuit) is considered as an Integrated circuit designed for a Specific purpose in the Integrated circuit field. An ultraviolet sensor (UV sensor) is a sensor that can convert an ultraviolet signal into a measurable electrical signal by means of a photovoltaic mode and a photoconductive mode using a photosensitive element. The earliest uv sensors were based on pure silicon, but according to the instructions of the national institute of standards and technology, pure silicon diodes also respond to visible light, forming electrical signals that are not originally needed, and resulting in poor accuracy. On the other hand, the accuracy of the GaN-based ultraviolet sensor is much higher than that of single crystal silicon, and the GaN-based ultraviolet sensor is the most commonly used ultraviolet sensor material.
As an example, as shown in fig. 3, for a group III nitride and silicon hetero-integrated substrate applied to an integrated UV sensor and ASIC, the group III nitride stacked structure 2 includes, from bottom to top, a buffer layer 206, a first unintentionally doped GaN layer 207, an N-type GaN layer 208, a second unintentionally doped GaN layer 209, and a P-type GaN layer 210.
In another example of an application, the group III nitride and silicon hetero-integrated substrate can also be used to implement integrated AlGaN HEMTs and CMOS ICs. The AlGaN HEMT is a High Electron Mobility Transistor (HEMT) using an AlGaN material. The mobility of two-dimensional electron gas formed by the GaN material and the AlGaN is more than 2000cm2The concentration of a carrier surface can reach 1013And the AlGaN/GaN HEMT is more suitable for application in high-frequency and high-power aspects. And a Complementary MOS Integrated Circuit (CMOS-IC) is formed by a PMOS transistor and an NMOS transistor.
As an example, as shown in fig. 4, for a group III nitride and silicon hetero-integrated substrate applied to an integrated AlGaN HEMT and CMOS IC, the group III nitride stacked structure 2 includes, in order from bottom to top, a buffer layer 211, an unintentionally doped GaN layer 212, an N-type GaN layer 213, and an AlGaN cap layer 214.
In another example of application, the group III nitride and silicon hetero-integrated substrate can also be used to implement integrated lasers (lasers) and drivers.
As an example, as shown in fig. 5, for a group III nitride and silicon hetero-integrated substrate applied to integrated laser and driving, the group III nitride stacked structure 2 includes, from bottom to top, a buffer layer 215, an unintentionally doped GaN layer 216, an AlGaN layer 217, an N-type GaN layer 218, an InGaN quantum well layer 219, a P-type AlGaN layer 220, and a P-type GaN layer 221 in this order.
Of course, in other embodiments, the specific composition of the group III nitride stacked structure 2 may vary according to the product of the application, and should not unduly limit the scope of the present invention.
According to the III-nitride and silicon heterogeneous integrated substrate, a silicon-based laminated structure and the III-nitride laminated structure are integrated on the same silicon substrate, wherein the silicon-based laminated structure can be used for manufacturing a traditional circuit, and various applications beyond molar can be realized by combining the III-nitride laminated structure. The III-nitride and silicon heterogeneous integrated substrate is compatible with CMOS, and can provide an important technical innovation platform for realizing 'surpassing Moore' law.
Example two
The present invention also provides a method for manufacturing a group III nitride and silicon heterogeneous integrated substrate, referring to fig. 6, which is a process flow diagram of the method, and includes the following steps:
s1: providing an SOI substrate which sequentially comprises a silicon substrate, a first insulating layer and a silicon layer from bottom to top;
s2: forming a second insulating layer on the surface of the silicon layer, and etching to obtain an epitaxial window; the epitaxial window sequentially penetrates through the second insulating layer, the silicon layer and the first insulating layer from top to bottom and exposes out of the silicon substrate;
S3: forming a side wall serving as an isolation structure on the side wall of the epitaxial window;
s4: epitaxially growing a group III nitride stack structure within the epitaxial window; the first insulating layer, the silicon layer and the second insulating layer form a silicon-based laminated structure;
s5: and forming a cap layer covering the surfaces of the silicon-based laminated structure and the III-nitride laminated structure.
Referring to fig. 7, step S1 is executed: an SOI substrate including a silicon substrate 1, a first insulating layer 301, and a silicon layer 302 in this order from bottom to top is provided.
Since conventional circuits are usually fabricated on Si (100) and group III nitrides are grown on Si (111), in the present invention, it is preferable to use a hybrid orientation substrate for the SOI substrate, in which the silicon substrate 1 uses (111) crystal orientation silicon and the silicon layer 302 uses (100) crystal orientation silicon. And the first insulating layer 301 as the buried insulating layer is typically made of silicon dioxide.
Specifically, the SOI substrate may be obtained by using a bonding technique, such as Smart-cut (Smart-cut) technique by Soitec corporation or Simbond (sambon) technique by nova corporation.
Bonding technology means that two wafers can be tightly bonded together by using bonding technology between silicon and silicon dioxide or between silicon dioxide and silicon dioxide, and a silicon dioxide layer is formed in the middle to serve as an insulating layer, and the bonded wafer is manufactured after being thinned to a required thickness on one side of the wafer.
The Smart-cut technology is a technology for implanting hydrogen ions and then peeling off, namely hydrogen ions are implanted into one bonded wafer and then bonded with another silicon wafer at a certain temperature, and when the temperature of bonding heat treatment is about 500 ℃, continuous cavities are formed at the hydrogen ion implantation positions, so that an SOI structure is formed by automatic peeling.
And an ultra-thin silicon layer can be obtained by an intelligent peeling technique using a bonding technique, and an SOI substrate of a mixed crystal orientation can be obtained.
Simmond is an oxygen implantation bonding technique that implants ions into a silicon material to create a uniformly distributed ion implanted layer that serves as a chemical etch stop and provides good control over the thickness of the device layer and its uniformity before final polishing of the wafer. The SOI silicon chip prepared by the Simbond technology has excellent SOI film uniformity and can obtain a thick insulating buried layer.
Then, referring to fig. 8, step S2 is executed: forming a second insulating layer 303 on the surface of the silicon layer 302, and etching to obtain an epitaxial window 6; the epitaxial window 6 sequentially penetrates through the second insulating layer 303, the silicon layer 302 and the first insulating layer 301 from top to bottom, and exposes the silicon substrate 1.
Specifically, the second insulating layer 303 may protect the surface of the silicon layer 302 and may also serve as an etching mask. In this embodiment, the second insulating layer 303 is preferably made of a silicon dioxide material.
Specifically, when the epitaxial window 6 is formed, a wet etching process is used for etching the intermediate insulating buried layer (the first insulating layer 301), so that defects formed on the surface of the silicon substrate 1 by dry etching can be avoided. While a high quality Si (111) substrate surface may provide a good growth base for subsequent epitaxial III-nitride growth.
Next, referring to fig. 9, step S3 is executed: and forming a side wall serving as the isolation structure 4 on the side wall of the epitaxial window 6.
Specifically, the sidewall spacer plays an isolation role, and includes but is not limited to insulating materials such as silicon dioxide and silicon nitride.
Referring to fig. 10, step S4 is executed: epitaxially growing a group III nitride stack structure 2 in the epitaxial window 6; the first insulating layer 301, the silicon layer 302 and the second insulating layer 303 form a silicon-based stacked structure 3.
In particular, the silicon-based stack 3 may be used to fabricate conventional circuits, and various applications beyond molar may be realized in conjunction with the III-nitride stack 2.
As an example, as shown in fig. 2, the group III nitride stacked structure 2 includes, from bottom to top, a buffer layer 201, an unintentionally doped GaN layer 202, an N-type GaN layer 203, an InGaN quantum well layer 204, and a P-type GaN layer 205. The group III-nitride and silicon hetero-integrated substrate comprising the group III-nitride stack structure 2 may be applied in the fabrication of integrated LEDs and drivers.
As an example, as shown in fig. 3, the group III nitride stacked layer structure 2 includes, in order from bottom to top, a buffer layer 206, a first unintentionally doped GaN layer 207, an N-type GaN layer 208, a second unintentionally doped GaN layer 209, and a P-type GaN layer 210. The group III-nitride and silicon hetero-integrated substrate comprising the group III-nitride stack structure 2 may be applied in the fabrication of integrated UV sensors and ASICs.
As an example, as shown in fig. 4, the group III nitride stacked structure 2 includes, from bottom to top, a buffer layer 211, an unintentionally doped GaN layer 212, an N-type GaN layer 213, and an AlGaN cap layer 214. The group III nitride and silicon hetero-integrated substrate including the group III nitride stacked structure 2 can be applied to the fabrication of integrated AlGaN HEMTs and CMOS ICs.
As an example, as shown in fig. 5, the group III nitride stacked layer structure 2 includes, from bottom to top, a buffer layer 215, an unintentionally doped GaN layer 216, an AlGaN layer 217, an N-type GaN layer 218, an InGaN quantum well layer 219, a P-type AlGaN layer 220, and a P-type GaN layer 221. The group III-nitride and silicon hetero-integrated substrate comprising the group III-nitride stack structure 2 may be applied in the fabrication of integrated lasers (lasers) and drivers.
Of course, in other embodiments, the specific composition of the group III nitride stacked structure 2 may vary according to the product of the application, and should not unduly limit the scope of the present invention.
Finally, referring to fig. 1, step S5 is executed: and forming a cap layer 5 covering the surfaces of the silicon-based laminated structure 3 and the III-nitride laminated structure 2.
Specifically, the cap layer 5 protects the silicon-based stacked structure 3 and the group III nitride stacked structure 2. In this embodiment, the capping layer 5 is preferably made of a silicon dioxide material.
The manufacturing method of the III-nitride and silicon heterogeneous integrated substrate has simple process, can manufacture various CMOS compatible novel III-nitride and silicon heterogeneous integrated substrates, and provides an important technical innovation platform for realizing 'exceeding Moore' law.
In summary, the group III nitride and silicon heterogeneous integrated substrate and the method for manufacturing the same of the present invention integrate the silicon-based stacked structure and the group III nitride stacked structure on the same silicon substrate, wherein the silicon-based stacked structure can be used for manufacturing a conventional circuit, and various applications beyond molar can be realized by combining the group III nitride stacked structure. The III-nitride and silicon heterogeneous integrated substrate and the novel heterogeneous integrated substrate obtained by the manufacturing method thereof are compatible with CMOS, and can provide an important technical innovation platform for realizing products exceeding Moore's law. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (4)
1. A method for manufacturing a group III nitride and silicon hetero-integrated substrate, comprising the steps of:
s1: providing an SOI substrate which sequentially comprises a silicon substrate, a first insulating layer and a silicon layer from bottom to top;
s2: forming a second insulating layer on the surface of the silicon layer, and etching to obtain an epitaxial window; the epitaxial window sequentially penetrates through the second insulating layer, the silicon layer and the first insulating layer from top to bottom and exposes out of the silicon substrate;
s3: forming a side wall serving as an isolation structure on the side wall of the epitaxial window;
s4: epitaxially growing a group III nitride stack structure within the epitaxial window; the first insulating layer, the silicon layer and the second insulating layer form a silicon-based laminated structure;
S5: forming a cap layer covering the surfaces of the silicon-based laminated structure and the III-nitride laminated structure;
the SOI substrate is obtained by adopting a bonding technology, and when the heat treatment temperature is about 500 ℃, a continuous cavity is formed at the hydrogen ion implantation position by adopting the bonding technology, so that an SOI structure is formed by automatic stripping; the SOI substrate adopts a mixed crystal orientation substrate, the silicon substrate adopts (111) crystal orientation silicon, and the silicon layer adopts (100) crystal orientation silicon; the silicon-based laminated structure is used for manufacturing a traditional circuit, and the traditional circuit is manufactured on the silicon layer; the lower surface of the cap layer is in contact with the upper surface of the III-nitride laminated structure, the upper surface of the isolation structure and the upper surface of the second insulating layer, and is used for protecting the silicon-based laminated structure and the III-nitride laminated structure; the III-group nitride laminated structure sequentially comprises a buffer layer, an unintentionally doped GaN layer, an N-type GaN layer and an AlGaN cap layer from bottom to top or sequentially comprises the buffer layer, the unintentionally doped GaN layer, the AlGaN layer, the N-type GaN layer, an InGaN quantum well layer, a P-type AlGaN layer and a P-type GaN layer from bottom to top, and the two-dimensional electron gas mobility of the GaN layer and the AlGaN layer in the III-group nitride laminated structure is more than 2000cm 2V.s, the surface concentration of the carrier reaches 1013Magnitude; in the step S2, wet process is adopted when the epitaxial window is formedAnd etching the first insulating layer by using a method etching process.
2. A group III nitride and silicon hetero-integrated substrate manufactured by the method for manufacturing a group III nitride and silicon hetero-integrated substrate according to claim 1, comprising:
a silicon substrate;
the III-nitride laminated structure is formed on the surface of the first preset area of the silicon substrate;
a silicon-based laminated structure formed on the surface of a second preset area of the silicon substrate; the silicon-based laminated structure sequentially comprises a first insulating layer, a silicon layer and a second insulating layer from bottom to top; the silicon-based laminated structure and the III-nitride laminated structure are isolated by an isolation structure;
and the cap layer covers the surfaces of the silicon-based laminated structure and the III-nitride laminated structure.
3. A group III nitride and silicon hetero-integrated substrate according to claim 2, characterized in that: the first insulating layer and the second insulating layer both comprise silicon dioxide materials.
4. A group III nitride and silicon hetero-integrated substrate according to claim 2, characterized in that: the cap layer comprises a silicon dioxide material.
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| CN116111456B (en) * | 2022-12-28 | 2024-03-19 | 上海铭锟半导体有限公司 | Silicon optical device integrated with III-V laser and manufacturing method thereof |
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| CN105529305A (en) * | 2015-12-17 | 2016-04-27 | 中航（重庆）微电子有限公司 | Three-layer hybrid crystal orientation on-insulator semiconductor structure and fabrication method thereof |
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| CN103021927A (en) * | 2012-12-26 | 2013-04-03 | 中国科学院上海微系统与信息技术研究所 | Hybrid coplanar SOI (silicon-on-insulator) substrate structure and preparation method thereof |
| CN105529305A (en) * | 2015-12-17 | 2016-04-27 | 中航（重庆）微电子有限公司 | Three-layer hybrid crystal orientation on-insulator semiconductor structure and fabrication method thereof |
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