CN107340994B - Processor - Google Patents
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- CN107340994B CN107340994B CN201710448018.1A CN201710448018A CN107340994B CN 107340994 B CN107340994 B CN 107340994B CN 201710448018 A CN201710448018 A CN 201710448018A CN 107340994 B CN107340994 B CN 107340994B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30181—Instruction operation extension or modification
- G06F9/30196—Instruction operation extension or modification using decoder, e.g. decoder per instruction set, adaptable or programmable decoders
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/30101—Special purpose registers
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
Abstract
The invention discloses a processor, comprising: the device comprises an instruction queue storage area, a configuration information storage area, a decoding control unit, an explicit decoder and an implicit decoder; the instruction queue storage area stores an instruction queue to be decoded; the configuration information storage area stores decoding constraint information; when each decoding period starts, the decoding control unit reads a plurality of instructions from the instruction queue storage area as the explicit instructions of the current decoding period and controls the explicit decoder to decode the explicit instructions according to the decoding constraint information in the configuration information storage area; and when the current decoding period is finished, taking the rest instructions decoded by the explicit decoder in the explicit instructions as implicit instructions of the next decoding period, and controlling the implicit decoder to decode the implicit instructions in the next decoding period. The embodiment of the invention realizes multi-instruction decoding through the logic circuit device, forms a decoding control flow capable of being continuously executed, optimizes the decoding design and improves the efficiency of instruction decoding and execution.
Description
Technical Field
The invention relates to the technical field of computers, in particular to a processor.
Background
The importance of information security is increasing due to the rapid development of information technology. To secure information, the security of the processor must be ensured. The secure processor is a key technology in the field of information security.
The current safety processor mainly realizes the safety processing of the processor by running encryption algorithm software. However, the probability of cracking the encryption algorithm is high, the overall performance of the processor is greatly reduced by the implementation of the encryption algorithm, and with the fact that the requirement on the data processing rate is higher and higher in practice, the safety of processing is ensured by simply using encryption algorithm software, so that the practical requirement cannot be met.
Disclosure of Invention
The present invention provides a processor to solve, in whole or in part, the above problems.
The invention provides a processor, comprising: the device comprises an instruction queue storage area, a configuration information storage area, a decoding control unit, an explicit decoder and an implicit decoder;
the instruction queue storage area is used for storing an instruction queue to be decoded;
the configuration information storage area is used for storing decoding constraint information;
the decoding control unit is used for reading a plurality of instructions from the instruction queue storage area as the explicit instructions of the current decoding period when each decoding period begins, and controlling the explicit decoder to decode the explicit instructions according to the decoding constraint information in the configuration information storage area;
when the current decoding period is finished, taking the rest instructions decoded by the explicit decoder in the explicit instructions as implicit instructions of the next decoding period, and controlling the implicit decoder to decode the implicit instructions in the next decoding period;
the explicit decoder is used for decoding the explicit instruction;
an implicit decoder is used to decode the implicit instruction.
Optionally, the decoding control unit is further configured to determine an association relationship between the explicit instruction and the implicit instruction according to the current decoding period;
and controlling the explicit decoder and the implicit decoder to decode the explicit instruction and the implicit instruction of the current decoding period in a serial or parallel mode.
Optionally, the processor further comprises: backing up the decoder;
the decoding control unit is also used for taking the residual instructions decoded by the implicit decoder in the implicit instructions of the current decoding period as backup instructions of the next decoding period when the current decoding period is finished, and controlling the backup decoder to decode the backup instructions in the next decoding period;
the backup decoder is used for decoding the backup instruction.
Optionally, the decoding control unit is further configured to control the explicit decoder, the implicit decoder, and the backup decoder to decode the explicit instruction, the implicit instruction, and the backup instruction of the current decoding cycle in a serial and/or parallel manner according to an association relationship between the explicit instruction, the implicit instruction, and the backup instruction of the current decoding cycle.
Optionally, the decode control unit is further configured to use an instruction carried by the implicit instruction in the current decode cycle as a backup instruction.
Optionally, the decoding control unit is further configured to control the backup decoder to decode the backup instruction in an empty manner in a decoding gap between the explicit decoder and the implicit decoder.
Optionally, the processor further comprises: an explicit instruction register and an implicit instruction register;
the decoding control unit is used for storing the explicit instruction to an explicit instruction register and storing the implicit instruction to an implicit instruction register; transferring the rest instructions in the explicit instruction register to an implicit instruction register when the current decoding period is finished;
the explicit decoder is used for decoding the explicit instruction in the explicit instruction register;
the implicit decoder is used for decoding an implicit instruction in the implicit instruction register.
Optionally, the processor further comprises: a backup instruction register;
the decoding control unit is used for storing the backup instruction to the backup instruction register; transferring the rest instructions in the implicit instruction register to a backup instruction register when the current decoding period is finished;
the backup decoder is used for decoding the backup instruction in the backup instruction register.
Optionally, the processor further comprises: configuring an information input interface;
the configuration information input interface is used for receiving decoding constraint information input by a user;
the configuration information storage area is connected with the configuration information input interface and used for acquiring the decoding constraint information from the configuration information input interface and updating and storing the decoding constraint information.
Optionally, the processor further comprises: an encryption and decryption unit;
the encryption and decryption unit is used for encrypting the decoding constraint information;
the configuration information storage area is used for storing encrypted decoding constraint information;
the encryption and decryption unit is also used for decrypting the encrypted decoding constraint information in the configuration information storage area;
the decoding control unit is used for reading the decoded decoding constraint information.
The embodiment of the invention has the beneficial effects that: the processor of the embodiment of the invention comprises: the device comprises an instruction queue storage area, a configuration information storage area, a decoding control unit, an explicit decoder and an implicit decoder; during actual work, the decoding control unit reads a plurality of instructions from the instruction queue storage area as the explicit instructions of the current decoding period when each decoding period starts, and controls the explicit decoder to decode the explicit instructions according to the decoding constraint information in the configuration information storage area; when the current decoding period is finished, taking the rest instructions decoded by the explicit decoder in the explicit instructions as implicit instructions of the next decoding period, and controlling the implicit decoder to decode the implicit instructions in the next decoding period; therefore, a plurality of instructions can be taken at one time, the unexecuted instructions are used as implicit instructions, compared with the method that one instruction is taken from the queue every time, the time is saved, the processing operation efficiency is improved on the basis of ensuring the processing safety, and the actual requirement is met.
Drawings
FIG. 1 is a block diagram of a processor in accordance with one embodiment of the invention;
fig. 2 is a block diagram of a processor according to another embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
Fig. 1 is a block diagram of a processor according to an embodiment of the present invention, and referring to fig. 1, a processor 100 according to the embodiment includes:
an instruction queue storage area 101, a configuration information storage area 103, a decode control unit 102, an explicit decoder 104, and an implicit decoder 105;
the instruction queue storage area 101 is used for storing an instruction queue to be decoded;
the configuration information storage area 103 is used for storing decoding constraint information;
the decoding control unit 102 is configured to, at the beginning of each decoding cycle, read a plurality of instructions from the instruction queue storage area 101 as explicit instructions of the current decoding cycle, and control the explicit decoder 104 to decode the explicit instructions according to the decoding constraint information in the configuration information storage area 103; when the current decoding period is finished, the rest of the explicit instructions decoded by the explicit decoder 104 in the explicit instructions are used as the implicit instructions of the next decoding period, and the implicit decoder 105 is controlled to decode the implicit instructions in the next decoding period;
the explicit decoder 104 is used to decode the explicit instruction;
the implicit decoder 105 is used to decode implicit instructions.
Note: the decoder is a multi-input multi-output combinational logic circuit device, and the main function of the decoder in the processor is to decode the instruction and translate the instruction into a corresponding output signal.
As shown in fig. 1, the processor according to the embodiment of the present invention can select a plurality of instructions to decode according to the decoding constraint information stored in the configuration information storage area, and can use an unprocessed instruction in a current decoding period as an implicit instruction in a next decoding period, so that the plurality of instructions form a decoding control flow that can be continuously executed, thereby optimizing the requirements of decoding design to the greatest extent and supporting the implementation of an optimized compiler algorithm. The execution efficiency is improved, the explicit decoder and the implicit decoder respectively execute decoding, the requirements of two aspects of safety and efficiency are met, and the competitiveness of the processor is improved.
In an embodiment of the present invention, the decode control unit 102 is further configured to determine an explicit instruction and an implicit instruction according to an association relationship between the explicit instruction and the implicit instruction in the current decode cycle; the explicit decoder 104 and the implicit decoder 105 are controlled to decode the explicit instruction and the implicit instruction of the current decoding cycle in a serial or parallel manner. The user instruction can be decoded at the same time, and decoding efficiency is improved. Fig. 2 is a block diagram of a processor according to another embodiment of the present invention, and referring to fig. 2, a processor 200 according to this embodiment includes:
an instruction queue storage area 201, a configuration information storage area 203, a decoding control unit 202, an explicit decoder 204, an implicit decoder 205, a backup decoder 206, an explicit instruction register 209, an implicit instruction register 208, a backup instruction register 207, a configuration information input interface 205, and an encryption/decryption unit 210.
The decoding control unit mainly controls the decoding and execution of various instruction configuration file codes to form a decoding control flow capable of being continuously executed, and normal and quick execution of instruction decoding work is guaranteed.
The functions of the instruction queue storage area 201, the configuration information storage area 203, the explicit decoder 204, and the implicit decoder 205 are the same as those in the foregoing embodiment, so that reference may be made to the description of the foregoing embodiment, which is not described herein again. The following describes the contents of the processor of the present embodiment different from the aforementioned embodiments.
Referring to fig. 2, the processor 200 of the present embodiment further includes: the backup decoder 206 is configured to back up the decoder,
the decoding control unit 202 is further configured to, when the current decoding cycle ends, use the remaining instructions decoded by the implicit decoder 205 in the implicit instructions of the current decoding cycle as backup instructions of the next decoding cycle, and control the backup decoder 206 to decode the backup instructions in the next decoding cycle;
here, the backup decoder 206 functions to decode the backup instruction.
In this embodiment, the decoding control unit 202 is further configured to control the explicit decoder 204, the implicit decoder 205, and the backup decoder 206 to decode the explicit instruction, the implicit instruction, and the backup instruction in the current decoding cycle in a serial and/or parallel manner according to an association relationship between the explicit instruction, the implicit instruction, and the backup instruction in the current decoding cycle.
It should be noted that, unlike the prior art, the decode control unit in the processor according to the embodiment of the present invention can control to execute decoding of the explicit instruction, the implicit instruction, and the backup instruction of the current decode cycle in series according to the association relationship between the explicit instruction, the implicit instruction, and the backup instruction of the current decode cycle, or control to execute decoding of the explicit instruction, the implicit instruction, and the backup instruction of the current decode cycle in parallel, or control to decode the explicit instruction, the implicit instruction, and the backup instruction of the current decode cycle in a series and parallel manner.
The serial execution instruction generally waits for the previous instruction to finish execution before executing the next instruction, and the parallel execution instruction is the execution of a plurality of instructions in parallel.
In this embodiment, the decoding control unit 202 is further configured to use the remaining instructions decoded by the implicit decoder in the implicit instructions in the current decoding cycle as backup instructions of the next decoding cycle.
And the decoding control unit 202 is further configured to control the backup decoder 206 to decode the backup instruction in an empty manner in the decoding gaps of the explicit decoder 204 and the implicit decoder 205. The decoding efficiency of the instruction can be greatly improved by processing the decoding of the backup instruction in an inserting mode.
As shown in fig. 2, the processor of this embodiment includes an explicit instruction decoder, an implicit instruction decoder, and a backup instruction decoder, thereby implementing parallel decoding and serial decoding (in the form of logical and or not) of the explicit instruction, the implicit instruction, and the backup instruction, and the three decoders work together to ensure that the execution result of the program instruction stream achieves the parallel effect.
Referring to fig. 2, in the present embodiment, the processor 200 further includes: an explicit instruction register 209 and an implicit instruction register 208;
the decode control unit 202 is used to store the explicit instruction into the explicit instruction register 209 and the implicit instruction into the implicit instruction register 208;
transferring the remaining instructions in the explicit instruction register 209 to the implicit instruction register 208 at the end of the current decode cycle;
it should be noted that the explicit decoder 204 is used to decode the explicit instruction in the explicit instruction register 209; the implicit decoder 205 functions to decode implicit instructions in the implicit instruction register 208.
Referring to fig. 2, the processor 200 in this embodiment further includes: a backup instruction register 207;
a decode control unit 202, configured to store the backup instruction in the backup instruction register 207; transferring the remaining instructions in the implicit instruction register 208 to the backup instruction register 207 at the end of the current decode cycle;
note: the backup decoder 206 is used for decoding the backup instruction in the backup instruction register 207.
As can be seen from the above, by providing the explicit decoder, the implicit decoder, and the backup decoder in the processor according to the embodiments of the present invention, it is possible to select multiple instructions at the beginning of each decoding period and use the selected instructions as the explicit instruction of the current decoding period, control the explicit decoder to decode, and if the selected explicit instruction is not completely decoded by the explicit decoder when the current decoding period ends, decode the remaining instructions that are not decoded in the currently selected explicit instruction as the implicit instruction of the next decoding period. In addition, when the current decoding period is finished, the rest of instructions decoded by the implicit decoder in the implicit instructions of the current decoding period are used as backup instructions of the next decoding period, and the backup decoder is controlled to decode the backup instructions in the next decoding period, so that a continuously executable instruction stream is formed, the decoding design is optimized to the greatest extent, and the efficiency of multi-instruction decoding is improved.
Referring to fig. 2, the processor 200 in this embodiment further includes: a configuration information input interface 205;
the configuration information input interface 205 is mainly used for receiving decoding constraint information input by a user;
the configuration information storage area 203 is connected with the configuration information input interface 205, and the configuration information storage area 203 is used for acquiring decoding constraint information from the configuration information input interface 205 and updating the storage.
And, referring to fig. 2, the processor 200 further includes: the encryption/decryption unit 210 is provided with a function,
the encryption and decryption unit 210 is configured to encrypt the decoding constraint information;
the configuration information storage area 203 is used for storing encrypted decoding constraint information;
the encryption and decryption unit 210 is further configured to decrypt the encrypted decoding constraint information in the configuration information storage area 203; the decoding control unit 202 is configured to read the decoded decoding constraint information.
Therefore, the processor of the embodiment can improve the processing safety by carrying out encryption operation on the decoding constraint information for selecting the decoding instruction, and ensure the safety and stability of the processor.
The working process of the processor of the embodiment is as follows:
firstly, decoding constraint information input by a user is received through a configuration information input interface of a processor.
The decoding constraint information may be delay constraint information, splicing constraint information, replacement constraint information, ordering constraint information, and the like of the instruction, which are used to constrain the decoding of the instruction. Specifically, the delay constraint information of the instruction is to constrain the current instruction to be decoded after delaying for a predetermined time (for example, delaying for one instruction cycle or delaying for two instruction cycles), and the splicing constraint information indicates which part of the current instruction or the current instruction needs to be spliced with other instructions. By analogy, these decode constraint information limits the decode execution process of instructions.
And after receiving decoding constraint information input by a user, storing the decoding constraint information into a configuration information storage area.
Then, when each decoding period starts, a decoding control unit of the processor reads a plurality of instructions from the instruction queue storage area as the explicit instructions of the current decoding period, and controls the explicit decoder to decode the explicit instructions according to the decoding constraint information in the configuration information storage area; when the current decoding period is finished, taking the rest instructions decoded by the explicit decoder in the explicit instructions as implicit instructions of the next decoding period, and controlling the implicit decoder to decode the implicit instructions in the next decoding period; the explicit decoder is used for decoding the explicit instruction; an implicit decoder is used to decode the implicit instruction.
For example, the instruction queue storage area stores 20 instructions in the instruction queue to be decoded, and the configuration information storage area stores one or more decoding constraint information for each instruction input by the user.
The decoding control unit reads a plurality of instructions (for example, 8 instructions) from the 20 instructions stored in the instruction queue storage area as the explicit instructions of the first decoding cycle at the beginning of the first decoding cycle, and controls the explicit decoder to sort and then decode the explicit instructions of the first decoding cycle according to the decoding constraint information (for example, the sorting constraint information) in the configuration information storage area.
When the first decoding period is finished, the decoding control unit counts and marks the instructions which are not decoded by the explicit decoder in the 8 instructions, takes the instructions which are not decoded by the explicit decoder in the current period as the implicit instructions of the second decoding period, and controls the implicit decoder to decode the implicit instructions of the second decoding period.
It is to be understood that when the second decoding cycle arrives, the decoding control unit may continue to read a plurality of instructions, for example, 5 instructions, from the 12 instructions stored in the instruction queue storage area as the explicit instruction of the second decoding cycle, and control the explicit decoder to decode the explicit instruction of the second decoding cycle according to the decoding constraint information in the configuration information storage area.
And the process is circulated until all the instructions stored in the instruction queue storage area of the processor are decoded.
Further, when the processor of this embodiment further includes a backup instruction decoder, the processor further includes, based on the above working process: when the current decoding period is finished, taking the residual instructions decoded by the implicit decoder in the implicit instructions of the current decoding period as backup instructions of the next decoding period, and controlling the backup decoder to decode the backup instructions in the next decoding period;
in the above example, the first decoding cycle begins by selecting 8 instructions as explicit instructions, and the explicit instruction decoder processes only 4 instructions in the first decoding cycle, and the remaining 4 instructions are decoded by the implicit instruction decoder as implicit instructions in the second decoding cycle.
In the second decoding period, the implicit instruction decoder only processes 1 instruction in the 4 instructions, and the remaining 3 instructions are used as backup instructions in the third decoding period and decoded by the backup instruction decoder.
Therefore, the processor of the embodiment includes three-dimensional decoder devices (an explicit instruction decoder, an implicit instruction decoder, and a backup instruction decoder) to support parallel execution of decoding of multiple instruction profiles, and the three-dimensional decoder devices act together; forming a continuously executable decoding control flow, and supporting the optimized decoding of instruction parallel and serial operations; the requirement of maximum optimization decoding design is realized, and the realization of an optimization compiler algorithm is supported.
In summary, the present invention provides such a processor, including: the device comprises an instruction queue storage area, a configuration information storage area, a decoding control unit, an explicit decoder and an implicit decoder; during actual work, the decoding control unit reads a plurality of instructions from the instruction queue storage area as the explicit instructions of the current decoding period when each decoding period starts, and controls the explicit decoder to decode the explicit instructions according to the decoding constraint information in the configuration information storage area; when the current decoding period is finished, taking the rest instructions decoded by the explicit decoder in the explicit instructions as implicit instructions of the next decoding period, and controlling the implicit decoder to decode the implicit instructions in the next decoding period; therefore, a plurality of instructions of a user can form a decoding stream which can be continuously executed, the decoding design is optimized, the processing efficiency is improved on the basis of ensuring the processing safety, and the actual requirement is met.
The above description is only for the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention shall fall within the protection scope of the present invention.
Claims (7)
1. A processor, comprising: the device comprises an instruction queue storage area, a configuration information storage area, a decoding control unit, an explicit decoder and an implicit decoder;
the instruction queue storage area is used for storing an instruction queue to be decoded;
the configuration information storage area is used for storing decoding constraint information;
the decoding control unit is used for reading a plurality of instructions from the instruction queue storage area as explicit instructions of the current decoding period when each decoding period begins, and controlling the explicit decoder to decode the explicit instructions according to decoding constraint information in the configuration information storage area; when the current decoding period is finished, taking the rest instructions decoded by the explicit decoder in the explicit instructions as implicit instructions of the next decoding period, and controlling the implicit decoder to decode the implicit instructions in the next decoding period;
the explicit decoder is to decode an explicit instruction; the implicit decoder is used for decoding an implicit instruction;
the processor further comprises: backing up the decoder;
the decoding control unit is further configured to use, when the current decoding cycle is ended, the remaining instructions decoded by the implicit decoder in the implicit instructions of the current decoding cycle as backup instructions of a next decoding cycle, and control the backup decoder to decode the backup instructions in the next decoding cycle;
the backup decoder is used for decoding the backup instruction;
the decoding control unit is further used for controlling the explicit decoder, the implicit decoder and the backup decoder to decode the explicit instruction, the implicit instruction and the backup instruction of the current decoding period in a serial and/or parallel mode according to the incidence relation among the explicit instruction, the implicit instruction and the backup instruction of the current decoding period.
2. The processor of claim 1,
the decoding control unit is also used for taking an instruction carried by the implicit instruction in the current decoding period as a backup instruction.
3. The processor of claim 2,
the decoding control unit is also used for controlling the backup decoder to decode the backup instruction in an inserting manner in the decoding gaps of the explicit decoder and the implicit decoder.
4. The processor of claim 1 or 2, wherein the processor further comprises: an explicit instruction register and an implicit instruction register;
the decoding control unit is used for storing an explicit instruction into the explicit instruction register and storing an implicit instruction into the implicit instruction register; transferring remaining instructions in the explicit instruction register into the implicit instruction register at the end of a current decode cycle;
the explicit decoder is used for decoding an explicit instruction in the explicit instruction register;
the implicit decoder is used for decoding an implicit instruction in the implicit instruction register.
5. The processor of claim 4, wherein the processor further comprises: a backup instruction register;
the decoding control unit is used for storing a backup instruction to the backup instruction register; transferring the remaining instructions in the implicit instruction register to the backup instruction register at the end of the current decode cycle;
the backup decoder is used for decoding the backup instruction in the backup instruction register.
6. The processor of claim 1, wherein the processor further comprises: configuring an information input interface;
the configuration information input interface is used for receiving decoding constraint information input by a user;
the configuration information storage area is connected with the configuration information input interface and used for acquiring decoding constraint information from the configuration information input interface and updating and storing the decoding constraint information.
7. The processor of claim 1, wherein the processor further comprises: an encryption and decryption unit;
the encryption and decryption unit is used for encrypting the decoding constraint information;
the configuration information storage area is used for storing encrypted decoding constraint information;
the encryption and decryption unit is also used for decrypting the encrypted decoding constraint information in the configuration information storage area;
the decoding control unit is used for reading the decoded decoding constraint information.
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| CN107340994B (en) * | 2017-06-14 | 2020-11-17 | 北京多思安全芯片科技有限公司 | Processor |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1431588A (en) * | 2002-01-08 | 2003-07-23 | 北京南思达科技发展有限公司 | Logic reorganizable circuit |
| CN107340994A (en) * | 2017-06-14 | 2017-11-10 | 北京天宏绎网络技术有限公司 | A kind of processor |
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| US8904151B2 (en) * | 2006-05-02 | 2014-12-02 | International Business Machines Corporation | Method and apparatus for the dynamic identification and merging of instructions for execution on a wide datapath |
| US9424045B2 (en) * | 2013-01-29 | 2016-08-23 | Arm Limited | Data processing apparatus and method for controlling use of an issue queue to represent an instruction suitable for execution by a wide operand execution unit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1431588A (en) * | 2002-01-08 | 2003-07-23 | 北京南思达科技发展有限公司 | Logic reorganizable circuit |
| CN107340994A (en) * | 2017-06-14 | 2017-11-10 | 北京天宏绎网络技术有限公司 | A kind of processor |
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