CN107332572B - Quick configurable Turbo encoder and encoding method - Google Patents
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- CN107332572B CN107332572B CN201710426548.6A CN201710426548A CN107332572B CN 107332572 B CN107332572 B CN 107332572B CN 201710426548 A CN201710426548 A CN 201710426548A CN 107332572 B CN107332572 B CN 107332572B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
- H03M13/2957—Turbo codes and decoding
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
- H03M13/2703—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques the interleaver involving at least two directions
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- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
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Abstract
The invention discloses a rapidly configurable Turbo encoder, and relates to the field of wireless communication. The encoder comprises an interleaving generation unit, a data processing unit, a data storage unit, a puncturing generation unit and an encoding unit. The invention mainly has three design points, namely, quick coding, finishing the interleaving process in data recombination and finishing the deletion process in a coding unit; secondly, the method is flexible and configurable, and an intra-row transformation sequence, an inter-row transformation sequence, a puncturing sequence and a component encoder can be externally configured by the encoder; and thirdly, the resource expense is small, the interleaving sequence does not need to be subjected to parallel-serial conversion, two paths of codes are controlled by one set of state machine, and the coding result does not need to store the deleted check sequence. The Turbo encoder of the invention is beneficial to the long-term evolution and development of the system.
Description
Technical Field
The invention relates to a wireless communication system, in particular to a quick configurable Turbo encoder supporting WCDMA, LTE, satellite mobile communication and other systems.
Background
As the coding length increases, Turbo codes can approach the shannon limit indefinitely under Additive White Gaussian Noise (AWGN) channel conditions. Turbo codes are widely used in wireless communication systems because of good bit error performance.
The conventional Turbo encoder is composed of an interleaver and two RSC component encoders, the interleaver can generate an interleaving table of coding length, or the interleaving table with the coding length configured outside carries out parallel-to-serial conversion on coding bits and then carries out interleaving, the coding bits and the interleaving bits respectively pass through the two component encoders, the RSC component encoders output all check sequences, and then coding results are obtained through puncturing processing.
Therefore, in order to conveniently research the Turbo code in each communication system, a fast configurable Turbo encoder needs to be designed, and the encoding structure can be compatible with each communication system. Moreover, the design and selection of each module in the Turbo encoder have great influence on the BER performance of the Turbo code, such as the design of an interleaver, the design of a component encoder, the design of a puncturing matrix and the like, and particularly, the satellite mobile communication system in China is still in an exploration stage, so that it is necessary to design an encoder structure which is fast, flexible and configurable in encoding parameters, simple in structure and easy to implement.
Disclosure of Invention
The invention aims to provide a fast configurable Turbo encoder.
The technical scheme adopted by the invention is as follows:
a fast configurable Turbo encoder comprising the following modules:
an interleaving generation unit for generating an intra-line transform sequence L1 and an inter-line transform sequence L2 according to the length of coded bits, or receiving an externally configured intra-line transform sequence L1 and an inter-line transform sequence L2;
the data reorganization unit is used for calling the coded data in the data storage unit, carrying out bit reorganization on the coded data, reorganizing the coded data into a first reorganization sequence C1 with the bit width of C and the address length of R, and storing the first reorganization sequence C1 in the data storage unit; the interleaving unit is also used for calling the intra-row conversion sequence L1 and the inter-row conversion sequence L2 in the interleaving generation unit to carry out data reorganization on the first reorganization sequence C1, reorganize the data into a second reorganization sequence C2 with the bit width of C and the address length of R, and store the second reorganization sequence C2 in the data storage unit; wherein, C is the length of the intra-row transformation sequence L1, and R is the length of the inter-row transformation sequence L2;
the data storage unit is used for receiving externally input coded data and outputting a coding result; the coding device is also used for storing the coding data, the recombination sequence and the coding result;
a puncturing generation unit for generating a puncturing sequence D1 of the first check sequence according to a puncturing rule, generating a puncturing sequence D2 of the second check sequence, or receiving externally configured puncturing sequences D1 and D2;
and the coding unit is used for calling the first recombination sequence C1 and the second recombination sequence C2 in the data storage unit and simultaneously coding, calling the puncture sequences D1 and D2 in the puncture generation unit respectively to control the generation of the first check sequence and the second check sequence in a one-to-one correspondence mode in the coding process, and storing the coding result in the data storage unit according to a bit arrangement rule.
The intra-row conversion sequence L1 is composed of R groups of sub-sequences with the length of C, the address of the sub-sequence represents the bit sequence in the row before conversion, the data of the sub-sequence represents the bit sequence after the intra-row conversion and is composed of data between 0 and C-1; the address of the interline transformation sequence L2 represents the interline order before transformation, and the data of the interline transformation sequence L2 represents the interline order after the interline transformation, and is composed of data from 0 to R-1; wherein the length C of the sub-sequence of the intra-row transform sequence L1 and the length R of the inter-row transform sequence L2 are set by the coding length and the interleaving rule adopted by the coding.
Wherein, the output memory addresses of the first recombination sequence C1 are in the order of 0 to R-1; the second recombination sequence C2 performs bit sequence adjustment in the corresponding rows according to the intra-row conversion sequence L1 sub-sequence, and outputs the storage addresses in the order of the inter-row conversion sequence L2.
The addresses of the puncturing sequences D1 and D2 respectively represent the puncturing sequence in the first check sequence and the second check sequence in a one-to-one correspondence manner, the data of the puncturing sequences D1 and D2 respectively represent the puncturing positions in the first check sequence and the second check sequence in a one-to-one correspondence manner, and the lengths of the puncturing sequences D1 and D2 are set by the coding length and the puncturing rule.
The encoding unit comprises an RSC encoder, the encoding process of the RSC encoder is controlled by a set of state machines, and the RSC encoding generating polynomial is configured or set outside the encoder.
An encoding method comprising the steps of:
(1) configuring parameters of an interleaving generation unit, a puncturing generation unit and an encoding unit, and storing encoded data into a data storage unit;
(2) starting an interleaving generation unit and a puncturing generation unit, and respectively generating an intra-row transformation sequence L1, an inter-row transformation sequence L2, a puncturing sequence D1 and a puncturing sequence D2;
(3) starting a data reorganization unit, calling the encoded data in the data storage unit and an intra-row transformation sequence L1 and an inter-row transformation sequence L2 in an interleaving generation unit, generating a first reorganization sequence C1 and a second reorganization sequence C2 according to the intra-row transformation sequence L1 and the inter-row transformation sequence L2, and storing the first reorganization sequence C1 and the second reorganization sequence C2 in the data storage unit;
(4) starting an encoding unit, calling a first recombination sequence C1 and a second recombination sequence C2 in a data storage unit, encoding the first recombination sequence C1 and the second recombination sequence C2, calling a puncturing sequence D1 and a puncturing sequence D2 in a puncturing generation unit respectively to control the generation of a first check sequence and a second check sequence in a one-to-one correspondence mode in the encoding process, and obtaining an encoding result and storing the encoding result in the data storage unit;
(5) and the data storage unit outputs the coding result.
In the step (2), the in-line conversion sequence L1 is composed of R groups of sub-sequences with the length of C, the address of the sub-sequence represents the bit sequence in the line before conversion, the data of the sub-sequence represents the bit sequence after the in-line conversion, and the sub-sequence is composed of the data between 0 and C-1; the address of the inter-line transition sequence L2 represents the inter-line sequence before transition, and the data of L2 represents the inter-line sequence after the inter-line transition, and is composed of data from 0 to R-1; wherein the length C of the L1 subsequence and the length R of the L2 subsequence are determined by the coding length and the interleaving rule adopted by the coding.
Wherein, the step (3) is specifically as follows:
starting a data reorganization unit, calling the coded data in the data storage unit, performing bit reorganization on the coded data to reorganize the coded data into a first reorganization sequence C1 with the bit width of C and the address length of R, and storing the first reorganization sequence C1 into the data storage unit according to the sequence from 0 to R-1; calling an intra-row conversion sequence L1 and an inter-row conversion sequence L2 in an interleaving generation unit, firstly, adjusting the bit sequence of a first recombination sequence C1 in a corresponding row according to a sub-sequence of the intra-row conversion sequence L1, recombining the first recombination sequence into a second recombination sequence C2 with the bit width of C and the address length of R, and storing the second recombination sequence C2 in a data storage unit according to the sequence of the inter-row conversion sequence L2; where C is the length of the intra-line transform sequence L1 and R is the length of the inter-line transform sequence L2.
Wherein, the addresses of the puncturing sequences D1 and D2 in step (2) respectively represent the puncturing order in the first check sequence and the second check sequence in a one-to-one correspondence manner, the data of the puncturing sequences D1 and D2 respectively represent the puncturing positions in the first check sequence and the second check sequence in a one-to-one correspondence manner, and the lengths of the puncturing sequences D1 and D2 are determined by the coding length and the puncturing rule.
Wherein, the RSC encoder is adopted for encoding the first recombination sequence C1 and the second recombination sequence C2 in the step (4), and the RSC encoding generating polynomial is externally configured or set by the encoder.
Compared with the background technology, the invention has the following advantages:
1. the invention can realize quick coding, the interleaving process is finished in data recombination, the deletion process is finished in a coding unit, the data processing time and the storage resource are saved, and the FPGA and the ASIC are easy to realize.
2. The invention is flexible and configurable, and the intra-row transformation sequence, the inter-row transformation sequence, the puncturing sequence and the component encoder can be configured from the outside of the encoder;
3. the invention has small resource overhead, the interweaving sequence does not need to carry out parallel-serial conversion, two paths of codes are controlled by a set of state machine, and the coding result does not need to store the deleted check sequence and the like. The design is beneficial to the long-term evolution and development of the system.
Drawings
Fig. 1 is an overall schematic block diagram of the present invention.
Fig. 2 is a detailed diagram of an encoding unit in the present invention.
Detailed Description
The implementation of the present invention is further described below with reference to fig. 1 to 2.
The overall principle diagram of the invention is shown in fig. 1, and comprises the following modules:
an interleaving generation unit for generating an intra-line transform sequence L1 and an inter-line transform sequence L2 according to the length of coded bits, or receiving an externally configured intra-line transform sequence L1 and an inter-line transform sequence L2; the intra-row conversion sequence L1 is composed of R groups of sub-sequences with the length of C, the address of the sub-sequence represents the bit sequence in the row before conversion, the data of the sub-sequence represents the bit sequence after the intra-row conversion and is composed of data between 0 and C-1; the address of the interline transformation sequence L2 represents the interline order before transformation, and the data of the interline transformation sequence L2 represents the interline order after the interline transformation, and is composed of data from 0 to R-1; wherein the length C of the sub-sequence of the intra-row transform sequence L1 and the length R of the inter-row transform sequence L2 are set by the coding length and the interleaving rule adopted by the coding.
The data reorganization unit is used for calling the coded data in the data storage unit, carrying out bit reorganization on the coded data to reorganize the coded data into a first reorganization sequence C1 with the bit width of C and the address length of R, and storing the first reorganization sequence C1 into the data storage unit according to the sequence from 0 to R-1; calling an intra-row conversion sequence L1 and an inter-row conversion sequence L2 in an interleaving generation unit, firstly, adjusting the bit sequence of a first recombination sequence C1 in a corresponding row according to a sub-sequence of the intra-row conversion sequence L1, recombining the first recombination sequence into a second recombination sequence C2 with the bit width of C and the address length of R, and storing the second recombination sequence C2 in a data storage unit according to the sequence of the inter-row conversion sequence L2; where C is the length of the intra-line transform sequence L1 and R is the length of the inter-line transform sequence L2.
The data storage unit is used for receiving externally input coded data, supporting any bit width from 1 bit to 32 bits by the coded input data and outputting a coded result; the coding device is also used for storing the coding data, the recombination sequence and the coding result;
a puncturing generation unit for generating a puncturing sequence D1 of the first check sequence according to a puncturing rule, generating a puncturing sequence D2 of the second check sequence, or receiving externally configured puncturing sequences D1 and D2; the addresses of the puncturing sequences D1 and D2 respectively represent the puncturing sequence in the first check sequence and the second check sequence in a one-to-one correspondence manner, the data of the puncturing sequences D1 and D2 respectively represent the puncturing positions in the first check sequence and the second check sequence in a one-to-one correspondence manner, and the lengths of the puncturing sequences D1 and D2 are set by the coding length and the puncturing rule.
The structure of the encoding unit is shown in fig. 2, the encoding unit comprises an RSC encoder, the encoding process is controlled by a set of state machines, and an RSC encoding generating polynomial of the RSC encoder is configured or set outside the encoder.
The working principle is that a first recombination sequence C1 and a second recombination sequence C2 in a data storage unit are called and encoded simultaneously, in the encoding process, puncturing sequences D1 and D2 in a puncturing generation unit are called respectively to control the generation of a first check sequence and a second check sequence in a one-to-one correspondence mode, and the encoding result is stored in the data storage unit according to a bit arrangement rule.
An encoding method comprising the steps of:
firstly, configuring parameters of an interleaving generation unit, a puncturing generation unit and a coding unit, and inputting coded data into a coded data area in a data storage unit, wherein if the coded length is 100 and the bit width is 8, the occupied address length is 13;
secondly, starting an interleaving generation unit and a puncturing generation unit to correspondingly generate an intra-row transformation sequence L1, an inter-row transformation sequence L2, a puncturing sequence D1 and a puncturing sequence D2 respectively;
the intra-row transform sequence L1 and the inter-row transform sequence L2 are generated as required, and the generation of the two sequences is determined by the interleaving rule, which is not described in detail herein. For example, in WCDMA system, the interleaver uses prime number interleaving algorithm, and needs to configure the interleaving length, i.e. the code bit length. Assuming that the length is 100, the inter-line transform sequence L2 generated according to the interleaving rule has a length of 5, L2 is [4,3,2,1,0], the intra-line transform sequence L1 is composed of 5 sub-sequences having a length of 20, and L1[0] is [1,10,5,12,6,3,11,15,17,18,9,14,7,13,16,8,4,2,0,19 ]; l1[1] ═ 1,3,9,8,5,15,7,2,6,18,16,10,11,14,4,12,17,13,0, 19; l1[2] ═ 1,15,16,12,9,2,11,13,5,18,4,3,7,10,17,8,6,14,0, 19; l1[3] ═ 1,14,6,8,17,10,7,3,4,18,5,13,11,2,9,12,16,15,0, 19; l1[4] ═ 19,2,4,8,16,13,7,14,9,18,17,15,11,3,6,12,5,10,0, 1; namely, R is 5 and C is 20. L1 and L2 may also be configured directly from outside the encoder.
And generating puncturing sequences D1 and D2 according to the puncturing rule. For example, when the encoding bit length is 100, 90 bits remain after puncturing in the check sequence 1,91 bits remain after puncturing in the check sequence 2, and the puncturing sequence D1 generated according to the puncturing rule is [9,19,29,39,49,59,69,79,89,99], and D2 is [11,21,31,41,51,61,71,81,91 ]. D1 and D2 may also be configured directly from outside the encoder.
Thirdly, starting a data reorganization unit, calling the coded data in the data storage unit, performing bit reorganization on the coded data to reorganize the coded data into a first reorganization sequence C1 with the bit width of C and the address length of R, and storing the first reorganization sequence C1 in the data storage unit according to the sequence from 0 to R-1; calling an intra-row conversion sequence L1 and an inter-row conversion sequence L2 in an interleaving generation unit, firstly, adjusting the bit sequence of a first recombination sequence C1 in a corresponding row according to a sub-sequence of the intra-row conversion sequence L1, recombining the first recombination sequence into a second recombination sequence C2 with the bit width of C and the address length of R, and storing the second recombination sequence C2 in a data storage unit according to the sequence of the inter-row conversion sequence L2; where C is the length of the intra-line transform sequence L1 and R is the length of the inter-line transform sequence L2.
Carrying out data reorganization on the coded bits according to the R and C values, reading the coded bits into a data reorganization unit sequentially, wherein the coded bits are 100 in length, 8 in width, 13 in length, reorganized into a data array C1 with 20 in width and 5 in length according to the bit sequence, and outputting and storing C1 in the sequence of [0,1,2,3,4 ]; meanwhile, bit sequence conversion is carried out on bits of each line of C1 according to a corresponding subsequence of the intra-line conversion sequence L1, and a result after conversion is output and stored according to the sequence of the inter-line conversion sequence L2. For example, C1[0] ═ 11111111110000000000], performs intra-row conversion in the order of L1[0], and stores the address output in the order of L2[0], i.e., C2[4] ═ 10101100001010011110], and so on. The reorganized data is stored in a reorganizing data area in the data storage unit.
Fourthly, starting a coding unit, calling a first recombination sequence C1 and a second recombination sequence C2 in the data storage unit, coding the first recombination sequence C1 and the second recombination sequence C2, calling a puncturing sequence D1 and a puncturing sequence D2 in the puncturing generation unit respectively to control the generation of the first check sequence and the second check sequence in a one-to-one correspondence mode in the coding process, and obtaining a coding result and storing the coding result in the data storage unit;
RSC encoding is carried out in an encoding unit, and the RSC component encoder is configurable, namely 8-state sub-code generator polynomial is flexible and configurable. For example, in a WCDMA system, the coding matrix function of a component coding 8-state sub-coder is
Wherein, g0(D)＝1+D2+D3Is a feedback polynomial.
g1(D)＝1+D+D3Is a feed forward polynomial.
Referring to FIG. 2, [ g0, g1, g2, g 3] may be configured]Is [1,1,0, 1]]Implementing a feedforward polynomial g1(D)＝1+D+D3(ii) a Configuration [ g4, g5, g6, g7 ]]Is [1,0, 1]]Implementing a feedback polynomial g0(D)＝1+D2+D3。
The reconstruction data C1 and C2, for example C1[0], are read in sequentially during the encoding process]And C2[ 0]]And simultaneously entering an encoding unit, carrying out bit shift addition under the control of the same state machine, and determining whether check bits are output or not by combining the puncturing sequences D1 and D2 when the check sequence is generated. The bit output sequence of the encoder is configurable, supporting two bit output sequences S1And S2. Suppose an information sequence bit is represented as x1,x2,x3,…,xk]Check sequence 1 bit is represented as [ z ]1,z2,z3,…,zk]Check sequence 2 bits are represented as [ z'1,z′2,z′3,…,z′k]. For example, in a WCDMA system, the bit output order needs to be configured as S1[x1,z1,z′1,x2,z2,z′2,…,xk,zk,z′k]. In China satellite mobile communication system, the bit output sequence needs to be configured as S2[x1,x2,…,xk,z1,z2,…,zk,z′1,z′2,…,z′k]。
And fifthly, outputting the coding result by the data storage unit.
Compared with the conventional Turbo encoder, the method has great advantages in encoding speed and flexibility, and is beneficial to long-term evolution of a communication system.
Claims (10)
1. A fast configurable Turbo encoder comprising:
an interleaving generation unit for generating an intra-line transform sequence L1 and an inter-line transform sequence L2 according to the length of coded bits, or receiving an externally configured intra-line transform sequence L1 and an inter-line transform sequence L2;
the data reorganization unit is used for calling the coded data in the data storage unit, carrying out bit reorganization on the coded data, reorganizing the coded data into a first reorganization sequence C1 with the bit width of C and the address length of R, and storing the first reorganization sequence C1 in the data storage unit; the interleaving unit is also used for calling the intra-row conversion sequence L1 and the inter-row conversion sequence L2 in the interleaving generation unit to carry out data reorganization on the first reorganization sequence C1, reorganize the data into a second reorganization sequence C2 with the bit width of C and the address length of R, and store the second reorganization sequence C2 in the data storage unit; wherein, C is the length of the intra-row transformation sequence L1, and R is the length of the inter-row transformation sequence L2;
it is characterized by also comprising:
the data storage unit is used for receiving externally input coded data and outputting a coding result; the coding device is also used for storing the coding data, the recombination sequence and the coding result;
a puncturing generation unit for generating a puncturing sequence D1 of the first check sequence and a puncturing sequence D2 of the second check sequence according to a puncturing rule, or receiving an externally configured puncturing sequence D1 and a puncturing sequence D2;
and the coding unit is used for calling the first recombination sequence C1 and the second recombination sequence C2 in the data storage unit and simultaneously coding, calling the puncture sequences D1 and D2 in the puncture generation unit respectively to control the generation of the first check sequence and the second check sequence in a one-to-one correspondence mode in the coding process, and storing the coding result in the data storage unit according to a bit arrangement rule.
2. The Turbo encoder of claim 1, wherein the intra-row transform sequence L1 is formed by R groups of sub-sequences of length C, the address of the sub-sequence representing the bit sequence in the row before transform, the data of the sub-sequence representing the bit sequence after intra-row transform, and the sub-sequence being formed by data between 0 and C-1; the address of the interline transformation sequence L2 represents the interline order before transformation, and the data of the interline transformation sequence L2 represents the interline order after the interline transformation, and is composed of data from 0 to R-1; wherein the length C of the sub-sequence of the intra-row transform sequence L1 and the length R of the inter-row transform sequence L2 are set by the coding length and the interleaving rule adopted by the coding.
3. The fast configurable Turbo encoder according to claim 2, wherein the output memory addresses of the first reassembly sequence C1 are in the order of 0 to R-1; the second recombination sequence C2 performs bit sequence adjustment in the corresponding rows according to the intra-row conversion sequence L1 sub-sequence, and outputs the storage addresses in the order of the inter-row conversion sequence L2.
4. The Turbo encoder of claim 1, wherein the addresses of the puncturing sequences D1 and D2 respectively represent the puncturing sequence in the first check sequence and the second check sequence in a one-to-one correspondence manner, the data of the puncturing sequences D1 and D2 respectively represent the puncturing positions in the first check sequence and the second check sequence in a one-to-one correspondence manner, and the lengths of the puncturing sequences D1 and D2 are set by the coding length and the puncturing rule.
5. The Turbo encoder of claim 1, wherein the encoding unit comprises an RSC encoder, the encoding process of the RSC encoder is controlled by a set of state machines, and the RSC encoding generator polynomial is externally configured or set by the encoder.
6. A method of encoding, comprising the steps of:
(1) configuring parameters of an interleaving generation unit, a puncturing generation unit and an encoding unit, and storing encoded data into a data storage unit;
(2) starting an interleaving generation unit and a puncturing generation unit, and respectively generating an intra-row transformation sequence L1, an inter-row transformation sequence L2, a puncturing sequence D1 and a puncturing sequence D2;
(3) starting a data reorganization unit, calling the encoded data in the data storage unit and an intra-row transformation sequence L1 and an inter-row transformation sequence L2 in an interleaving generation unit, generating a first reorganization sequence C1 and a second reorganization sequence C2 according to the intra-row transformation sequence L1 and the inter-row transformation sequence L2, and storing the first reorganization sequence C1 and the second reorganization sequence C2 in the data storage unit;
(4) starting an encoding unit, calling a first recombination sequence C1 and a second recombination sequence C2 in a data storage unit, encoding the first recombination sequence C1 and the second recombination sequence C2, calling a puncturing sequence D1 and a puncturing sequence D2 in a puncturing generation unit respectively to control the generation of a first check sequence and a second check sequence in a one-to-one correspondence mode in the encoding process, and obtaining an encoding result and storing the encoding result in the data storage unit;
(5) and the data storage unit outputs the coding result.
7. An encoding method according to claim 6, wherein in step (2), the in-line transition sequence L1 is composed of R group C length sub-sequences, the address of the sub-sequence represents the in-line bit sequence before transition, the data of the sub-sequence represents the bit sequence after transition in the line, and is composed of data between 0 and C-1; the address of the inter-line transition sequence L2 represents the inter-line sequence before transition, and the data of L2 represents the inter-line sequence after the inter-line transition, and is composed of data from 0 to R-1; wherein the length C of the L1 subsequence and the length R of the L2 subsequence are determined by the coding length and the interleaving rule adopted by the coding.
8. The encoding method according to claim 7, wherein the step (3) specifically comprises:
starting a data reorganization unit, calling the coded data in the data storage unit, performing bit reorganization on the coded data to reorganize the coded data into a first reorganization sequence C1 with the bit width of C and the address length of R, and storing the first reorganization sequence C1 into the data storage unit according to the sequence from 0 to R-1; calling an intra-row conversion sequence L1 and an inter-row conversion sequence L2 in an interleaving generation unit, firstly, adjusting the bit sequence of a first recombination sequence C1 in a corresponding row according to a sub-sequence of the intra-row conversion sequence L1, recombining the first recombination sequence into a second recombination sequence C2 with the bit width of C and the address length of R, and storing the second recombination sequence C2 in a data storage unit according to the sequence of the inter-row conversion sequence L2; where C is the length of the intra-line transform sequence L1 and R is the length of the inter-line transform sequence L2.
9. The encoding method as claimed in claim 6, wherein the addresses of the puncturing sequences D1 and D2 in step (2) represent the puncturing order in the first check sequence and the second check sequence, respectively, in a one-to-one correspondence, the data of the puncturing sequences D1 and D2 represent the puncturing positions in the first check sequence and the second check sequence, respectively, in a one-to-one correspondence, and the lengths of the puncturing sequences D1 and D2 are determined by the encoding length and the puncturing rule.
10. The encoding method according to claim 6, wherein the first recombined sequence C1 and the second recombined sequence C2 are encoded by the RSC encoder in step (4), the encoding process of the RSC encoder is controlled by a set of state machines, and the RSC encoding generator polynomial is externally configured or set by the encoder.
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| EP0986181A2 (en) * | 1998-09-10 | 2000-03-15 | Nds Limited | Method and apparatus for generating punctured pragmatic turbo codes |
| CN1381095A (en) * | 1998-12-10 | 2002-11-20 | 诺泰网络有限公司 | Efficient implementation of proposed TURBO code interleavers for third generation code division multiple access |
| CN101083512A (en) * | 2006-06-02 | 2007-12-05 | 中兴通讯股份有限公司 | Dual-binary system tailbaiting Turbo code coding method and apparatus |
| CN102868478A (en) * | 2011-07-07 | 2013-01-09 | 中国科学院研究生院 | Method for designing Turbo code puncturing device for joint channel safety codes |
| CN106452672A (en) * | 2016-09-28 | 2017-02-22 | 郑州大学西亚斯国际学院 | Puncturing scheme designing method for Turbo codes of strong unequal error protection |
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2017
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|---|---|---|---|---|
| EP0986181A2 (en) * | 1998-09-10 | 2000-03-15 | Nds Limited | Method and apparatus for generating punctured pragmatic turbo codes |
| CN1381095A (en) * | 1998-12-10 | 2002-11-20 | 诺泰网络有限公司 | Efficient implementation of proposed TURBO code interleavers for third generation code division multiple access |
| CN101083512A (en) * | 2006-06-02 | 2007-12-05 | 中兴通讯股份有限公司 | Dual-binary system tailbaiting Turbo code coding method and apparatus |
| CN102868478A (en) * | 2011-07-07 | 2013-01-09 | 中国科学院研究生院 | Method for designing Turbo code puncturing device for joint channel safety codes |
| CN106452672A (en) * | 2016-09-28 | 2017-02-22 | 郑州大学西亚斯国际学院 | Puncturing scheme designing method for Turbo codes of strong unequal error protection |
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