CN107331666A - Split-gate flash memory and the method for avoiding its programming interference from failing - Google Patents
Split-gate flash memory and the method for avoiding its programming interference from failing Download PDFInfo
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- CN107331666A CN107331666A CN201710543546.5A CN201710543546A CN107331666A CN 107331666 A CN107331666 A CN 107331666A CN 201710543546 A CN201710543546 A CN 201710543546A CN 107331666 A CN107331666 A CN 107331666A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
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Abstract
The invention provides a kind of Split-gate flash memory and the method for avoiding its programming interference from failing, including：Tube core is provided, the tube core includes substrate, the tunnel oxide being formed on the substrate；In tunnel oxide layer surface formation word line layer, the thickness H of the word line layer0=H1+ Δ H, wherein, H1The word line layer thickness formed the need for for process set, Δ H is the wordline layer thickness H measured during process monitoring is tested2With actual wordline layer thickness H3Difference.Split-gate flash memory provided by the present invention and the method for avoiding its programming interference from failing, the difference gone out by Data analysis in process monitoring test between the word line layer thickness and actual word line layer thickness that measure, word line layer is allowed in formation, compensate this difference, the thickness of word line layer is set to reach required requirement, so as to avoid Split-gate flash memory because word line layer thickness is excessively thin and programming interference failure occur.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly to one kind avoids Split-gate flash memory and avoids its programming string
The method for disturbing failure.
Background technology
The problem of random access memory (such as DRAM and SRAM) deposits loss of data after a power failure in use, in order to gram
The problem is taken, people have designed and developed multigroup flash memory, the flash memory based on point grid concept is due to less
Unit size and good service behaviour are as more general flash memory.
Flash memory includes two kinds of basic structures：Gate stack (stackgate) and point grid (splitgate) device.
Wherein, gate device is divided to be formed in the side of floating boom as the wordline for wiping grid, wordline alternatively grid, on wiping/writing performance,
Gate device is divided effectively to avoid the erasure effect excessively of gatestack device, circuit design is relatively easy.And grid dividing structure utilizes source
End thermoelectron injection is programmed, with higher programming efficiency, thus be widely used in all kinds of such as smart cards, SIM card,
In the electronic products such as microcontroller, mobile phone.
In Split-gate flash memory, the thickness and width of word line polysilicon layer affects the anti-interference of grid flash memory
Can, and the width of word line polysilicon layer and its thickness are closely related.If the thickness of word line polysilicon layer is excessively thin, it can cause point
There is row break-through crosstalk failure (column punch-throughdisturb) in gate flash memory, and in production procedure, word
The thickness of line polysilicon layer is measured according in PCM (test of ProcessControlMonitortest process monitorings)
The thickness of word line polysilicon layer shows, and due to the influence of load effect, in the thickness of the PCM word line polysilicon layers measured
Degree is bigger than the thickness of the word line polysilicon layer in actual flash cell area, such as the wordline in some product requirement flash cell areas is more
The thickness of crystal silicon layer is 1500 angstroms, if only 1500 angstroms of the result measured based on PCM, then actual flash cell area wordline is more
The thickness of crystal silicon layer is less than 1500 angstroms, and this thickness for resulting in the actual word line polysilicon layer of product is less than required thickness,
The thinner thickness of word line polysilicon layer, causes Split-gate flash memory row break-through crosstalk failure phenomenon occur.
So needing a kind of new technique badly to solve the above problems.
The content of the invention
It is existing to solve it is an object of the invention to provide a kind of method for avoiding Split-gate flash memory programming interference from failing
The thickness of some word line polysilicon layers is excessively thin and causes Split-gate flash memory the problem of row break-through crosstalk is failed occur.
In order to solve the above technical problems, the present invention provides a kind of side for avoiding Split-gate flash memory programming interference from failing
Method, including：
Tube core is provided, the tube core includes substrate, the tunnel oxide being formed on the substrate；
In tunnel oxide layer surface formation word line layer, the thickness H of the word line layer0=H1+ Δ H, wherein, H1For system
The word line layer thickness that journey is formed the need for setting, Δ H is the wordline layer thickness H measured during process monitoring is tested2With reality
Wordline layer thickness H3Difference.
Optionally, the tube core is stored with n binary digit, the Δ H and the n positive correlations.
Optionally, it is characterised in that in n≤2700, the Δ H and n meets formula：Δ H=0.0421n-
43.177。
Optionally, it is characterised in that in n>When 2700, Δ H is 75 angstroms.
Optionally, the scope of the Δ H is 0-75 angstroms.
The corresponding present invention also provides a kind of Split-gate flash memory, including：Substrate；It is formed at the tunnelling on the substrate
Oxide layer；It is formed at the word line layer of the tunnel oxide layer surface；The thickness H of the word line layer0=H1+ Δ H, wherein, H1For system
The word line layer thickness that journey is formed the need for setting, Δ H is the wordline layer thickness H measured during process monitoring is tested2With reality
Wordline layer thickness H3Difference.
Optionally, the substrate is provided with source line layer and floating gate oxide layers, and the floating gate oxide layers surface deposition has floating boom
Polysilicon layer, is provided with the first side wall, the source line layer and the floating gate oxide layers and floating boom between the source line layer and word line layer
The second side wall is provided between polysilicon layer.
Optionally, the floating gate polysilicon layer is provided with floating boom tip, and the floating boom is sophisticated with the tunnel oxide phase
Contact.
Split-gate flash memory provided by the present invention and the method for avoiding its programming interference from failing, pass through data analysis point
The difference between the word line layer thickness measured in process monitoring test and actual word line layer thickness is separated out, word line layer is allowed in formation
When, this difference is compensated, the thickness of word line layer is reached required requirement, so as to avoid Split-gate flash memory due to wordline
The thickness of layer is excessively thin to there is programming interference failure.
Brief description of the drawings
Fig. 1 is a kind of profile of gate-division type flash memory device；
Fig. 2 is a kind of structural representation of wafer；
Fig. 3 is the matched curve figure of relation between Δ H and n in one embodiment of the invention.
Label in figure：
10- substrates；111- drain regions；112- source regions；12- sources line polysilicon layer；13- floating gate oxide layers；14- floating gate polysilicons
Layer；141- floating booms tip；The side walls of 151- first；The side walls of 152- second；16- tunnel oxides；17- word line layers；18- wordline side
Wall.
Embodiment
Below in conjunction with the drawings and specific embodiments are to Split-gate flash memory proposed by the present invention and avoid its programming interference
The method of failure is described in further detail.According to following explanation and claims, advantages and features of the invention will be more clear
Chu.It should be noted that, accompanying drawing is using very simplified form and uses non-accurately ratio, only to conveniently, lucidly
Aid in illustrating the purpose of the embodiment of the present invention.
There is the problem of thickness is excessively thin in the floating gate polysilicon layer of existing Split-gate flash memory, present inventor is led to
Long-term research and experiment is crossed, a kind of new method has been invented, has solved above mentioned problem.
The present invention provides a kind of method for avoiding Split-gate flash memory programming interference from failing, including：
S1：Tube core is provided, the tube core includes substrate, the tunnel oxide being formed on the substrate；
S2：In tunnel oxide layer surface formation word line layer, the thickness H of the word line layer0=H1+ Δ H, wherein, H1For
The word line layer thickness formed the need for process set, Δ H is the wordline layer thickness H measured during process monitoring is tested2With reality
Wordline layer thickness H3Difference.
It refer to Fig. 2, Fig. 2 is that a square is to represent a tube core in a crystal circle structure schematic diagram, figure, and the tube core is deposited
Contain n binary digit.
The structure of the tube core is as shown in figure 1, including substrate 10, be formed at source line layer 12, floating boom oxygen on the substrate
Change layer 13 and tunnel oxide 16, the surface of tunnel oxide 16 deposition has word line layer 17.The source line layer 12 is located at source region
On 112, the surface of floating gate oxide layers 13 deposition has floating gate polysilicon layer 14, and the floating gate polysilicon layer is provided with floating boom point
End 141, the floating boom is sophisticated to be in contact with the tunnel oxide 16.The source line layer 12 is more with floating gate oxide layers 13 and floating boom
Between crystal silicon layer 14 be provided with the second side wall 152, second side wall 152 by source line layer 12 with floating gate oxide layers 13 and floating boom polycrystalline
Silicon layer 14 is kept apart.The side of the word line layer 17 has the first side wall 151, and opposite side has a wordline side wall 18, and described the
One side wall 151 keeps apart source line layer 12 and word line layer 17.
Whether conformed with the regulations requirement for the deposit thickness of word line layer 17, inventor thinks can be in process monitoring test volume
The thickness of word line layer is surveyed, judges whether word line layer meets the requirements with this.But inventor is further to be sent out after data analysis
Wordline layer thickness H that is existing, being measured in process monitoring test2Than the thickness H of actual word line layer3Greatly, between the two in the presence of certain
Difference, refer to table 1：
Table 1：
Pass through table 1, Δ the H (=H of different product (PartID)2-H3) value difference, the number of bits n stored with it
Positive correlation, Fig. 3 is the matched curve figure of relation between Δ H and n, and abscissa represents n quantity (k), and ordinate represents Δ H valueAs shown in Figure 3, in n≤2700, the Δ H becomes big as n change is big, meets relational expression：Δ H=
0.0421n-43.177, works as n>2700, Δ H values tend to saturation, reach 75 angstroms, the scope of the Δ H is 0-75 angstroms.
By above-mentioned analysis, the wordline layer thickness H measured in process monitoring test2Sudden strain of a muscle can not accurately be corresponded to
The actual (real) thickness of word line layer in memory cell area, i.e., the word line layer measured in actual word line layer thickness ratio process monitoring test
Thickness is small, there is difference DELTA H, in order to accurately obtain required word line layer thickness, when depositing word line layer, it is necessary to compensate
This partial difference, i.e., the word line layer thickness of required deposition is H0=H1+ Δ H, wherein H1Deposition is needed for the word line layer of process set
Thickness.
For example flash cell area needsWord line layer when, for different products, the thickness H deposited0Can be with
With reference to table 2：
Table 2：
It should be noted that H now0It is worth the word line layer thickness measured in testing for process monitoring, i.e. process monitoring to survey
The word line layer thickness measured in examination is more than required word line layer thickness, only in this way could really obtain the wordline needed for us
Thickness degree.
In the present embodiment, the material of the word line layer is polysilicon, in other embodiments, the material of the word line layer
Can also be the polysilicon of doping, using chemical vapor deposition method, physical gas-phase deposition or atom layer deposition process
Form the word line layer.
Accordingly, the present invention also provides a kind of Split-gate flash memory, including substrate, the tunnelling that is formed on the substrate
Oxide layer；It is formed at the word line layer of the tunnel oxide layer surface；The thickness H of the word line layer0=H1+ Δ H, wherein, H1For system
The word line layer thickness that journey is deposited the need for setting, Δ H is the wordline layer thickness H measured during process monitoring is tested2With reality
Wordline layer thickness H3Difference.The structure of the Split-gate flash memory is consistent with the structure in above-described embodiment, here no longer
Carry out excessive elaboration.
In summary, Split-gate flash memory provided by the present invention and the method for avoiding its programming interference from failing, pass through
Data analysis goes out the difference between the word line layer thickness that measures and actual word line layer thickness in process monitoring test, allows wordline
Layer compensates this difference when being formed, and the thickness of word line layer is reached required requirement, so as to avoid Split-gate flash memory
There is programming interference failure because the thickness of word line layer is excessively thin.
Foregoing description is only the description to present pre-ferred embodiments, not to any restriction of the scope of the invention, this hair
Any change, modification that the those of ordinary skill in bright field does according to the disclosure above content, belong to the protection of claims
Scope.
Claims (8)
1. a kind of method for avoiding Split-gate flash memory programming interference from failing, including：
Tube core is provided, the tube core includes substrate, the tunnel oxide being formed on the substrate；
In tunnel oxide layer surface formation word line layer, the thickness H of the word line layer0=H1+ Δ H, wherein, H1Set for processing procedure
The word line layer thickness formed the need for fixed, Δ H is the wordline layer thickness H measured during process monitoring is tested2With actual wordline
Layer thickness H3Difference.
2. the method as claimed in claim 1 for avoiding Split-gate flash memory programming interference from failing, it is characterised in that described point
Gate flash memory is stored with n binary digit, the Δ H and the n positive correlations.
3. the as claimed in claim 2 method for avoiding Split-gate flash memory programming interference from failing, it is characterised in that n≤
When 2700, the Δ H and n meets formula：Δ H=0.0421n-43.177.
4. the method as claimed in claim 2 for avoiding Split-gate flash memory programming interference from failing, it is characterised in that in n>
When 2700, Δ H is 75 angstroms.
5. the method as claimed in claim 1 for avoiding Split-gate flash memory programming interference from failing, it is characterised in that the Δ
H scope is 0-75 angstroms.
6. a kind of Split-gate flash memory, it is characterised in that including：Substrate；It is formed at the tunnel oxide on the substrate；Shape
The word line layer of tunnel oxide layer surface described in Cheng Yu；The thickness H of the word line layer0=H1+ Δ H, wherein, H1For process set
The word line layer thickness to be formed is needed, Δ H is the wordline layer thickness H measured during process monitoring is tested2With actual wordline thickness
Spend H3Difference.
7. Split-gate flash memory as claimed in claim 6, it is characterised in that the substrate is provided with source line layer and floating boom oxygen
Change layer, the floating gate oxide layers surface deposition has floating gate polysilicon layer, the first side wall is provided between the source line layer and word line layer,
The second side wall is provided between the source line layer and the floating gate oxide layers and floating gate polysilicon layer.
8. Split-gate flash memory as claimed in claim 7, it is characterised in that the floating gate polysilicon layer is provided with floating boom point
End, the floating boom is sophisticated to be in contact with the tunnel oxide.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710543546.5A CN107331666A (en) | 2017-07-05 | 2017-07-05 | Split-gate flash memory and the method for avoiding its programming interference from failing |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710543546.5A CN107331666A (en) | 2017-07-05 | 2017-07-05 | Split-gate flash memory and the method for avoiding its programming interference from failing |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111599814A (en) * | 2020-06-11 | 2020-08-28 | 上海华虹宏力半导体制造有限公司 | Split-gate flash memory and forming method thereof |
| CN112750784A (en) * | 2021-01-22 | 2021-05-04 | 上海华虹宏力半导体制造有限公司 | Process manufacturing method for improving crosstalk failure of split-gate flash memory |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102347281A (en) * | 2011-10-28 | 2012-02-08 | 上海宏力半导体制造有限公司 | Split-gate flash memory unit and forming method thereof |
| CN106252252A (en) * | 2016-08-30 | 2016-12-21 | 上海华力微电子有限公司 | The film thickness forecast model of conformal deposit is set up and application process |
-
2017
- 2017-07-05 CN CN201710543546.5A patent/CN107331666A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102347281A (en) * | 2011-10-28 | 2012-02-08 | 上海宏力半导体制造有限公司 | Split-gate flash memory unit and forming method thereof |
| CN106252252A (en) * | 2016-08-30 | 2016-12-21 | 上海华力微电子有限公司 | The film thickness forecast model of conformal deposit is set up and application process |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111599814A (en) * | 2020-06-11 | 2020-08-28 | 上海华虹宏力半导体制造有限公司 | Split-gate flash memory and forming method thereof |
| CN111599814B (en) * | 2020-06-11 | 2023-04-18 | 上海华虹宏力半导体制造有限公司 | Split-gate flash memory and forming method thereof |
| CN112750784A (en) * | 2021-01-22 | 2021-05-04 | 上海华虹宏力半导体制造有限公司 | Process manufacturing method for improving crosstalk failure of split-gate flash memory |
| CN112750784B (en) * | 2021-01-22 | 2024-03-12 | 上海华虹宏力半导体制造有限公司 | Process manufacturing method for improving crosstalk failure of split gate flash memory |
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Application publication date: 20171107 |