CN107331629A - The wafer scale preparation method and bio-identification chip of a kind of bio-identification chip - Google Patents
The wafer scale preparation method and bio-identification chip of a kind of bio-identification chip Download PDFInfo
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- CN107331629A CN107331629A CN201710695720.8A CN201710695720A CN107331629A CN 107331629 A CN107331629 A CN 107331629A CN 201710695720 A CN201710695720 A CN 201710695720A CN 107331629 A CN107331629 A CN 107331629A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 25
- 238000003466 welding Methods 0.000 claims abstract description 102
- 239000000758 substrate Substances 0.000 claims abstract description 99
- 239000000463 material Substances 0.000 claims abstract description 33
- 238000009413 insulation Methods 0.000 claims abstract description 30
- 238000000034 method Methods 0.000 claims abstract description 27
- 230000002093 peripheral effect Effects 0.000 claims abstract description 16
- 238000001259 photo etching Methods 0.000 claims description 11
- 229910000679 solder Inorganic materials 0.000 claims description 10
- 238000001459 lithography Methods 0.000 claims description 8
- 230000006698 induction Effects 0.000 claims description 5
- 238000007650 screen-printing Methods 0.000 claims description 5
- 238000007639 printing Methods 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 2
- 230000000704 physical effect Effects 0.000 abstract description 6
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 238000005516 engineering process Methods 0.000 description 8
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 239000004744 fabric Substances 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 238000001723 curing Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000001548 drop coating Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000006552 photochemical reaction Methods 0.000 description 1
- 230000001766 physiological effect Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/27—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
- H01L2224/26122—Auxiliary members for layer connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
- H01L2224/26145—Flow barriers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
- H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/276—Manufacturing methods by patterning a pre-deposited material
- H01L2224/2761—Physical or chemical etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
- H01L2224/301—Disposition
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Abstract
The embodiment of the invention discloses a kind of wafer scale preparation method of bio-identification chip and bio-identification chip, wherein, the wafer scale preparation method of the bio-identification chip includes：Dielectric insulation layer is prepared at the underlay substrate back side of chip, is prepared on the dielectric insulation layer and reroutes layer and pad；Anti-welding layer pattern is formed on the surface for be formed with pad, wherein, the anti-welding layer pattern exposes the pad, and including protection zone pattern, the protection zone pattern is the pattern of the pad peripheral setting range；Baking-curing is carried out to the anti-welding layer pattern.Technical scheme provided in an embodiment of the present invention, improves chip fabrication process, improves because the thermal strain physical property of anti-welding layer material causes chip internal stress big, the problem of chip warpage is serious improves module group assembling yield and properties of product.
Description
Technical field
The present embodiments relate to technical field of semiconductor preparation, more particularly to a kind of wafer scale system of bio-identification chip
Preparation Method and bio-identification chip.
Background technology
Current biological identification technology mainly passes through the high-techs such as optics, acoustics, biology sensor and biostatistics principle
Skill technological means is intimately associated, and personal identification is carried out using the intrinsic physiological property of human body (if biological, face is as, iris etc.)
Identification.And it is biological there is unchangeable shape, the feature such as uniqueness and convenience will can be collected by biological recognition system
It is biological handled after fast and accurately carry out authentication, so its personal identification identification in use importance all the more dash forward
Go out.
Figure 1A -1C are a kind of structural representation of bio-identification chip in the prior art.As shown in figs. 1A-1 c, chip bag
Including has bond pads 12 on underlay substrate 11, underlay substrate 11 and offers thereunder under through hole, the underlay substrate 11
Surface is formed with dielectric insulation layer 13, is formed on dielectric insulation layer 13 and reroutes layer 14, is additionally provided with layer 14 is rerouted
Pad 16, and anti-welding layer pattern 15 is formed on the rewiring layer 14 for forming pad 16, and expose pad 16.Specifically prepared
Cheng Zhong：The lower surface of counterweight wiring layer 14 coats anti-welding layer material, the full whole back side of lid, by photoetching technique only by welding
Pad tin ball bottom metal layers are exposed.
Existing chip is by the anti-welding layer material of backside coating of whole bio-identification chip, due to the heat of anti-welding layer material
Physical property is strained, is caused during being heating and curing, welding resisting layer is heated to be deformed upon, and thus causes to be applied on chip
Pulling force increase so that chip internal stress is big so that the warping phenomenon of chip is serious after preparation, have impact on module group assembling yield
And properties of product.
The content of the invention
The embodiment of the present invention provides the wafer scale preparation method and bio-identification chip of a kind of bio-identification chip, to improve
Preparation process, so as to improve the warping phenomenon caused by chip internal stress.
In a first aspect, the embodiments of the invention provide a kind of wafer scale preparation method of bio-identification chip, this method bag
Include：
Dielectric insulation layer is prepared at the underlay substrate back side of chip, is prepared on the dielectric insulation layer and reroutes layer and weldering
Disk；
Anti-welding layer pattern is formed on the surface for be formed with pad, wherein, the anti-welding layer pattern exposes the pad,
And including protection zone pattern, the protection zone pattern is the pattern of the pad peripheral setting range；
Baking-curing is carried out to the anti-welding layer pattern.
Second aspect, the embodiment of the present invention additionally provides a kind of bio-identification chip, and the bio-identification chip includes：
Underlay substrate；
Dielectric insulation layer, is arranged on the back side of the underlay substrate；
Layer and pad are rerouted, is arranged on the dielectric insulation layer；
Anti-welding layer pattern, including protection zone pattern, are partially covered on the rewiring layer, and expose the weldering
Disk, wherein, the protection zone pattern is the pattern of the pad peripheral setting range.
The embodiment of the present invention forms anti-by improving the preparation process of bio-identification chip on the surface for be formed with pad
Layer pattern, the anti-welding layer pattern exposes the pad, while protecting the annular welding resisting layer of pad peripheral setting, can improve
Traditional die preparation technology, removes the anti-welding layer material of large area on chip substrate substrate, improves due to the heat of anti-welding layer material
Physical property is strained, causes chip internal stress big, chip internal stress causes the problem of chip warpage is serious, module group assembling is improved
Yield and properties of product.
Brief description of the drawings
Figure 1A is a kind of profile for bio-identification chip that prior art is provided；
Figure 1B is a kind of upward view for bio-identification chip that prior art is provided；
Fig. 1 C are a kind of top views for bio-identification chip that prior art is provided；
Fig. 2 is a kind of flow signal of the wafer scale preparation method for bio-identification chip that the embodiment of the present invention one is provided
Figure；
Fig. 3 is a kind of flow signal of the wafer scale preparation method for bio-identification chip that the embodiment of the present invention two is provided
Figure；
Fig. 4 is a kind of flow signal of the wafer scale preparation method for bio-identification chip that the embodiment of the present invention three is provided
Figure；
Fig. 5 A are a kind of profiles for bio-identification chip that the embodiment of the present invention four is provided；
Fig. 5 B are a kind of upward views for bio-identification chip that the embodiment of the present invention four is provided；
Fig. 5 C are a kind of top views for bio-identification chip that the embodiment of the present invention four is provided.
Embodiment
The present invention is described in further detail with reference to the accompanying drawings and examples.It is understood that this place is retouched
The specific embodiment stated is used only for explaining the present invention, rather than limitation of the invention.It also should be noted that, in order to just
Part related to the present invention rather than entire infrastructure are illustrate only in description, accompanying drawing.
Embodiment one
Fig. 2 is a kind of flow signal of the wafer scale preparation method for bio-identification chip that the embodiment of the present invention one is provided
Figure.The present embodiment is applicable to the situation of bio-identification chip preparation, and Fig. 5 A-5C are the preparation-obtained lifes of the embodiment of the present invention
The structural representation of thing identification chip, a kind of wafer scale preparation method bag of bio-identification chip provided in an embodiment of the present invention
Include：
Step 110, at the underlay substrate back side of chip dielectric insulation layer is prepared, weight cloth is prepared on the dielectric insulation layer
Line layer and pad.
Wherein, as shown in figures 5a-5c, dielectric insulation layer 13 is located at the lower surface of chip substrate substrate 11, reroutes layer 14
It is located at pad 16 on the dielectric insulation layer 13.The chip substrate substrate 11 of such as offer can be silicon chip, in chip substrate
Prepared by the lower surface of substrate 11 have nonconducting dielectric insulation layer 13, wherein, dielectric insulation layer be used for keeping circuit and each layer it
Between insulating properties.And metal rewiring and pad 16 are distributed with described dielectric insulation layer 13, obtain rerouting the He of layer 14
The structure of pad 16.Wherein, one end of pad 16 is connected by rerouting layer 14 with the bond pads 12 of chip surface, bond pads
12 are connected with the conducting wire 17 of induction region, and the other end is welded with outside.The pad of such as connection can be scolding tin weldering
Disk 16.
Step 120, anti-welding layer pattern is formed on the surface for be formed with pad, wherein, the anti-welding layer pattern exposes
The pad, and including protection zone pattern, the protection zone pattern is the pattern of the pad peripheral setting range.
Wherein, as shown in Figure 5 B, anti-welding layer pattern 15, institute are provided with the chip substrate substrate 11 for being formed with pad 16
The anti-welding layer pattern 15 stated includes the pad 16 of exposure and includes the pattern of the pad peripheral setting range.For example：Protection zone
Region pattern can be formulated according to pad size and shape.
Step 130, baking-curing is carried out to the anti-welding layer pattern.
Wherein, as shown in Figure 5 B, the chip substrate substrate 11 for setting anti-welding layer pattern 15 can be dried under the high temperature conditions
Roasting solidification so that anti-welding layer material is shaped in chip back in patterned mode.
Above-mentioned preparation method be wafer wafer level processing technology, the technical scheme that the embodiment of the present invention is provided, by
It is formed with the surface of pad and forms anti-welding layer pattern, wherein, the anti-welding layer pattern exposes the pad, and including protection
Zone map, the protection zone pattern is the pattern of the pad peripheral setting range, is removed many on chip substrate substrate
Remaining anti-welding layer material, improves traditional die preparation technology, improves the thermal strain physical property in itself due to anti-welding layer material,
Cause the internal stress of chip to become big, cause the problem of chip warpage is serious, reduce the angularity of bio-identification chip, improve mould
Group assembling yield and properties of product.
On the basis of above-mentioned technical proposal, institute's protection zone pattern is preferably annular welding resisting layer, encloses and is located at the pad
Periphery.The shape of its middle ring can be circular, square and rectangle etc., be mainly determined by the shape of pad.And it is described
The diameter of ring is preferably greater than to be equal to 50 μm, less than or equal to 1000 μm.Specific ring diameter size is by chip substrate substrate 11
Actual size is determined, and it is partially covered in solder pad 16, is played stable scolding tin effect, is prevented scolding tin in welding process
In, moved along conducting wire.
On the basis of above-mentioned technical proposal, the beam worker before the underlay substrate back side of chip prepares dielectric insulation layer
Work preferably can be：The underlay substrate is ground thinned；Through hole etching is carried out to the underlay substrate.
Wherein, before the back side of underlay substrate 11 of chip prepares dielectric insulation layer 13, to being provided with bond pads 12
It is to remove unnecessary underlay substrate thickness that underlay substrate 11, which is ground and is thinned,；Carrying out via etch to underlay substrate 11 is
It is connected for the ease of rerouting through through hole with the bond pads 12 of upper surface of base plate.
It is preferred to the later stage work after the anti-welding layer pattern progress baking-curing on the basis of above-mentioned technical proposal
Can be：The underlay substrate is cut, multiple bio-identification chips are obtained.
Wherein, the anti-welding layer pattern 15 is carried out after baking-curing, cutting process can be carried out to underlay substrate 11,
Obtained multiple bio-identification chips, are convenient for chip package.
Embodiment two
Fig. 3 is a kind of flow signal of the wafer scale preparation method for bio-identification chip that the embodiment of the present invention two is provided
Figure, Fig. 5 A-5C are the structural representations of the preparation-obtained bio-identification chip of the embodiment of the present invention.The present embodiment is in above-mentioned reality
Apply and optimize on the basis of example one, be specifically the specific method bag that anti-welding layer pattern is formed on the surface for be formed with pad
Include：Anti-welding layer material is coated on the surface for be formed with pad, welding resisting layer is formed；The underlay substrate for forming welding resisting layer is entered
Row precuring is handled；The welding resisting layer of the underlay substrate is exposed using the lithography mask version of predetermined pattern, and shown
Shadow processing, the pad, and reservation protection zone map are exposed to etch away the welding resisting layer.Accordingly, the present embodiment
Method includes：
Step 210, at the underlay substrate back side of chip dielectric insulation layer is prepared, weight cloth is prepared on the dielectric insulation layer
Line layer and pad.
Step 220, coat anti-welding layer material on the surface for be formed with pad, form welding resisting layer.
Wherein, as shown in figures 5a-5c, layer 14 will be rerouted and is connected with pad 16, be coated with the surface of pad 16 anti-
Welding layer material, forms welding resisting layer.Wherein, the anti-welding layer material of coating can be by spin coating spraying, narrow slit coating or drop coating in core
On piece underlay substrate 16.
Step 230, the underlay substrate progress precuring processing that welding resisting layer will be formed.
Wherein, as shown in figures 5a-5c, can be under relatively low baking temperature to forming the chip substrate substrate 11 of welding resisting layer
Precuring processing is carried out, stereotyped structure is obtained.
Step 240, using the lithography mask version of predetermined pattern the welding resisting layer of the underlay substrate is exposed, and carried out
Development treatment, the pad, and reservation protection zone map are exposed to etch away the welding resisting layer.
Wherein, photoetching technique refers to that ultraviolet light is irradiated to the substrate surface with anti-welding layer material by lithography mask version,
The anti-welding layer material of exposure area is caused to occur photochemical reaction；Exposure area or unexposed is removed by developing technique dissolving again
The anti-welding layer material in region, makes the figure on mask plate be copied on welding resisting layer；Lithographic technique is finally utilized by pattern transfer
Onto substrate.
Wherein, as shown in figures 5a-5c, there is pad 16 to welding resisting layer exposure resulting after photoetching technique processing, and retain
Protection zone pattern, wherein obtaining needing the region retained to be welding resisting layer pattern 15.Also, photoresist (anti-welding layer material)
Can be positive photoetching rubber or negative photoresist.
Step 250, baking-curing is carried out to the anti-welding layer pattern.
The technical scheme that the embodiment of the present invention is provided, is carried out by using the lithography mask version of predetermined pattern to welding resisting layer
Exposure and development treatment, etches away anti-welding layer material unnecessary on welding resisting layer, and exposure pad and pad peripheral protection zone
Anti-welding layer pattern, is improved because anti-welding layer material has thermal strain physical property in itself, is caused the internal stress of chip to become big, is drawn
The problem of chip warpage is serious is played, the angularity of bio-identification chip is reduced, module group assembling yield and properties of product are improved.
Embodiment three
Fig. 4 is a kind of flow signal of the wafer scale preparation method for bio-identification chip that the embodiment of the present invention three is provided
Figure, Fig. 5 A-5C are the structural representations of the preparation-obtained bio-identification chip of the embodiment of the present invention.The present embodiment is in above-mentioned reality
Apply and optimize on the basis of example one, be specifically the specific method bag that anti-welding layer pattern is formed on the surface for be formed with pad
Include：The graphical silk screen being pre-designed is aligned with described chip substrate substrate；To the chip lining of wire mesh arrangement
Substrate solder-mask printing layer material, and the pattern of exposure pad and pad peripheral setting range, to form anti-welding layer pattern；By shape
The underlay substrate into anti-welding layer pattern carries out precuring processing.Accordingly, the method for the present embodiment includes：
Step 310, at the underlay substrate back side of chip dielectric insulation layer is prepared, weight cloth is prepared on the dielectric insulation layer
Line layer and pad.
Step 320, the graphical silk screen being pre-designed aligned with described chip substrate substrate.
Wherein, as shown in figures 5a-5c, it will be pre-designed and make patterned silk screen and described chip substrate substrate
11 are accurately aligned, for example, by the position of pad 16 and its area to be protected can be needed to be accurately positioned with silk screen,
To obtain exposed pad 16 and pad peripheral protection zone pattern.
Step 330, the chip substrate substrate solder-mask printing layer material to wire mesh arrangement, and exposure pad and pad week
The pattern of side setting range, to form anti-welding layer pattern.
Wherein, as shown in figures 5a-5c, anti-welding layer material, and exposure are printed with the chip substrate substrate 11 of wire mesh arrangement
There are pad 16 and the anti-welding layer pattern 15 of pad peripheral.For example by the extruding of scraper plate when screen printing technique refers to print, make to prevent
Solder paste ink is transferred on chip substrate substrate 11 by part mesh.Wherein, it is right in screen printing technique in the embodiment of the present invention
The non-lithography performance limitation of anti-solder ink material, can be with the anti-welding layer material of right and wrong lithography type.
Step 340, the underlay substrate progress precuring processing that anti-welding layer pattern will be formed.
Wherein, as shown in Figure 5A, to forming the chip substrate substrate 11 of anti-welding layer pattern 15 under relatively low baking temperature
Precuring is handled, the anti-welding layer pattern being fixed.
Step 350, baking-curing is carried out to the anti-welding layer pattern.
The technical scheme that the embodiment of the present invention is provided, by the technology that silk-screen printing is used on the underlay substrate of chip
Means, can directly obtain the anti-welding layer pattern of needs, it is not necessary to carry out the photoetching technique of traditional handicraft, process simplification,
Save production cost.The thermal strain physical property due to anti-welding layer material in itself is improved simultaneously, causes the internal stress of chip to become
Greatly, cause the problem of chip warpage is serious, reduce coverage rate of the anti-welding layer material in underlay substrate, so as to reduce biological knowledge
The chip warpage of other chip, improves module group assembling yield and properties of product.
Example IV
Fig. 5 A are a kind of profiles for bio-identification chip that the embodiment of the present invention four is provided, and Fig. 5 B are the embodiment of the present invention
A kind of upward view of the four bio-identification chips provided, Fig. 5 C are a kind of bio-identification chips that the embodiment of the present invention four is provided
Top view.
The embodiment of the present invention also provides a kind of bio-identification chip, and the bio-identification chip can be used any real in the present invention
The wafer scale preparation method for applying a kind of bio-identification chip of example offer is obtained, as shown in figures 5a-5c, the bio-identification chip bag
Include：
Underlay substrate 11, dielectric insulation layer 13, rewiring layer 14 and pad 16 and anti-welding layer pattern 15；Wherein, dielectric
Insulating barrier 13 is arranged on the back side of the underlay substrate 11；Reroute layer 14 and pad 16 is arranged on the dielectric insulation layer 13
On；Anti-welding layer pattern 15 includes protection zone pattern, is partially covered on the rewiring layer 14, and expose the pad
16, wherein, the protection zone pattern is the pattern of the pad peripheral setting range.
Specifically, board structure of the underlay substrate 11 for manufacture chip, usually silicon chip.
Wherein, chip includes bond pads 12 and the phase of conducting wire 17 of induction region on underlay substrate 11, underlay substrate
Connection, while offering the through hole by underlay substrate on chip substrate substrate 11, reroutes layer 14 and exists with bond pads 12
Conducting is connected with each other in the through hole of underlay substrate, the lower surface of the underlay substrate 11 is formed with dielectric insulation layer 13, and dielectric is exhausted
Edge layer 13 is used to keep the insulating properties between circuit and each layer.
Wherein, metal is provided with the chip substrate substrate 11 for setting dielectric insulation layer 13 to reroute, rerouting layer
Pad 16 is additionally provided with 14, and anti-welding layer pattern 15 is connected with the rewiring layer 14 for forming pad 16.Wherein, pad 16
One end can be connected by rerouting with the bond pads 12 of chip substrate substrate 11 conducting, bond pads 12 and substrate base
The conducting wire 17 of induction region is connected on plate, and the other end of pad 16 can be welded.
Wherein, anti-welding layer pattern 15 includes exposed pad 16 and protection zone pattern, and protection zone pattern is the weldering
The pattern of disk periphery setting range, main function is anti-welding.
Further, protection pattern described above is annular, and the annular diameter is more than or equal to 50 μm, is less than or waits
In 1000 μm.Annular welding resisting layer is mainly designed according to the shape of pad, and the size of its diameter can be according to chip substrate substrate
11 actual size is selected with the size of pad 16, so as to prepare the chip of a variety of different demands.
Further, in order to adapt to the package requirements of present electronic equipment, the selection of anti-welding layer material can be for can photoetching
Anti-solder ink, is made of photoetching process.Photoetching anti-solder ink is exposed and developing technique, obtained in photoetching process is carried out
To the anti-welding Rotating fields specifically needed.
Further, in order to optimize the preparation technology to bio-identification chip, the selection of anti-welding layer material can be unglazed
Carve the anti-solder ink of performance limitation, by screen printing technique, the anti-welding Rotating fields specifically needed.
Preferably, being provided with bond pads 12 and the conduction of induction region in the front of the chip substrate substrate 11 of offer
Circuit 17, the back side of the underlay substrate 11 is provided with solder pad 16.
Bio-identification chip provided in an embodiment of the present invention can be fingerprint recognition chip, compared with prior art for,
A kind of bio-identification chip provided in an embodiment of the present invention, reduces the coverage rate of anti-welding layer material on chip, can reach drop
Low chip internal stress, improves chip warping phenomenon, improves module group assembling yield and properties of product.
Note, above are only presently preferred embodiments of the present invention and institute's application technology principle.It will be appreciated by those skilled in the art that
The invention is not restricted to specific embodiment described here, can carry out for a person skilled in the art it is various it is obvious change,
Readjust and substitute without departing from protection scope of the present invention.Therefore, although the present invention is carried out by above example
It is described in further detail, but the present invention is not limited only to above example, without departing from the inventive concept, also
Other more equivalent embodiments can be included, and the scope of the present invention is determined by scope of the appended claims.
Claims (13)
1. a kind of wafer scale preparation method of bio-identification chip, it is characterised in that including：
Dielectric insulation layer is prepared at the underlay substrate back side of chip, is prepared on the dielectric insulation layer and reroutes layer and pad；
Anti-welding layer pattern is formed on the surface for be formed with pad, wherein, the anti-welding layer pattern exposes the pad, and bag
Protection zone pattern is included, the protection zone pattern is the pattern of the pad peripheral setting range；
Baking-curing is carried out to the anti-welding layer pattern.
2. according to the method described in claim 1, it is characterised in that anti-welding layer pattern bag is formed on the surface for be formed with pad
Include：
Anti-welding layer material is coated on the surface for be formed with pad, welding resisting layer is formed；
The underlay substrate for forming welding resisting layer is subjected to precuring processing；
The welding resisting layer of the underlay substrate is exposed using the lithography mask version of predetermined pattern, and carries out development treatment, with
Etch away the welding resisting layer and expose the pad, and reservation protection zone map.
3. according to the method described in claim 1, it is characterised in that anti-welding layer pattern bag is formed on the surface for be formed with pad
Include：
The graphical silk screen being pre-designed is aligned with described chip substrate substrate；
To the chip substrate substrate solder-mask printing layer material of wire mesh arrangement, and exposure pad and pad peripheral setting range
Pattern, to form anti-welding layer pattern；
The underlay substrate for forming anti-welding layer pattern is subjected to precuring processing.
4. according to any described methods of claim 1-3, it is characterised in that the protection zone pattern is annular, encloses and is located at
The pad peripheral.
5. method according to claim 4, it is characterised in that the diameter of the ring is more than or equal to 50 μm, is less than or waits
In 1000 μm.
6. according to any described methods of claim 1-3, it is characterised in that：
Before the underlay substrate back side of chip prepares dielectric insulation layer, in addition to：The underlay substrate is ground thinned；
Through hole etching is carried out to the underlay substrate；
After the anti-welding layer pattern progress baking-curing, in addition to：The underlay substrate is cut, multiple lifes are obtained
Thing identification chip.
7. a kind of bio-identification chip, it is characterised in that the chip includes：
Underlay substrate；
Dielectric insulation layer, is arranged on the back side of the underlay substrate；
Layer and pad are rerouted, is arranged on the dielectric insulation layer；
Anti-welding layer pattern, including protection zone pattern, are partially covered on the rewiring layer, and expose the pad, its
In, the protection zone pattern is the pattern of the pad peripheral setting range.
8. chip according to claim 7, it is characterised in that the protection zone pattern is annular.
9. chip according to claim 8, it is characterised in that the annular diameter is more than or equal to 50 μm, is less than or waits
In 1000 μm.
10. chip according to claim 7, it is characterised in that the material of the anti-welding layer pattern is can the anti-solder paste of photoetching
Ink, is made of photoetching process.
11. chip according to claim 7, it is characterised in that the material of the anti-welding layer pattern limits for non-lithography performance
The anti-solder ink of system, is made of silk-screen printing technique.
12. chip according to claim 7, it is characterised in that also include：
The front of the underlay substrate is provided with bond pads and the conducting channel of induction region, and the back side of the underlay substrate is set
The pad put is solder pad.
13. chip according to claim 7, it is characterised in that the bio-identification chip is fingerprint recognition chip.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201710695720.8A CN107331629A (en) | 2017-08-15 | 2017-08-15 | The wafer scale preparation method and bio-identification chip of a kind of bio-identification chip |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710695720.8A CN107331629A (en) | 2017-08-15 | 2017-08-15 | The wafer scale preparation method and bio-identification chip of a kind of bio-identification chip |
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| CN107331629A true CN107331629A (en) | 2017-11-07 |
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ID=60225241
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Cited By (1)
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| CN116705816A (en) * | 2023-07-28 | 2023-09-05 | 甬矽半导体(宁波)有限公司 | Chip packaging structure and preparation method thereof |
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| CN104681523A (en) * | 2015-02-28 | 2015-06-03 | 苏州科阳光电科技有限公司 | Fingerprint lock recognition module packaging structure |
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| CN207183256U (en) * | 2017-08-15 | 2018-04-03 | 苏州科阳光电科技有限公司 | A kind of bio-identification chip |
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| US20110198760A1 (en) * | 2010-02-15 | 2011-08-18 | Renesas Electronics Corporation | Semiconductor device, semiconductor package, interposer, semiconductor device manufacturing method and interposer manufacturing method |
| CN104681523A (en) * | 2015-02-28 | 2015-06-03 | 苏州科阳光电科技有限公司 | Fingerprint lock recognition module packaging structure |
| CN105405853A (en) * | 2015-08-20 | 2016-03-16 | 苏州科阳光电科技有限公司 | Manufacturing process for image sensing device |
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| CN116705816A (en) * | 2023-07-28 | 2023-09-05 | 甬矽半导体(宁波)有限公司 | Chip packaging structure and preparation method thereof |
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Application publication date: 20171107 |