CN107329807B - Data delay processing method and device, and computer readable storage medium - Google Patents

Data delay processing method and device, and computer readable storage medium Download PDF

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CN107329807B
CN107329807B CN201710510902.3A CN201710510902A CN107329807B CN 107329807 B CN107329807 B CN 107329807B CN 201710510902 A CN201710510902 A CN 201710510902A CN 107329807 B CN107329807 B CN 107329807B
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pointed
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CN107329807A (en
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徐开廷
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Beijing Jingdong Century Trading Co Ltd
Beijing Jingdong Shangke Information Technology Co Ltd
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Beijing Jingdong Shangke Information Technology Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
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    • G06F9/466—Transaction processing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0727—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a storage system, e.g. in a DASD or network based storage system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751—Error or fault detection not based on redundancy
    • G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
    • G06F11/0757—Error or fault detection not based on redundancy by exceeding limits by exceeding a time limit, i.e. time-out, e.g. watchdogs

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Abstract

The invention discloses a data delay processing method and device, and relates to the technical field of data processing. The method comprises the following steps: i) establishing a container containing N1Circular linked list of individual nodes, N1According to task processing interval TsAnd a task delay duration TdTo determine N1Is an integer greater than 1; ii) setting a read pointer and a write pointer for the circular linked list, wherein the node pointed by the write pointer is the node which is previous to the node pointed by the read pointer; iii) writing the received task into the node pointed by the write pointer, reading the task in the node pointed by the read pointer and executing the task; iv) moving both the write pointer and the read pointer to the next node; v) repeating steps iii) and iv) until all tasks have been processed. The method and the device can improve the efficiency of data processing.

Description

Data delay processing method and device, and computer readable storage medium
Technical Field
The present invention relates to the field of data processing technologies, and in particular, to a data delay processing method and apparatus, and a computer-readable storage medium.
Background
In the field of data processing, situations are often encountered where delayed processing of tasks is required. For example, in electronic commerce, a user needs to wait for several minutes after receiving an order, and if the same user arrives at other orders within the time, the orders can be merged and dispatched, so that the waste of resources is reduced.
In the technical scheme of the prior art, the initiating time and the state information of each task need to be recorded, a timer is set at the same time, the initiating time of the task is compared with the current time every other fixed time, and the task conforming to the delay time is executed.
Disclosure of Invention
The inventors of the present invention have found that the following problems exist in the above prior art: each time a task is executed, the initiation time of all tasks needs to be compared with the current time, resulting in low data processing efficiency. The present inventors have devised a solution to at least one of the above-mentioned problems.
An object of the present invention is to provide a data delay processing technical solution.
According to an embodiment of the present invention, there is provided a data delay processing method including: i) establishing a container containing N1Circular linked list of individual nodes, N1According to task processing interval TsAnd a task delay duration TdTo determine N1Is an integer greater than 1; ii) setting a read pointer and a write pointer for the circular linked list, wherein the node pointed by the write pointer is the node which is previous to the node pointed by the read pointer; iii) writing the received task into the node pointed by the write pointer, reading the task in the node pointed by the read pointer and executing the task; iv) moving both the write pointer and the read pointer to a next node; v) repeating steps iii) and iv) until all tasks have been processed.
Alternatively,
Figure BDA0001335667830000021
optionally, setting an identification bit for the received task according to a task initiator; recording the corresponding relation among the task, the identification position and the node position of the task; and judging whether a task with the same identification bit as the task in the node pointed by the read pointer exists or not, and if so, merging and executing the tasks with the same identification bit.
Optionally, T is added when neededdExtension of Delta T1In the case of (2), inserting N between the node pointed to by the write pointer and the next node2A node, N2According to TsAnd Δ T1Determination of N2Is a positive integer; moving the write pointer to the next node direction, sequentially pointing to the inserted nodes, simultaneously writing the tasks into the nodes pointed by the write pointer according to the receiving sequence, and stopping the read pointer at the nodes pointed by the current point until delta T1And (6) ending.
Alternatively,
Figure BDA0001335667830000022
optionally, T is added when neededdShortening of DeltaT2Under the condition of (1), moving the read pointer to the next node direction, and reading the N pointed by the read pointer in sequence3After the tasks in each node are executed, N is deleted3Each of the nodes, N3According to TsAnd Δ T2Determining; and stopping the write pointer at the node pointed to currently until the deletion operation is finished.
Alternatively,
Figure BDA0001335667830000023
according to another embodiment of the present invention, there is provided a data delay processing apparatus including: a memory for storing the task to be executed, the memory having a storage structure comprising N1Circular linked list of individual nodes, N1According to task processing interval TsAnd a task delay duration TdTo determine N1Is an integer greater than 1; the processor is used for writing tasks into the memory and reading tasks from the memory and executing the tasks, and comprises the following steps: i) setting a read pointer and a write pointer for the circular linked list, wherein the node pointed by the write pointer is the node which is previous to the node pointed by the read pointer; ii) writing the received task into the node pointed by the write pointer, reading the task in the node pointed by the read pointer and executing the task; iii) moving both said write pointer and said read pointer to a next node; iv) repeating steps ii) and iii) until all tasks have been processed.
Optionally, the step ii) executed by the processor includes setting an identification bit for the received task according to the task initiator; recording the corresponding relation among the task, the identification position and the node position of the task; and judging whether a task with the same identification bit as the task in the node pointed by the read pointer exists or not, and if so, merging and executing the tasks with the same identification bit.
Optionally, T is added when neededdExtension of Delta T1In the case where the memory inserts N between the node to which the write pointer points and the next node2A node, N2According to TsAnd ΔT1Determination of N2Is a positive integer; the processor moves the write pointer to the next node direction, sequentially points to the inserted nodes, simultaneously writes tasks into the nodes pointed by the write pointer respectively according to the receiving sequence, and stops the read pointer at the nodes pointed by the current point until delta T1And (6) ending.
Optionally, T is added when neededdShortening of DeltaT2Under the condition that the read pointer points to the next node, the processor moves the read pointer to the next node direction, and reads the N pointed by the read pointer in sequence3Task and execution in individual nodes, N3According to TsAnd Δ T2Determining N after the memory delete execution3And before each node, stopping the write pointer at the node pointed at currently.
According to still another embodiment of the present invention, there is provided a data delay processing apparatus including: a memory and a processor coupled to the memory, the processor configured to execute the data delay processing method of any of the above embodiments based on instructions stored in the memory device.
According to still another embodiment of the present invention, there is provided a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements the data delay processing method in any of the above embodiments.
According to still another embodiment of the present invention, there is provided a data delay processing apparatus including means for executing the data delay processing method according to any one of the above embodiments.
One advantage of the present invention is that a circular linked list is established according to the delay time to store the task to be executed, and the write pointer is set at a node on the read pointer, so that the task can be accurately executed according to the delay time without comparing the task initiation time with the current time, thereby improving the efficiency of data processing.
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The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.
The invention will be more clearly understood from the following detailed description, taken with reference to the accompanying drawings, in which:
fig. 1 shows a flow chart of one embodiment of a data delay processing method of the present invention.
Fig. 2 shows a schematic diagram of an embodiment of the data delay processing method of the present invention.
Fig. 3 shows a schematic diagram of another embodiment of the data delay processing method of the present invention.
Fig. 4 shows a schematic diagram of a further embodiment of the data delay processing method of the present invention.
Fig. 5 shows a flow chart of another embodiment of the data delay processing method of the present invention.
Fig. 6 is a block diagram showing an embodiment of a data delay processing apparatus of the present invention.
Fig. 7 is a block diagram showing another embodiment of the data delay processing apparatus of the present invention.
Detailed Description
Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, the numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise.
Meanwhile, it should be understood that the sizes of the respective portions shown in the drawings are not drawn in an actual proportional relationship for the convenience of description.
The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.
Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.
In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.
Fig. 1 shows a flow chart of one embodiment of a data delay processing method of the present invention.
As shown in FIG. 1, in step 110, a container N is established1Circular linked list of individual nodes, N1According to task processing interval TsAnd a task delay duration TdTo determine N1Is an integer greater than 1. The total number of nodes can be set as
Figure BDA0001335667830000051
For example, the task needs to be executed for 20 minutes in a delayed manner, and the interval of task processing is 2 minutes, the total number of nodes in the circular linked list can be set to 10.
In step 120, a read pointer and a write pointer are set for the circular linked list, and the node pointed by the write pointer is the node previous to the node pointed by the read pointer.
In one embodiment, the task is required to be executed after delaying for 10 minutes, and the task processing interval is 1 minute, then a circular linked list as shown in fig. 2 may be established as the task pool. In fig. 2, the circular linked list has 10 nodes, the node initially pointed to by the read pointer is node 1, and the node initially pointed to by the write pointer is node 10.
In step 130, the received task is written into the node pointed by the write pointer, and the task in the node pointed by the read pointer is read and executed.
In step 140, both the write pointer and the read pointer are moved to the next node.
In step 150, it is determined whether all tasks have been performed. If so, then the write and read tasks are not resumed (step 160); if not, return to execute step 130.
In one embodiment, as shown in fig. 2, first, a write pointer writes a first received task into node 10, and a read pointer reads a task stored in node 1, where no task has been written into node 1, so that no task is executed; then, the write pointer points to the next node 1, and writes the received task into the node 1, and the read pointer points to the next node 2, and at this time, the task is not written into the node 2, so the task is not executed; proceeding so, when the write pointer points to node 9, the received task is written to node 9, while the read pointer points to node 10, and the task previously written to node 10 is read and executed. At this time, the writing time of the task in the node 10 is just 10 minutes, which meets the requirement of delayed execution of the task, and then the read pointer and the write pointer continue to move to the next node and repeat the above process until all tasks are processed.
In another embodiment, T is added when neededdExtension of Delta T1In the case of (2), N is inserted between the node pointed to by the write pointer and the next node2A node, N2According to TsAnd Δ T1Determination of N2Is a positive integer. The increased number of nodes can satisfy
Figure BDA0001335667830000052
For example, if the time needs to be prolonged by 10 minutes and the task processing interval is 2 minutes, 5 nodes can be added; moving the write pointer to the next node direction, sequentially pointing to the inserted nodes, simultaneously writing the tasks into the nodes pointed by the write pointer according to the receiving sequence, respectively, and stopping the read pointer at the nodes pointed by the current point until delta T1And (6) ending.
For example, if the task originally needs to be delayed for 10 minutes, the task is delayed for 20 minutes, and the task execution interval is 1 minute, 10 new nodes may be inserted into the original circular list. As shown in fig. 3, the node to which the write pointer currently points is node 1, and the node to which the read pointer points is node 2, and first, 10 new nodes are inserted between node 1 and node 2: node 101-110; then, the write pointer moves to the node 101, and writes the received task to the node 101; the write pointer continues to move until the received tasks are written into the nodes 101 and 110 in sequence, and the read pointer always points to the node 2 in the period of time; when the read pointer points to the node 110, the read pointer reads the task in the node 2 and executes the task, and the write-in time of the task in the node 2 is just 20 minutes at this time, which meets the specified task delay time; then, the write pointer and the read pointer move to the next node respectively, and read-write operation is carried out until all tasks are processed.
In yet another embodiment, T is added when neededdShortening of DeltaT2In the case of (1), the read pointer is moved to the next node direction, and N to which the read pointer points in sequence is read3After the tasks in each node are executed, N is deleted3A node, N3According to TsAnd Δ T2Determining; the write pointer is held at the node currently pointed to until the deletion operation is finished. The number of nodes deleted may be set to
Figure BDA0001335667830000061
For example, if the task delay time needs to be shortened by 4 minutes and the task processing interval is 2 minutes, 2 nodes are deleted.
For example, if the task originally needs to be executed with a delay of 10 minutes, and now is executed with a delay of 7 minutes, and the task execution interval is 1 minute, the circular linked list may be deleted by 3 nodes. As shown in FIG. 4, the write pointer points to node 1 and the read pointer points to node 2; firstly, a read pointer reads and executes tasks in nodes 2, 3 and 4, and a write pointer stays at node 1 all the time; then the read pointer is moved to node 5, and nodes 2, 3 and 4 are deleted; the task in node 5 is executed with a delay of just 7 minutes from the write time of the task in node 5.
In the above embodiment, the circular linked list is established as the task pool according to the task delay time, the write pointer is set at a node on the read pointer, and the tasks in the circular linked list are respectively subjected to write and read processing. The method and the device can accurately control the task to be executed according to the delay time without consuming a large amount of resources to compare the current time with the task execution time, thereby improving the data processing efficiency and the accuracy of task delay. And the node number of the circular linked list can be changed according to the change of the delay time, thereby improving the flexibility of data processing.
Fig. 5 shows a flow chart of another embodiment of the data delay processing method of the present invention.
As shown in fig. 5, step 130 in the previous embodiment includes the following steps:
for example, as shown in FIG. 2, two tasks A and B are received when the write pointer points to node 10, the identification bits of the two tasks are set to α and β according to the task initiator, the two tasks are stored in node 10 in a data structure of { key: α, value: A } and { key: β, value: B }, the write pointer receives task C when the write pointer points to node 1, the identification bit of the task is set to α according to the task initiator, and the task is stored in node 1 in a data structure of { key: α, value: C }.
In step 1302, the corresponding relationship between the task, the identification bit and the node position where the task is located is recorded.
For example, while writing tasks to the circular linked list, the tasks may be written to memories outside the circular linked list such as { key: α, value (A, 10), (C, 1) } and
β, value (B, 10) } records the corresponding relation between the task, the identification bit and the node, and updates the record according to the identification bit of the newly written task.
In step 1303, it is determined whether there is a task having the same identification bit as the task in the node pointed to by the read pointer. If yes, merging and executing the tasks with the same identification bits (step 1304); if not, then only the tasks in the node pointed to by the read pointer are executed (step 1305).
For example, when the read pointer points to node 10, task a and its identifier α stored in node 10 are read, task C, whose identifier is also α, is found in the record in memory, and tasks a and C are merged and executed.
In the embodiment, when the task is written into the circular linked list, the flag bit is set for the task according to the task initiator; and when the tasks are read from the circular linked list, searching the tasks with the identification bits and executing the tasks in a merging mode. The method and the device can realize the simultaneous execution of the tasks identical to the initiator, thereby avoiding the repeated consumption of resources, reducing the cost and improving the efficiency of task execution.
Fig. 6 is a block diagram showing an embodiment of a data delay processing apparatus of the present invention.
As shown in fig. 6, the apparatus includes a memory 61 and a processor 62.
The memory 61 is used to store tasks to be performed. For example, the initial memory structure of the memory is N1Circular linked list of individual nodes, N1According to task processing interval TsAnd a task delay duration TdTo determine N1Is an integer greater than 1.
The processor 62 is configured to write tasks into the memory and read tasks from the memory and execute the tasks, and includes the following steps: i) setting a read pointer and a write pointer for the circular linked list, wherein the node pointed by the write pointer is the previous node of the nodes pointed by the read pointer; ii) writing the received task into the node pointed by the write pointer, reading the task in the node pointed by the read pointer and executing the task; iii) moving both the write pointer and the read pointer to the next node; iv) repeating steps ii) and iii) until all tasks have been processed.
In one embodiment, the processor performs step ii) comprising: setting an identification bit for a received task according to a task initiator; recording the corresponding relation between the task, the identification position and the position of the node where the task is located; and judging whether a task with the same identification bit as the task in the node pointed by the read pointer exists or not, and if so, merging and executing the tasks with the same identification bit. For example, in the field of electronic commerce, the device can automatically realize that the order is not sent after receiving the order of the user, but the order is waited for 10 minutes first; if the user has reached other orders to be served within 10 minutes, the orders are merged together for serving.
In another embodiment, T is added when neededdExtension of Delta T1In the case of (2), the memory 61 inserts N between the node pointed to by the write pointer and the next node2A node, N2According to TsAnd Δ T1Determination of N2Is a positive integer; the processor moves the write pointer to the next node direction, points to the inserted nodes in sequence, and simultaneously receives the data according to the receiving orderRespectively writing the tasks into the nodes pointed by the write pointer, and stopping the read pointer at the nodes pointed by the write pointer till delta T1And (6) ending.
In yet another embodiment, T is added when neededdShortening of DeltaT2In this case, the processor 62 moves the read pointer to the next node, and reads the N points to which the read pointer points in sequence3After the tasks in the nodes are executed, the memory deletes N3A node, N3According to TsAnd Δ T2It is determined that the processor stalls the write pointer at the currently pointing node until the delete operation is complete. For example, if the task delay time is shortened from 10 minutes to 5 minutes, the processor 62 not only executes the task that has been waiting for 10 minutes, but also executes the task that has been waiting for more than 5 minutes at a time.
In the embodiment, the number of the nodes of the circular linked list in the memory is determined according to the task delay time, and the tasks with the same identification bits are merged, so that the accurate control of the task execution time can be automatically realized, the consumption of a large amount of resources to process unrelated tasks is avoided, and the data processing efficiency is improved; when the task delay time is changed, the number of the nodes of the circular linked list in the memory is increased or reduced, and the flexibility of data processing is improved.
Fig. 7 is a block diagram showing another embodiment of the data delay processing apparatus of the present invention.
As shown in fig. 7, the apparatus 70 of this embodiment includes: a memory 71 and a processor 72 coupled to the memory 71, the processor 72 being configured to execute the data delay processing method according to any of the embodiments of the present invention based on instructions stored in the memory 71.
The memory 71 may include, for example, a system memory, a fixed nonvolatile storage medium, and the like. The system memory stores, for example, an operating system, an application program, a Boot Loader (Boot Loader), a database, and other programs.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable non-transitory storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
So far, the data delay processing method and apparatus, and the computer-readable storage medium according to the present invention have been described in detail. Some details well known in the art have not been described in order to avoid obscuring the concepts of the present invention. It will be fully apparent to those skilled in the art from the foregoing description how to practice the presently disclosed embodiments.
The method and system of the present invention may be implemented in a number of ways. For example, the methods and systems of the present invention may be implemented in software, hardware, firmware, or any combination of software, hardware, and firmware. The above-described order for the steps of the method is for illustrative purposes only, and the steps of the method of the present invention are not limited to the order specifically described above unless specifically indicated otherwise. Furthermore, in some embodiments, the present invention may also be embodied as a program recorded in a recording medium, the program including machine-readable instructions for implementing a method according to the present invention. Thus, the present invention also covers a recording medium storing a program for executing the method according to the present invention.
Although some specific embodiments of the present invention have been described in detail by way of illustration, it should be understood by those skilled in the art that the above illustration is only for the purpose of illustration and is not intended to limit the scope of the invention. It will be appreciated by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.

Claims (14)

1. A data delay processing method, comprising:
i) establishing a container containing N1Circular linked list of individual nodes, N1According to task processing interval TsAnd a task delay duration TdTo determine N1Is an integer greater than 1;
ii) setting a read pointer and a write pointer for the circular linked list, wherein the node pointed by the write pointer is the node which is previous to the node pointed by the read pointer;
iii) writing the received task into the node pointed by the write pointer, reading the task in the node pointed by the read pointer and executing the task;
iv) when T is not requireddUnder the condition of extension or shortening, moving the write pointer and the read pointer to a next node;
v) repeating steps iii) and iv) until all tasks have been processed;
wherein step iii) comprises:
and writing the task received for the first time into the node pointed by the write pointer, wherein in the case, the task is not written into the node pointed by the read pointer and the task is not executed.
2. The data delay processing method of claim 1,
Figure FDA0002267602340000011
3. the data delay processing method of claim 1, wherein step iii) comprises:
setting an identification bit for the received task according to a task initiator;
recording the corresponding relation among the task, the identification position and the node position of the task;
and judging whether a task with the same identification bit as the task in the node pointed by the read pointer exists or not, and if so, merging and executing the tasks with the same identification bit.
4. A data delay processing method according to any one of claims 1 to 3, further comprising:
when needed, T is addeddExtension ofΔT1In the case of (2), inserting N between the node pointed to by the write pointer and the next node2A node, N2According to TsAnd Δ T1Determination of N2Is a positive integer;
moving the write pointer to the next node direction, sequentially pointing to the inserted nodes, simultaneously writing the tasks into the nodes pointed by the write pointer according to the receiving sequence, and stopping the read pointer at the nodes pointed by the current point until delta T1And (6) ending.
5. The data delay processing method of claim 4, wherein,
Figure FDA0002267602340000012
6. a data delay processing method according to any one of claims 1 to 3, further comprising:
when needed, T is addeddShortening of DeltaT2Under the condition of (1), moving the read pointer to the next node direction, and reading the N pointed by the read pointer in sequence3After the tasks in each node are executed, N is deleted3Each of the nodes, N3According to TsAnd Δ T2Determining;
and stopping the write pointer at the node pointed to currently until the deletion operation is finished.
7. The data delay processing method of claim 6,
Figure FDA0002267602340000021
8. a data delay processing apparatus comprising:
a memory for storing the task to be executed, the memory having a storage structure comprising N1Circular linked list of individual nodes, N1According to task processing interval TsAnd a task delay duration TdTo determine N1Is an integer greater than 1;
the processor is used for writing tasks into the memory and reading tasks from the memory and executing the tasks, and comprises the following steps:
i) setting a read pointer and a write pointer for the circular linked list, wherein the node pointed by the write pointer is the node which is previous to the node pointed by the read pointer;
ii) writing the received task into the node pointed by the write pointer, reading the task in the node pointed by the read pointer and executing the task;
iii) when T is not requireddUnder the condition of extension or shortening, moving the write pointer and the read pointer to a next node;
iv) repeating steps ii) and iii) until all tasks have been processed;
wherein step ii) comprises:
and writing the task received for the first time into the node pointed by the write pointer, wherein in the case, the task is not written into the node pointed by the read pointer and the task is not executed.
9. The data delay processing apparatus of claim 8, wherein the processor performs step ii) comprising:
setting an identification bit for the received task according to a task initiator;
recording the corresponding relation among the task, the identification position and the node position of the task;
and judging whether a task with the same identification bit as the task in the node pointed by the read pointer exists or not, and if so, merging and executing the tasks with the same identification bit.
10. The data delay processing apparatus according to claim 8 or 9,
when needed, T is addeddExtension of Delta T1In the case where the memory inserts N between the node to which the write pointer points and the next node2A node, N2According to TsAnd Δ T1Determination of N2Is a positive integer;
the processor moves the write pointer to the next node direction, sequentially points to the inserted nodes, simultaneously writes tasks into the nodes pointed by the write pointer respectively according to the receiving sequence, and stops the read pointer at the nodes pointed by the current point until delta T1And (6) ending.
11. A data delay processing apparatus as claimed in claim 8 or 9, wherein T is delayed if requireddShortening of DeltaT2In the case of (2), the processor
Moving the read pointer to the next node direction, and reading the N pointed by the read pointer in sequence3Task and execution in individual nodes, N3According to TsAnd Δ T2It is determined that,
n after the memory delete execution3And before each node, stopping the write pointer at the node pointed at currently.
12. A data delay processing apparatus comprising:
a memory; and
a processor coupled to the memory, the processor configured to perform the data latency processing method of any one of claims 1-7 based on instructions stored in the memory device.
13. A computer-readable storage medium, on which a computer program is stored which, when executed by a processor, implements a data delay processing method as claimed in any one of claims 1 to 7.
14. A data delay processing apparatus comprising means for performing the data delay processing method according to any one of claims 1 to 7.
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CN101630276A (en) * 2009-08-18 2010-01-20 深圳市融创天下科技发展有限公司 High-efficiency memory pool access method
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