CN107329731A - A kind of I2S signal transmission systems - Google Patents
A kind of I2S signal transmission systems Download PDFInfo
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- CN107329731A CN107329731A CN201710586535.5A CN201710586535A CN107329731A CN 107329731 A CN107329731 A CN 107329731A CN 201710586535 A CN201710586535 A CN 201710586535A CN 107329731 A CN107329731 A CN 107329731A
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- 230000008054 signal transmission Effects 0.000 title claims abstract description 43
- 238000011084 recovery Methods 0.000 claims abstract description 69
- 230000005540 biological transmission Effects 0.000 claims abstract description 45
- 238000000034 method Methods 0.000 claims abstract description 14
- 239000000872 buffer Substances 0.000 claims description 45
- 230000001360 synchronised effect Effects 0.000 claims description 4
- 101150035574 mcl2 gene Proteins 0.000 description 3
- 230000005611 electricity Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/16—Sound input; Sound output
- G06F3/162—Interface to dedicated audio devices, e.g. audio drivers, interface to CODECs
Abstract
The invention belongs to field of signal transmissions, there is provided a kind of I2S signal transmission systems；The present invention is by the way that including dispensing device, the first USB port, USB transmission line, the second USB port and reception device, reception device includes transmission recovery module；Dispensing device sends the first I2S signals, first I2S signals are transmitted to reception device via the first USB port, USB transmission line and the second USB port and decay to the 2nd I2S signals successively, and the transmission recovery module in reception device is forwarded to the 2nd I2S signals, synchronization process or waveform are recovered to generate the 3rd I2S signals；Wherein, the 3rd information that the 3rd I2S signals are carried is identical with the first information that the first I2S signals are carried；Therefore reduce the cost of I2S signal transmission systems and reduce the distorted signals in transmitting procedure.
Description
Technical field
The invention belongs to field of signal transmissions, more particularly to a kind of I2S signal transmission systems.
Background technology
Conventionally, as ((Inter-IC Sound, integrated circuit built-in audio bus) signal is high frequency to I2S
Square-wave signal, easy distortion when transmitting over long distances, therefore when needing transmission I2S signals over long distances, transmitting terminal first turns I2S signals
Bluetooth signal or audio analog signals are changed to, receiving terminal receives after Bluetooth signal or audio analog signals, then bluetooth is believed
Number or audio analog signals be reduced to I2S signals.Because transmitting terminal and receiving terminal are required to configure chromacoder, so that
It result in I2S signal transmission systems cost high, and signal can be caused during chromacoder conversion signal in various degree
Distortion.
Therefore, there is chromacoder and result in I2S signal transmission systems cost height and transmitting procedure in prior art
In distorted signals the problem of.
The content of the invention
The invention provides a kind of I2S signal transmission systems, it is intended to solves the I2S signals transmission system present in prior art
Cost of uniting is high and transmitting procedure in distorted signals the problem of.
The present invention is achieved in that a kind of I2S signal transmission systems, and the I2S signal transmission systems, which include sending, to be filled
Put, the first USB port, USB transmission line, the second USB port and reception device, the reception device includes transmission and recovers mould
Block；
The dispensing device, the input/output terminal of first USB port, the USB transmission line, the 2nd USB ends
The input/output terminal of mouth and the input of the transmission recovery module in the reception device are sequentially connected；
The dispensing device sends the first I2S signals, and the first I2S signals are successively via first USB port, institute
State USB transmission line and second USB port transmits to the reception device and decays to the 2nd I2S signals, the reception
The transmission recovery module in device is forwarded to the 2nd I2S signals, synchronization process or waveform are recovered to generate the 3rd
I2S signals；Wherein, the first information phase that the 3rd information that the 3rd I2S signals are carried is carried with the first I2S signals
Together.
The beneficial effect that the technical scheme that the present invention is provided is brought is：It was found from the invention described above, due to the transmission of I2S signals
System includes dispensing device, the first USB port, USB transmission line, the second USB port and reception device, and reception device includes passing
Defeated recovery module；Dispensing device send the first I2S signals, the first I2S signals successively via the first USB port, USB transmission line with
And second USB port transmit to reception device and decay to the transmission recovery module in the 2nd I2S signals, reception device to institute the
Two I2S signals are forwarded, synchronization process or waveform are recovered to generate the 3rd I2S signals；Wherein, the 3rd I2S signals are carried
3rd information is identical with the first information that the first I2S signals are carried；Therefore reduce the cost of I2S signal transmission systems and reduce
Distorted signals in transmitting procedure.
Brief description of the drawings
Technical scheme in order to illustrate the embodiments of the present invention more clearly, makes required in being described below to embodiment
Accompanying drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the present invention, for
For those of ordinary skill in the art, on the premise of not paying creative work, other can also be obtained according to these accompanying drawings
Accompanying drawing.
Fig. 1 is a kind of function structure chart of I2S signal transmission systems provided in an embodiment of the present invention；
Fig. 2 is a kind of function structure chart that I2S signal transmission systems provided in an embodiment of the present invention transmit recovery module；
Fig. 3 is another function structure chart that I2S signal transmission systems provided in an embodiment of the present invention transmit recovery module；
Fig. 4 is another function structure chart that I2S signal transmission systems provided in an embodiment of the present invention transmit recovery module；
Fig. 5 be I2S signal transmission systems provided in an embodiment of the present invention in short circuit module a kind of exemplary circuit structure
Figure；
Fig. 6 be I2S signal transmission systems provided in an embodiment of the present invention in buffer module a kind of exemplary circuit structure
Figure；
Fig. 7 be I2S signal transmission systems provided in an embodiment of the present invention in waveform recovery module a kind of exemplary circuit
Structure chart；
Fig. 8 be I2S signal transmission systems provided in an embodiment of the present invention in USB3.0 ports a kind of exemplary circuit knot
Composition；
Fig. 9 is a kind of exemplary circuit structure chart of I2S signal transmission systems provided in an embodiment of the present invention；
Figure 10 is another exemplary circuit structure chart of I2S signal transmission systems provided in an embodiment of the present invention；
Figure 11 is another exemplary circuit structure chart of I2S signal transmission systems provided in an embodiment of the present invention；
Figure 12 is another exemplary circuit structure chart of I2S signal transmission systems provided in an embodiment of the present invention.
Embodiment
In order to make the purpose , technical scheme and advantage of the present invention be clearer, it is right below in conjunction with drawings and Examples
The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and
It is not used in the restriction present invention.
Fig. 1 shows the modular structure of I2S signal transmission systems provided in an embodiment of the present invention, for convenience of description, only
The part related to the embodiment of the present invention is shown, details are as follows：
A kind of I2S signal transmission systems it include dispensing device 01, the first USB port 02, USB transmission line 03, the 2nd USB
Port 04 and reception device 05, reception device 05 include transmission recovery module 051.
Wherein, dispensing device 01, the input/output terminal of the first USB port 02, USB transmission line 03, second USB port 04
The input of transmission recovery module 051 in input/output terminal and reception device 05 is sequentially connected.
In above-mentioned I2S signal transmission systems, dispensing device 01 send the first I2S signals, the first I2S signals successively via
First USB port 02, the USB port 04 of USB transmission line 03 and second transmit to reception device 05 and decay to the 2nd I2S letters
Number, 051 pair of the 2nd I2S signal of transmission recovery module in reception device 05 is forwarded, synchronization process or waveform recover with
Generate the 3rd I2S signals；Wherein, the first information phase that the 3rd information that the 3rd I2S signals are carried is carried with the first I2S signals
Together.
When the 2nd I2S signals are synchronous and undistorted, transmission recovery module 051 is the first short circuit module；First short circuit mould
Block is forwarded to generate the 3rd I2S signals to the 2nd I2S signals.
As shown in Fig. 2 when the 2nd I2S signals are asynchronous and undistorted, transmission recovery module 051 includes the first buffering mould
The short circuit module 0512 of block 0511 and second；The output end of first buffer module 0511 and the input of the second short circuit module 0512 connect
Connect；First buffer module synchronizes processing to the 2nd I2S signals, and the second short circuit module is believed the 2nd I2S after synchronization process
Number forwarded to generate the 3rd I2S signals.
As shown in figure 3, when the 2nd I2S signals synchronization and distortion, transmission recovery module 051 includes the 3rd short circuit module
0513 and first waveform recovery module 0514；The output end of 3rd short circuit module 0513 is defeated with first waveform recovery module 0514
Enter end connection；First short circuit module is forwarded to the 2nd I2S signals, and first waveform recovery module is to the 2nd I2S after forwarding
Signal carries out waveform and recovers to generate the 3rd I2S signals.
As shown in figure 4, when the 2nd I2S signals are asynchronous and during distortion, transmission recovery module 051 includes the second buffer module
0515 and the second waveform recovery module 0516；The output end of second buffer module 0515 is defeated with the second waveform recovery module 0516
Enter end connection；Second buffer module synchronizes processing to the 2nd I2S signals, after the second waveform recovery module is to synchronization process
2nd I2S signals carry out waveform and recover to generate the 3rd I2S signals.
The circuit structure of first short circuit module, the second short circuit module 0512 and the 3rd short circuit module 0513 is identical, such as Fig. 5
Shown, short circuit module includes first resistor R1, second resistance R2,3rd resistor R3 and the 4th resistance R4.
First resistor R1 first end is the first input end of short circuit module, and first resistor R1 the second end is short circuit module
The first output end, second resistance R2 first end is the second input of short circuit module, and second resistance R2 the second end is short
Second output end of connection module, 3rd resistor R3 first end is the 3rd input of short circuit module, the second of 3rd resistor R3
The 3rd output end for short circuit module is held, the 4th resistance R4 first end is the 4th input of short circuit module, the 4th resistance R4
The second end be short circuit module the 4th output end.
4th input of the first input end of short circuit module to short circuit module constitutes the input of short circuit module, short circuit mould
First output end of block constitutes the output end of short circuit module to the 4th output end of short circuit module.
First buffer module 0511 is identical with the circuit structure of the second buffer module 0515, as shown in fig. 6, buffer module bag
Include the first electric capacity C1, the second electric capacity C2, the 3rd electric capacity C3, the 4th electric capacity C4, the 5th resistance R5, the 6th resistance R6, the 7th resistance
R7 and the 8th resistance R8.
5th resistance R5 first end is the first input end of buffer module, the 5th resistance R5 the second end and the first electric capacity
C1 first end is the first output end of buffer module, and the 6th resistance R6 first end is the first input end of buffer module, the
Six resistance R6 the second end and the second electric capacity C2 first end are the first output end of buffer module, the 7th resistance R7 first end
For the first input end of buffer module, the 7th resistance R7 the second end and the 3rd electric capacity C3 first end are the first of buffer module
Output end, the 8th resistance R8 first end is the first input end of buffer module, the 8th resistance R8 the second end and the 4th electric capacity
C4 first end is the first output end of buffer module, the first electric capacity C1 the second end, the second electric capacity C2 the second end, the 3rd electricity
Appearance C3 the second end and the 4th electric capacity C4 the second end with being connected to power supply altogether.
The first input end of buffer module constitutes the input of buffer module to the 4th input of buffer module, buffers mould
4th output end of the first output end of block to buffer module constitutes the output end of buffer module.
First waveform recovery module 0514 is identical with the circuit structure of the second waveform recovery module 0516, as shown in fig. 7, ripple
Shape recovery module include the first triode Q1, the second triode Q2, the 3rd triode Q3, the 4th triode Q4, the 9th resistance R9,
Tenth resistance R10, the 11st resistance R11, the 12nd resistance R12, the 13rd resistance R13, the 14th resistance R14, the 15th electricity
Hinder R15 and the 16th resistance R16.
The first input end of first triode Q1 transmitting extremely waveform recovery module, the first triode Q1 colelctor electrode and
9th resistance R9 first end is the first output end of waveform recovery module, the first triode Q1 base stage and the tenth resistance R10
First end connection, the second input of the second triode Q2 transmitting extremely waveform recovery module, the second triode Q2 collection
Electrode and the 11st resistance R11 first end are the second output end of waveform recovery module, the second triode Q2 base stage and the
12 resistance R12 first end connection, the 3rd input of the 3rd triode Q3 transmitting extremely waveform recovery module, the three or three
Pole pipe Q3 colelctor electrode and the 13rd resistance R13 first end are the 3rd output end of waveform recovery module, the 3rd triode Q3
Base stage be connected with the 14th resistance R14 first end, the 4th triode Q4 transmitting extremely waveform recovery module it is the 4th defeated
Enter end, the 4th triode Q4 colelctor electrode and the 4th output end that the 15th resistance R15 first end is waveform recovery module, the
Four triode Q4 base stage is connected with the 16th resistance R16 first end, the 9th resistance R9 the second end, the tenth resistance R10
Second end, the 11st resistance R11 the second end, the 12nd resistance R12 the second end, the 13rd resistance R13 the second end, the tenth
Second end at four resistance R14 the second end, the 15th resistance R15 the second end and the 16th resistance R16 with the first power supply
Connection.
The first input end of waveform recovery module to the 4th input of waveform recovery module constitutes waveform recovery module
Input, the 4th output end of the first output end to the waveform recovery module of waveform recovery module constitutes the defeated of waveform recovery module
Go out end.
First USB port 02 is identical with the circuit structure of the second USB port 04.
As shown in figure 8, the power end VBUS of USB3.0 ports is connected with second source, the USB2.0 data of USB3.0 ports
Negative pole end D- is the first input/output terminal of USB3.0 ports, and the USB2.0 data positive terminals D+ of USB3.0 ports is USB3.0 ends
Second input/output terminal of mouth, the high speed of USB3.0 ports receives threeth inputs of the data negative pole end SSRX- for USB3.0 ports
Output end, the high speed of USB3.0 ports receives the 4th input/output terminal that data positive terminal SSRX+ is USB3.0 ports, USB3.0
The high speed of port sends the 5th input/output terminal that data negative pole end SSTX- is USB3.0 ports, the high speed hair of USB3.0 ports
Send the 6th input/output terminal that data positive terminal SSTX+ is USB3.0 ports, the earth terminal GND and USB3.0 ends of USB3.0 ports
The feedback signal earth terminal GND_DRAIN of mouth with being connected to power supply altogether.
3rd input/output terminal of USB3.0 ports to the 6th input/output terminal of USB3.0 ports collectively forms USB3.0
The input/output terminal of port.
In specific implementation, the USB port of dispensing device 01 can connect the first USB port 02 to realize I2S long range
Transmission, can also connect USB2.0 USB flash disk.
The I2S signal transmission systems shown in Fig. 9 are described further below in conjunction with operation principle：
Dispensing device 01 sends the first I2S signals, and the first I2S signals include I2S_MCL1, I2S_BCLK1, I2S_
LRCLK1 and I2S_SD1, the first I2S signals are successively via the first USB port 02, the USB port of USB transmission line 03 and second
04 transmits to reception device 05 and decays to the 2nd I2S signals, and the 2nd I2S signals include I2S_MCL2, I2S_BCLK2, I2S_
LRCLK2 and I2S_SD2, because the 2nd I2S signals are synchronous and undistorted, the first resistor R1 in reception device 05 is to I2S_
MCL2 is forwarded to be forwarded to generate with generating the second resistance R2 in I2S_MCL3, reception device 05 to I2S_BCLK2
3rd resistor R3 in I2S_BCLK3, reception device 05 is forwarded to generate I2S_LRCLK3 to I2S_LRCLK2, receives dress
The 4th resistance R4 set to 0 in 5 is forwarded to generate I2S_SD3 to I2S_SD2；I2S_MCL3、I2S_BCLK3、I2S_
LRCLK3 and I2S_SD3 collectively constitute the 3rd I2S signals；Wherein, the 3rd I2S signals are carried the 3rd information and the first I2S
The first information that signal is carried is identical.
The I2S signal transmission systems shown in Figure 10 are described further below in conjunction with operation principle：
Dispensing device 01 sends the first I2S signals, and the first I2S signals include I2S_MCL1, I2S_BCLK1, I2S_
LRCLK1 and I2S_SD1, the first I2S signals are successively via the first USB port 02, the USB port of USB transmission line 03 and second
04 transmits to reception device 05 and decays to the 2nd I2S signals, and the 2nd I2S signals include I2S_MCL2, I2S_BCLK2, I2S_
LRCLK2 and I2S_SD2, because the 2nd I2S signals are asynchronous and undistorted, the 5th resistance R5 and the first electric capacity C1 are to I2S_
MCL2 is cached, and the 6th resistance R6 and the second electric capacity C2 are cached to I2S_BCLK2, the 7th resistance R7 and the 3rd electric capacity C3
I2S_LRCLK2 is cached, the 8th resistance R8 and the 4th electric capacity C4 are cached to I2S_SD2, to realize the after caching
The synchronization of two I2S signals, first resistor R1 is forwarded to generate I2S_MCL3, second resistance R2 to the I2S_MCL2 after caching
I2S_BCLK2 after caching is forwarded to generate I2S_BCLK3,3rd resistor R3 is carried out to the I2S_LRCLK2 after caching
Forwarding is to generate I2S_LRCLK3, and the 4th resistance R4 is forwarded to generate I2S_SD3 to the I2S_SD2 after caching；I2S_
MCL3, I2S_BCLK3, I2S_LRCLK3 and I2S_SD3 collectively constitute the 3rd I2S signals；Wherein, the 3rd I2S signals are carried
The 3rd information it is identical with the first information that the first I2S signals are carried.
The I2S signal transmission systems shown in Figure 11 are described further below in conjunction with operation principle：
Dispensing device 01 sends the first I2S signals, and the first I2S signals include I2S_MCL1, I2S_BCLK1, I2S_
LRCLK1 and I2S_SD1, the first I2S signals are successively via the first USB port 02, the USB port of USB transmission line 03 and second
04 transmits to reception device 05 and decays to the 2nd I2S signals, and the 2nd I2S signals include I2S_MCL2, I2S_BCLK2, I2S_
LRCLK2 and I2S_SD2, due to the 2nd I2S signals synchronization and distortion, second resistance R2 is forwarded to I2S_BCLK2, the
Three resistance R3 are forwarded to I2S_LRCLK2, and the 4th resistance R4 is forwarded to I2S_SD2, after the first triode Q1 is to forwarding
I2S_MCL2 carry out waveform and recover to generate I2S_MCL3, the second triode Q2 carries out waveform to the I2S_BCLK2 after forwarding
Recover to generate I2S_BCLK3, the 3rd triode Q3 carries out waveform to the I2S_LRCLK2 after forwarding and recovered to generate I2S_
LRCLK3, the 4th triode Q4 carry out waveform to the I2S_SD2 after forwarding and recovered to generate I2S_SD3, I2S_MCL3, I2S_
BCLK3, I2S_LRCLK3 and I2S_SD3 collectively constitute the 3rd I2S signals；Wherein, the 3rd information that the 3rd I2S signals are carried
It is identical with the first information that the first I2S signals are carried.
The I2S signal transmission systems shown in Figure 12 are described further below in conjunction with operation principle：
Dispensing device 01 sends the first I2S signals, and the first I2S signals include I2S_MCL1, I2S_BCLK1, I2S_
LRCLK1 and I2S_SD1, the first I2S signals are successively via the first USB port 02, the USB port of USB transmission line 03 and second
04 transmits to reception device 05 and decays to the 2nd I2S signals, and the 2nd I2S signals include I2S_MCL2, I2S_BCLK2, I2S_
LRCLK2 and I2S_SD2, because the 2nd I2S signals are asynchronous and distortion, the 5th resistance R5 and the first electric capacity C1 are to I2S_
MCL2 is cached, and the 6th resistance R6 and the second electric capacity C2 are cached to I2S_BCLK2, the 7th resistance R7 and the 3rd electric capacity C3
I2S_LRCLK2 is cached, the 8th resistance R8 and the 4th electric capacity C4 are cached to I2S_SD2, to realize the after caching
The synchronization of two I2S signals, the first triode Q1 carries out waveform to the I2S_MCL2 after caching and recovered to generate I2S_MCL3, second
Triode Q2 carries out waveform to the I2S_BCLK2 after caching and recovered to generate I2S_BCLK3, after the 3rd triode Q3 is to caching
I2S_LRCLK2 carries out waveform and recovered to generate I2S_LRCLK3, and the 4th triode Q4 carries out waveform to the I2S_SD2 after caching
Recover to generate I2S_SD3, I2S_MCL3, I2S_BCLK3, I2S_LRCLK3 and I2S_SD3 collectively constitute the 3rd I2S letters
Number；Wherein, the 3rd information that the 3rd I2S signals are carried is identical with the 3rd information that the first I2S signals are carried.
The 2nd I2S signals after caching can be realized by adjusting the RC real constants of cache module Zhong Mei roads buffer circuit
Synchronization.
In summary, in embodiments of the present invention, because I2S signal transmission systems include dispensing device, the first USB ends
Mouth, USB transmission line, the second USB port and reception device, reception device include transmission recovery module；Dispensing device sends the
One I2S signals, the first I2S signals transmit to reception via the first USB port, USB transmission line and the second USB port fill successively
Put and decay to the transmission recovery module in the 2nd I2S signals, reception device the 2nd I2S signals are forwarded, it is synchronous at
Reason or waveform recover to generate the 3rd I2S signals；Wherein, the 3rd information that the 3rd I2S signals are carried is carried with the first I2S signals
The first information it is identical；Therefore reduce the cost of I2S signal transmission systems and reduce the distorted signals in transmitting procedure.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all essences in the present invention
Any modifications, equivalent substitutions and improvements made within refreshing and principle etc., should be included in the scope of the protection.
Claims (9)
1. a kind of I2S signal transmission systems, it is characterised in that it includes dispensing device, the first USB port, USB transmission line,
Two USB ports and reception device, the reception device include transmission recovery module；
The dispensing device, the input/output terminal of first USB port, the USB transmission line, second USB port
The input of the transmission recovery module in input/output terminal and the reception device is sequentially connected；
The dispensing device sends the first I2S signals, and the first I2S signals are successively via first USB port, described
USB transmission line and second USB port transmit to the reception device and decay to the 2nd I2S signals, the reception dress
The transmission recovery module in putting is forwarded to the 2nd I2S signals, synchronization process or waveform are recovered to generate the 3rd
I2S signals；Wherein, the first information phase that the 3rd information that the 3rd I2S signals are carried is carried with the first I2S signals
Together.
2. I2S signal transmission systems as claimed in claim 1, it is characterised in that when the 2nd I2S signals are synchronous and do not lose
When true, the transmission recovery module is short circuit module；
The short circuit module is forwarded to generate the 3rd I2S signals to the 2nd I2S signals.
3. I2S signal transmission systems as claimed in claim 1, it is characterised in that when the 2nd I2S signals are asynchronous and not
During distortion, the transmission recovery module includes buffer module and short circuit module；
The output end of the buffer module is connected with the input of the short circuit module；
The buffer module synchronizes processing to the 2nd I2S signals, and the short circuit module is to described in after synchronization process
2nd I2S signals are forwarded to generate the 3rd I2S signals.
4. I2S signal transmission systems as claimed in claim 1, it is characterised in that when the 2nd I2S signals synchronization and distortion
When, the transmission recovery module includes short circuit module and waveform recovery module；
The output end of the short circuit module is connected with the input of the waveform recovery module；
The short circuit module is forwarded to the 2nd I2S signals, and the waveform recovery module is to described second after forwarding
I2S signals carry out waveform and recover to generate the 3rd I2S signals.
5. I2S signal transmission systems as claimed in claim 1, it is characterised in that when the 2nd I2S signals are asynchronous and lose
When true, the transmission recovery module includes buffer module and waveform recovery module；
The output end of the buffer module is connected with the input of the waveform recovery module；
The buffer module synchronizes processing to the 2nd I2S signals, after the waveform recovery module is to synchronization process
The 2nd I2S signals carry out waveform and recover to generate the 3rd I2S signals.
6. the I2S signal transmission systems as described in any one of claim 2 to 4, it is characterised in that the short circuit module includes the
One resistance, second resistance, 3rd resistor and the 4th resistance；
The first end of the first resistor is the first input end of the short circuit module, and the second end of the first resistor is described
First output end of short circuit module, the first end of the second resistance is the second input of the short circuit module, described second
Second end of resistance is the second output end of the short circuit module, and the first end of the 3rd resistor is the of the short circuit module
Three inputs, the second end of the 3rd resistor is the 3rd output end of the short circuit module, the first end of the 4th resistance
For the 4th input of the short circuit module, the second end of the 4th resistance is the 4th output end of the short circuit module；
4th input of the first input end of the short circuit module to the short circuit module constitutes the input of the short circuit module
End, the first output end of the short circuit module constitutes the output of the short circuit module to the 4th output end of the short circuit module
End.
7. the I2S signal transmission systems as described in any one of claim 3 or 5, it is characterised in that the buffer module includes the
One electric capacity, the second electric capacity, the 3rd electric capacity, the 4th electric capacity, the 5th resistance, the 6th resistance, the 7th resistance and the 8th resistance；
The first end of 5th resistance is the first input end of the buffer module, the second end and first of the 5th resistance
The first end of electric capacity is the first output end of the buffer module, and the first end of the 6th resistance is the of the buffer module
One input, the second end of the 6th resistance and the first end of the second electric capacity are the first output end of the buffer module, institute
The first end for stating the 7th resistance is the first input end of the buffer module, the second end of the 7th resistance and the 3rd electric capacity
First end is the first output end of the buffer module, and the first end of the 8th resistance inputs for the first of the buffer module
End, the second end of the 8th resistance and the first end of the 4th electric capacity are the first output end of the buffer module, described first
Second end of electric capacity, the second end of second electric capacity, the second of the second end of the 3rd electric capacity and the 4th electric capacity
End with being connected to power supply altogether；
The first input end of the buffer module constitutes the input of the buffer module to the 4th input of the buffer module
End, the 4th output end of the first output end to the buffer module of the buffer module constitutes the output of the buffer module
End.
8. the I2S signal transmission systems as described in any one of claim 4 or 5, it is characterised in that the waveform recovery module bag
Include the first triode, the second triode, the 3rd triode, the 4th triode, the 9th resistance, the tenth resistance, the 11st resistance,
12 resistance, the 13rd resistance, the 14th resistance, the 15th resistance and the 16th resistance；
The first input end of the extremely described waveform recovery module of transmitting of first triode, the current collection of first triode
The first end of pole and the 9th resistance be the waveform recovery module the first output end, the base stage of first triode with
The first end connection of tenth resistance, the second input of the extremely described waveform recovery module of transmitting of second triode
The first end of end, the colelctor electrode of second triode and the 11st resistance exports for the second of the waveform recovery module
End, the base stage of second triode is connected with the first end of the 12nd resistance, and the transmitting of the 3rd triode is extremely
3rd input of the waveform recovery module, the colelctor electrode of the 3rd triode and the first end of the 13rd resistance are
3rd output end of the waveform recovery module, the base stage of the 3rd triode connects with the first end of the 14th resistance
Connect, the 4th input of the extremely described waveform recovery module of transmitting of the 4th triode, the current collection of the 4th triode
The first end of pole and the 15th resistance is the 4th output end of the waveform recovery module, the base stage of the 4th triode
It is connected with the first end of the 16th resistance, the second end of the 9th resistance, the second end of the tenth resistance, described
Second end of 11 resistance, the second end of the 12nd resistance, the second end of the 13rd resistance, the 14th resistance
The second end, the second end of the 15th resistance and the second end of the 16th resistance be connected with the first power supply；
It is extensive that the first input end of the waveform recovery module to the 4th input of the waveform recovery module constitutes the waveform
The input of multiple module, the 4th output end of the first output end to the waveform recovery module of the waveform recovery module is constituted
The output end of the waveform recovery module.
9. I2S signal transmission systems as claimed in claim 1, it is characterised in that first USB port and the 2nd USB ends
Mouth is USB3.0 ports；
The power end of the USB3.0 ports is connected with second source, and the USB2.0 data negative pole end of the USB3.0 ports is institute
The first input/output terminal of USB3.0 ports is stated, the USB2.0 data positive terminal of the USB3.0 ports is the USB3.0 ports
The second input/output terminal, the high speeds of the USB3.0 ports receives threeth input of the data negative pole end for the USB3.0 ports
Output end, the high speed of the USB3.0 ports receives the 4th input/output terminal that data positive terminal is the USB3.0 ports, institute
The high speed for stating USB3.0 ports sends the 5th input/output terminal that data negative pole end is the USB3.0 ports, the USB3.0 ends
The high speed of mouth sends the 6th input/output terminal that data positive terminal is the USB3.0 ports, the earth terminal of the USB3.0 ports
With the feedback signal earth terminal of the USB3.0 ports with being connected to power supply altogether；
3rd input/output terminal of the USB3.0 ports to the 6th input/output terminal of the USB3.0 ports collectively forms institute
State the input/output terminal of USB3.0 ports.
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| CN201710586535.5A CN107329731A (en) | 2017-07-18 | 2017-07-18 | A kind of I2S signal transmission systems |
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