CN107329073B - A kind of double time domain dynamic frequency-conversion test methods - Google Patents
A kind of double time domain dynamic frequency-conversion test methods Download PDFInfo
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- CN107329073B CN107329073B CN201710641641.9A CN201710641641A CN107329073B CN 107329073 B CN107329073 B CN 107329073B CN 201710641641 A CN201710641641 A CN 201710641641A CN 107329073 B CN107329073 B CN 107329073B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2601—Apparatus or methods therefor
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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Abstract
The present invention proposes a kind of double time domain dynamic frequency-conversion test methods, including the following steps: the reference frequency that low speed is used on ATE, as communication frequency；It is configured on ATE by PLL circuit of the BIST circuit to chip interior, generates and obtain high-frequency signal；The number of external clock waiting time synchronous with inner high speed clock and inner high speed instruction operation are obtained by calculating；It can be detected the result of current internal high speed clock domain instruction operation after clock domain synchronizes when inside and outside；By constantly changing PLL setting in external clock domain, the frequency conversion to internal high-speed time domain is realized, until detecting greatest limit frequency.Double time domain dynamic frequency-conversion test methods proposed by the present invention are realized under high-speed chip converting operation, the test using peripheral low speed ATE to its performance.
Description
Technical field
The present invention relates to test of semiconductor integrated circuit fields, and in particular to a kind of double time domain dynamic frequency-conversions test side
Method.
Background technique
Semiconductor automation test macro (ATE) is produced for detecting the integrality of integrated circuit function for integrated circuit
The last process of manufacture, to ensure the quality of the integrated circuit manufacturing.Existing semiconductor automation test macro (ATE) is logical
It is, by the level signal on input and output pin, to read and write number after carrying out addressing for memory under test chip with working principle
According to the comparator inside test machine, the test process of desired value and the result of actual measurement logical value acquisition PASS/FAIL is compared.
Chip speed is continuously improved, and ATE is limited by the factors such as equipment limit and probe card lead cannot achieve high speed survey
Examination.BIST (built-in self-test) is to be implanted into related functional circuits in circuit in design for providing the skill of selftest function
Art reduces device detection to the degree of dependence of automatic test equipment (ATE) with this.However use BIST mode exist again it is external and
The limitation that internal clocking is asynchronous, internal actual frequency is unknowable.It accurately to obtain internal operation frequency and detect internal electricity
Road limit running frequency has certain difficulty.
Summary of the invention
The present invention proposes a kind of double time domain dynamic frequency-conversion test methods, realizes the upconversion operation of chip interior high-speed time domain,
The final characteristic for obtaining chip interior limiting frequency.
In order to achieve the above object, the present invention proposes a kind of double time domain dynamic frequency-conversion test methods, including the following steps:
The reference frequency that low speed is used on ATE, as communication frequency；
It is configured on ATE by PLL circuit of the BIST circuit to chip interior, generates and obtain high-frequency signal；
External clock waiting time synchronous with inner high speed clock and inner high speed instruction operation are obtained by calculating
Number；
It can be detected the result of current internal high speed clock domain instruction operation after clock domain synchronizes when inside and outside；
By constantly changing PLL setting in external clock domain, the frequency conversion to internal high-speed time domain is realized, until detecting most
Big limiting frequency.
Further, the acquisition PLL circuit high-frequency signal is to carry out by the following method: to PLL circuit output signal
It by scaling down processing and is tested, obtains the practical high frequency output signal of PLL circuit.
Further, the clock number that this method is instructed according to the internal frequency and internal operation of acquisition, with external low speed
Reference frequency calculates least common multiple, and obtains external clock waiting synchronous with inner high speed clock according to the common multiple
The number of time and inner high speed instruction operation.
Further, this method further includes the synchronization time by finely tuning least common multiple, eliminate after internal PLL output by
The internal frequency deviation caused by load jitter reason, it is final to obtain internal accurate running frequency.
Double time domain dynamic frequency-conversion test methods proposed by the present invention are realized under high-speed chip converting operation, low using periphery
Test of the fast ATE to its performance.Implementation method is communicated using external low-speed clock domain, and chip interior pll clock is set
Frequency, detected by peripheral frequency obtain it is internal should actually add frequency, then by periphery ATE precompute lower frequency region and
High-frequency domain is used as the synchronous waiting time in the least common multiple of operation project, when realizing external low speed time domain and inner high speed with this
The synchronization in domain realizes the change of chip interior high-speed time domain then by constantly changing setting of the low speed time domain instruction to PLL frequency
Frequency operates, the final characteristic for obtaining chip interior limiting frequency.
Detailed description of the invention
Fig. 1 show double time domain dynamic frequency-conversion test method flow charts of present pre-ferred embodiments.
Fig. 2 show the chip system circuit diagram of present pre-ferred embodiments.
Fig. 3 show the frequency conversion test philosophy schematic diagram of present pre-ferred embodiments.
Specific embodiment
A specific embodiment of the invention is provided below in conjunction with attached drawing, but the present invention is not limited to the following embodiments and the accompanying drawings.Root
According to following explanation and claims, advantages and features of the invention will be become apparent from.It should be noted that attached drawing be all made of it is very simple
The form of change and use non-accurate ratio, be only used for conveniently, lucidly aid in illustrating the embodiment of the present invention purpose.
Referring to FIG. 1, Fig. 1 show double time domain dynamic frequency-conversion test method flow charts of present pre-ferred embodiments.This
Invention proposes a kind of double time domain dynamic frequency-conversion test methods, including the following steps:
Step S100: the reference frequency of low speed is used on ATE, as communication frequency；
Step S200: it is configured on ATE by PLL circuit of the BIST circuit to chip interior, generates and obtain height
Frequency signal；
Step S300: the external clock waiting time synchronous with inner high speed clock is obtained by calculating, and internal high
The number of speed instruction operation；
Step S400: it can be detected the knot of current internal high speed clock domain instruction operation after clock domain synchronizes when inside and outside
Fruit；
Step S500: by constantly changing PLL setting in external clock domain, the frequency conversion to internal high-speed time domain is realized, directly
To detecting greatest limit frequency.
Preferred embodiment according to the present invention, the acquisition PLL circuit high-frequency signal are to carry out by the following method: to PLL
Circuit output signal is by scaling down processing and is tested, and the practical high frequency output signal of PLL circuit is obtained.
The clock number that this method is instructed according to the internal frequency and internal operation of acquisition, with external low-speed reference frequency meter
Least common multiple is calculated, and the external clock waiting time synchronous with inner high speed clock is obtained according to the common multiple, and
The number of inner high speed instruction operation.
This method further includes the synchronization time by finely tuning least common multiple, is trembled after eliminating internal PLL output due to loading
Internal frequency deviation caused by dynamic reason, it is final to obtain internal accurate running frequency.
Fig. 2 show the chip system circuit diagram of present pre-ferred embodiments, and Fig. 3 show present pre-ferred embodiments
Frequency conversion test philosophy schematic diagram.Each high-speed chip is connect by BIST circuit with periphery low-frequency time-domain in Fig. 2, when external low speed
Clock is set by BIST circuit of the address data (D) clock (TCK) (ADR) to each tested circuit, is then posted PLL
Storage is set, and so that PLL is generated the clock signal of high frequency on CLK_PLL, other circuit-under-tests are then under CLK_PLL time domain
Carry out high-speed cruising.
The high frequency clock that PLL generates internal operation is arranged in ATE, obtains the practical frequency generated of PLL by PLL interface,
According to the relationship of the length of circuit-under-test instruction operation and external low frequency clock, when calculating the synchronous waiting of least common multiple
Between.The signal that test result latches occurs in this time ATE, while the chip of inner high speed operation also feeds back the knot of internal operation
Fruit is put into BIST test result memory.If the pass result for not obtaining internal operation is latched in outside, illustrate that internal clocking is transported
Row is slower than anticipation or internal circuit can not work normally under current clock frequency.Adjustment PLL is set for frequency scanning, weight
Multiple above-mentioned movement can be obtained the highest frequency of internal operation until detecting pass result.When pass result can not be scanned
When, the clock edge of also fine-tuning test latch signal detects that PLL generates the deviation between clock and internal circuit operation clock.
In conclusion double time domain dynamic frequency-conversion test methods proposed by the present invention, realize under high-speed chip converting operation, adopt
Test with peripheral low speed ATE to its performance.Implementation method is communicated using external low-speed clock domain, and chip interior is set
The frequency of pll clock, frequency should actually be added by detecting acquisition inside by peripheral frequency, then be precomputed by periphery ATE
Lower frequency region and high-frequency domain are used as the synchronous waiting time in the least common multiple of operation project, with this realize external low speed time domain with it is interior
The synchronization of portion's high-speed time domain realizes chip interior high speed then by constantly changing setting of the low speed time domain instruction to PLL frequency
The upconversion operation of time domain, the final characteristic for obtaining chip interior limiting frequency.
Although the present invention has been disclosed as a preferred embodiment, however, it is not to limit the invention.Skill belonging to the present invention
Has usually intellectual in art field, without departing from the spirit and scope of the present invention, when can be used for a variety of modifications and variations.Cause
This, the scope of protection of the present invention is defined by those of the claims.
Claims (3)
1. a kind of double time domain dynamic frequency-conversion test methods, characterized in that it comprises the following steps:
The reference frequency that low speed is used on ATE, as communication frequency；
It is configured on ATE by PLL circuit of the BIST circuit to chip interior, generates and obtain high-frequency signal；
Time of external clock waiting time synchronous with inner high speed clock and inner high speed instruction operation are obtained by calculating
Number calculates minimum public affairs with external low-speed reference frequency according to the clock number that the internal frequency of acquisition and internal operation instruct
Multiple, and referred to according to common multiple acquisition external clock waiting time synchronous with inner high speed clock and inner high speed
Enable the number of operation；
It can be detected the result of current internal high speed clock domain instruction operation after clock domain synchronizes when inside and outside；
By constantly changing PLL setting in external clock domain, the frequency conversion to internal high-speed time domain is realized, until detecting maximum pole
Frequency limit rate.
2. double time domain dynamic frequency-conversion test methods according to claim 1, which is characterized in that the acquisition PLL circuit is high
Frequency signal is to carry out by the following method: passing through scaling down processing to PLL circuit output signal and tests, obtains PLL circuit
Practical high frequency output signal.
3. double time domain dynamic frequency-conversion test methods according to claim 2, which is characterized in that this method further includes by micro-
The synchronization time of least common multiple is adjusted, internal frequency deviation caused by eliminating after internal PLL output due to load jitter, most
Internal accurate running frequency is obtained eventually.
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| CN109032023B (en) * | 2018-08-08 | 2021-03-09 | 上海精密计量测试研究所 | Built-in self-test method for DCM and PLL in FPGA |
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| CN1281294A (en) * | 1999-07-19 | 2001-01-24 | 三菱电机株式会社 | Clock forming circuit |
| CN1756080A (en) * | 2004-09-28 | 2006-04-05 | 富士通株式会社 | Semiconductor integrated circuit |
| CN101499798A (en) * | 2009-02-24 | 2009-08-05 | 华为技术有限公司 | Method and apparatus for controlling phase synchronization and system for implementing phase synchronization |
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| US4890270A (en) * | 1988-04-08 | 1989-12-26 | Sun Microsystems | Method and apparatus for measuring the speed of an integrated circuit device |
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| CN1281294A (en) * | 1999-07-19 | 2001-01-24 | 三菱电机株式会社 | Clock forming circuit |
| CN1756080A (en) * | 2004-09-28 | 2006-04-05 | 富士通株式会社 | Semiconductor integrated circuit |
| CN101499798A (en) * | 2009-02-24 | 2009-08-05 | 华为技术有限公司 | Method and apparatus for controlling phase synchronization and system for implementing phase synchronization |
| CN102142836A (en) * | 2010-01-28 | 2011-08-03 | 日本电波工业株式会社 | PLL oscillator circuit |
| CN102567168A (en) * | 2010-12-27 | 2012-07-11 | 北京国睿中数科技股份有限公司 | BIST (Built-in Self-test) automatic test circuit and test method aiming at PHY (Physical Layer) high-speed interface circuit |
| CN104459395A (en) * | 2014-12-04 | 2015-03-25 | 中国电子科技集团公司第四十一研究所 | Calibration frequency mixer scaling method based on time-frequency double domains |
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