CN107317576A - A kind of eight phase rotatory current circuits for Hall sensor - Google Patents

A kind of eight phase rotatory current circuits for Hall sensor Download PDF

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Publication number
CN107317576A
CN107317576A CN201710376518.9A CN201710376518A CN107317576A CN 107317576 A CN107317576 A CN 107317576A CN 201710376518 A CN201710376518 A CN 201710376518A CN 107317576 A CN107317576 A CN 107317576A
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ports
current
hall
signal
nmos tube
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CN107317576B (en
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徐跃
李鼎
赵庭晨
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Nanjing Post and Telecommunication University
Nanjing University of Posts and Telecommunications
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Nanjing Post and Telecommunication University
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/017509—Interface arrangements

Abstract

A kind of eight phase rotatory current circuits for Hall sensor, the invention discloses a kind of eight phase rotatory current circuits based on current output mode and its dynamic imbalance removing method.Eight phase rotatory current circuits are made up of 32 NMOS tubes, wherein the output polarity in the direction, in addition 16 size identical NMOS tube control hall signals and misalignment signal of 16 size identical NMOS tube control bias current inputs and output.The octal hall device of 45 ° of rotational symmetry structures carries out the operation of eight phase rotatory currents, the misalignment signal that the constant hall signal of output polarity and polarity change under the control of eight phase sequence clocks.Dynamic offset canceling scheme proposed by the present invention is simple, circuit is easily achieved, the misalignment signal and the constant hall signal of polarity changed using output polarity in eight phase rotatory current modulated process, amplified by follow-up current integration, sampling/holding and phase reducing, the imbalance of hall device can be effectively eliminated, low-down residual offset can be obtained.

Description

A kind of eight phase rotatory current circuits for Hall sensor
Technical field
The invention belongs to magnetic sensor technologies field, and in particular to a kind of eight phase rotatory currents electricity for Hall sensor Road and dynamic imbalance removing method, can make Hall sensor obtain low-down residual offset.
Background technology
Hall magnetic field sensor is a kind of magnetoelectric conversion element based on Hall effect, and CMOS integrated hall sensorses are because of it Small volume, cost be low, low in energy consumption, response fast, strong antijamming capability many advantages, such as, in Industry Control, automotive electronics, logical The various fields such as news, medical treatment and instrument manufacturing are applied widely.But CMOS integrated hall sensorses have magnetic field The serious problems that sensitivity is low and imbalance is high.Domain alignment error, device active region ion implanting cause during hall device photoetching Carrier Profile is uneven, piezoresistive effect, the junction field effect of PN junction caused by encapsulation stress etc. are to cause CMOS hall devices to lose The main cause heightened.Under low magnetic field conditions, the Hall voltage of CMOS hall devices output is typically smaller than 1mV, and Hall device Part imbalance may but be up to several mV to tens mV, and high misalignment signal floods faint hall signal, so that follow-up letter Number modulate circuit is difficult to amplify hall signal.In order to eliminate imbalance and the low-frequency noise of hall device, generally using dynamic rotation Turn current technique.Wide variety of dynamic offset cancellation circuit is based on traditional two-phase rotatory current technology, but two-phase electric rotating The effect that Flow Technique eliminates Hall imbalance is undesirable, and residual offset is larger, causes the magnetic field resolution ratio of Hall sensor not high enough, It is difficult to meet high accuracy, high-resolution detection of magnetic field requirement, it is therefore necessary to use four phases and eight phase rotatory current technologies.
Compared to four phase rotatory current technologies, eight phase rotatory current technologies carry out on 8 symmetry directions of hall device Rotatory current is operated, and the effect for eliminating hall device imbalance more preferably, can obtain lower residual offset, but eight phase rotatory currents The sequential and circuit structure of circuit are more complicated.On the other hand, the modulation and demodulation technology of eight phase rotatory currents is also immature, no The change in polarity feature of hall signal and misalignment signal during eight phase rotatory currents can be made full use of farthest to eliminate The imbalance of hall device and amplifying circuit.In addition, the mode of operation that hall device is generally exported using Hall voltage, but it is this The offset cancellation circuit of voltage mode is highly susceptible to the influence of parasitic capacitance effect and introduces very big noise and interference, so that Reduce the signal to noise ratio of Hall sensor.
The content of the invention
The present invention is directed to above-mentioned the deficiencies in the prior art, it is proposed that a kind of eight phase rotatory currents based on current output mode Circuit and its dynamic imbalance removing method.Eight phase rotatory current circuits are under eight phase sequence clock controls by 45 ° of rotations pair The octal hall device of structure is claimed to carry out the operation of eight phase rotatory currents, the constant Hall current signal of output polarity and change in polarity Misalignment signal.Then the Hall current of eight phase rotatory current circuit outputs and offset current aliasing signal are sent into current integration Amplifier, sampling/retainer, subtracter and low pass filter, the final imbalance for eliminating hall device and low-frequency noise, are obtained non- Often low residual offset.
To achieve the above object, the technical solution used in the present invention is a kind of eight phase electric rotatings for Hall sensor Current circuit, the circuit includes 32 NMOS tube M1~M32, octal hall device, clock signal clk1~clk8, bias current sources And outside port, wherein M1~M8 is control bias current IbiasThe switching tube of octal hall device is flowed into, M9~M16 is control Bias current IbiasThe switching tube of octal hall device is flowed out, M17~M24 flows into outer for control hall device current output signal Portion port Io1Switching tube, M25~M32 flows into outside port I for control hall device current output signalo2Switching tube, NMOS tube M1~M8 drain electrode is connected to input bias current source I jointlyb1Output end, NMOS tube M1~M8 grid is respectively successively It is connected to clock signal clk1~clk8, NMOS tube M1~M8 source electrode connects a ports, b ports, c of octal hall device successively respectively Port, d ports, e ports, f ports, g ports, h ports；NMOS tube M9~M16 source electrode is connected to output bias current source jointly Ib2Input, NMOS tube M9~M16 grid is connected to clock signal clk successively respectively1~clk8, NMOS tube M9~M16's Drain electrode is connected to e ports, f ports, g ports, h ports, a ports, b ports, c ports, the d ends of octal hall device successively respectively Mouthful；NMOS tube M17~M24 source electrode is connected to outside port I jointlyo1, when NMOS tube M17~M24 grid is connected to successively respectively Clock signal clk1~clk8, NMOS tube M17~M24 drain electrode is connected to the c ports, d ports, e ends of octal hall device successively respectively Mouth, f ports, g ports, h ports, a ports, b ports；NMOS tube M25~M32 source electrode is connected to outside port I jointlyo2, NMOS Pipe M25~M32 grid is connected to clock signal clk successively respectively1~clk8, NMOS tube M25~M32 drain electrode connects successively respectively To the g ports of octal hall device, h ports, a ports, b ports, c ports, d ports, e ports, f ports；All 32 NMOS Pipe M1~M32 Substrate ground, two bias current sources Ib1And Ib2It is equal there is provided bias current size be Ibias, it is ensured that The bias current for flowing in and out octal hall device is equal.
Further, 8 ports of above-mentioned octal hall device are 45 ° of rotational symmetry structures.
Further, above-mentioned clock clk1~clk8For eight phase sequence clock signals, carry out eight by octal hall device and mutually revolve Turn the constant Hall current signal of output polarity after current practice and the misalignment signal of change in polarity.
The present invention is it is further proposed that a kind of utilize the above-mentioned eight phase rotatory current circuits for Hall sensor to enter action The removing method of state imbalance, is specifically comprised the steps of：
S1：The differential current signal I of eight phase rotatory current circuit outputso1And Io2Send into current integration amplifier and carry out electricity Flow to the differential voltage signal V of the conversion of voltage, output aliasing Hall voltage and offset voltageo1And Vo2；
S2：During eight phase rotatory currents are operated, the differential voltage signal of current integration amplifier output is respectively Vo1= 8Vh+Vop1+Vop3+Vop5+Vop7, Vo2=Vop2+Vop4+Vop6+Vop8, wherein VhFor Hall current IhExported by integral amplifier Hall voltage signal, and Vop1~Vop8For eight phase Hall offset current Iop1~Iop8The offset voltage exported by integral amplifier Signal；
S3：The differential voltage signal of current integration amplifier output is through over-sampling, and/retainer sample/is sent again after keeping Enter subtracter and carry out phase reducing, the signal of subtracter output is Vout=Vo1-Vo2=8Vh+(Vop1+Vop3+Vop5+Vop7-Vop2- Vop4-Vop6-Vop8)；
S4：Obtained Hall voltage filters out high frequency harmonic components by low pass filter again, after final output amplification suddenly That voltage signal, misalignment signal is effectively eliminated, and obtains low-down residual offset voltage △ Vop=Vop1+Vop3+Vop5+Vop7- Vop2-Vop4-Vop6-Vop8。
The present invention is primarily present following advantage relative to the tradition imbalance removing method of Hall sensor：
1st, dynamic offset canceling scheme proposed by the present invention is simple, and circuit is easily achieved, and utilizes eight phase rotatory currents Output polarity changes in modulated process misalignment signal and the constant hall signal of polarity, are amplified by follow-up current integration, Sampling/holding and phase reducing, can effectively eliminate the imbalance of hall device, can obtain low-down residual offset.
2nd, the present invention is operated using the rotatory current of current-mode, and the Hall current of output is integrated amplification, can obtained Very strong antijamming capability and low power consumption.
3rd, the big I of Hall voltage that the present invention is exported is adjusted by current integration amplifier and subtraction device, with very big spirit Activity.
Brief description of the drawings
Fig. 1 is the eight phase rotatory current operating principle schematic diagrames proposed by the present invention based on current output mode.
Description of reference numerals：A, b, c, d, e, f, g, h represent a ports of octal hall device, b ports, c ports d respectively Port, e ports, f ports, g ports and h ports.
Fig. 2 is the octal hall device structural representation with 45 ° of rotational symmetry structures.
Description of reference numerals：A, b, c, d, e, f, g, h represent a ports of octal hall device, b ports, c ports d respectively Port, e ports, f ports, g ports and h ports.
Fig. 3 is the eight phase rotatory current circuit theory diagrams based on current output mode.
Fig. 4 is clock signal figure and output Hall current signal and the imbalance of eight phase rotatory current circuits shown in Fig. 3 Current signal schematic diagram.
Fig. 5 is the dynamic imbalance removing method schematic diagram based on eight phase rotatory current technologies.
Description of reference numerals：A, b, c, d, e, f, g, h represent a ports of octal hall device, b ports, c ports d respectively Port, e ports, f ports, g ports and h ports.
Fig. 6 is the clock signal figure of the eight phase rotatory currents imbalance removing method shown in Fig. 5.
Embodiment
Patent of the present invention is described in further detail in conjunction with Figure of description.
A kind of eight phase rotatory current circuits based on current output mode proposed by the present invention, its operation principle such as Fig. 1 institutes Show.Octal hall device is operated under current output mode, i.e. bias current IbiasFrom an input port stream of hall device Enter, then flowed out again from another output port parallel with input port.Octal hall device two other and input port Perpendicular output port output difference current signal, the differential current signal is Hall current and offset current aliasing signal. The structural representation of octal hall device is as shown in Figure 2.The octal hall device has 45 ° of rotational symmetry structures, with positive eight The N traps or deep N-well of side shape are as the active area of hall device, and 8 N+ contact holes are distributed in the edge of octagon N traps, adjacent Angle between two contact hole centers is 45 °.The center surface of octagon N traps covers the P+ injections of one layer of octagon Layer, for reducing the compound of N trap surface carriers, so as to reduce the noise of hall device.When carrying out the first phase rotatory current, Bias current IbiasFirst flow into, then flowed out again from e ports, hall device c ports and g ports are defeated from a ports of hall device Go out current signal and be coupled with outside port Io1And Io2；When carrying out the second phase rotatory current, bias current IbiasFirst from Hall Device b ports are flowed into, and are then flowed out again from f ports, hall device d ports and h ports output current signal are coupled with outside Port Io1And Io2；When carrying out third phase rotatory current, bias current IbiasFirst flowed into from hall device c ports, then again from g Port is flowed out, and hall device e ports and a ports output current signal are coupled with outside port Io1And Io2；When the 4th phase of progress During rotatory current, bias current IbiasFirst flow into, then flowed out again from h ports, hall device f ports from hall device d ports Outside port I is coupled with b ports output current signalo1And Io2；When carrying out the 5th phase rotatory current, bias current Ibias First flow into, then flowed out again from a ports from hall device e ports, hall device g ports and c ports output current signal difference It is connected to outside port Io1And Io2；When carrying out the 6th phase rotatory current, bias current IbiasFirst flowed into from hall device f ports, Then flowed out again from b ports, hall device h ports and d ports output current signal are coupled with outside port Io1And Io2；When When carrying out the 7th phase rotatory current, bias current IbiasFirst flow into, then flowed out again from c ports, Hall from hall device g ports Device a ports and e ports output current signal are coupled with outside port Io1And Io2；When carrying out the 8th phase rotatory current, partially Put electric current IbiasFirst flow into, then flowed out again from d ports from hall device h ports, hall device b ports and f ports output electricity Stream signal is coupled with outside port Io1And Io2。
The eight phase rotatory current operating principle figures based on current output mode according to Fig. 1, base proposed by the present invention In current output mode eight phase rotatory current circuit theory diagrams as shown in figure 3, Fig. 4 be Fig. 3 in clock control signal figure with And output Hall current signal and offset current signal schematic representation.
Eight phases rotatory current circuit structure proposed by the present invention is as described below：It is made up of 32 NMOS tube M1~M32, wherein M1~M8 is control bias current IbiasThe switching tube of octal hall device is flowed into, M9~M16 is control bias current IbiasOutflow The switching tube of octal hall device, M17~M24 flows into outside port I for control hall device current output signalo1Switch Pipe, and M25~M32 flows into outside port I for control hall device current output signalo2Switching tube.NMOS tube M1~M8's Drain electrode is connected to input bias current source I jointlyb1Output end, NMOS tube M1~M8 grid is connected to clock signal successively respectively clk1~clk8, NMOS tube M1~M8 source electrode meets a ports of octal hall device, b ports, c ports, d ports, e successively respectively Port, f ports, g ports, h ports；NMOS tube M9~M16 source electrode is connected to output bias current source I jointlyb2Input, NMOS tube M9~M16 grid is connected to clock signal clk successively respectively1~clk8, NMOS tube M9~M16 drain electrode difference is successively It is connected to e ports, f ports, g ports, h ports, a ports, b ports, c ports, the d ports of octal hall device；NMOS tube M17~ M24 source electrode is connected to outside port I jointlyo1, NMOS tube M17~M24 grid is connected to clock signal clk successively respectively1~ clk8, NMOS tube M17~M24 drain electrode is connected to the c ports of octal hall device, d ports, e ports, f ports, g successively respectively Port, h ports, a ports, b ports；NMOS tube M25~M32 source electrode is connected to outside port I jointlyo2, NMOS tube M25~M32 Grid be connected to clock signal clk successively respectively1~clk8, NMOS tube M25~M32 drain electrode is connected to octal Hall successively respectively G ports, h ports, a ports, b ports, c ports, d ports, e ports, the f ports of device；All 32 NMOS tubes M1~M32's Substrate ground.Two bias current sources Ib1And Ib2It is equal there is provided bias current size be Ibias, it is ensured that flow in and out eight The bias current of hole hall device is equal.
The operation principle of eight phase rotatory current circuits is as described below：As clock signal clk1High level and remaining clock signal During low level, NMOS tube M1, M9, M17 and M25 conducting, the cut-off of remaining NMOS tube.Bias current sources Ib1The bias current of outflow IbiasThe a ports of hall device are flowed into by nmos switch pipe M1, then bias current IbiasAgain from the e port flows of hall device Go out, bias current sources I is flowed into by nmos switch pipe M9b2.The current signal of hall device port c outputs passes through nmos switch pipe M17 is connected to outside port Io1, and the current signal of hall device port g outputs is connected to outside port by nmos switch pipe M25 Io2；As clock signal clk2High level and during remaining clock signal low level, NMOS tube M2, M10, M18 and M26 conducting, remaining NMOS tube is ended.Bias current sources Ib1The bias current I of outflowbiasThe b ports of hall device are flowed into by nmos switch pipe M2, Then bias current IbiasFlowed out again from the f ports of hall device, bias current sources I is flowed into by nmos switch pipe M10b2.Suddenly You are connected to outside port I by the current signal of device interface d outputs by nmos switch pipe M18o1, and hall device port h is exported Current signal be connected to outside port I by nmos switch pipe M26o2；As clock signal clk3High level and remaining clock signal During low level, NMOS tube M3, M11, M19 and M27 conducting, the cut-off of remaining NMOS tube.Bias current sources Ib1The bias current of outflow IbiasThe c ports of hall device are flowed into by nmos switch pipe M3, then bias current IbiasAgain from the g port flows of hall device Go out, bias current sources I is flowed into by nmos switch pipe M11b2.The current signal of hall device port e outputs passes through nmos switch Pipe M19 is connected to outside port Io1, and the current signal of hall device port a outputs is connected to outer end by nmos switch pipe M27 Mouth Io2；As clock signal clk4High level and during remaining clock signal low level, NMOS tube M4, M12, M20 and M28 conducting, its Remaining NMOS tube cut-off.Bias current sources Ib1The bias current I of outflowbiasThe d ends of hall device are flowed into by nmos switch pipe M4 Mouthful, then bias current IbiasFlowed out again from the h ports of hall device, bias current sources I is flowed into by nmos switch pipe M12b2。 The current signal of hall device port f outputs is connected to outside port I by nmos switch pipe M20o1, and hall device port b is defeated The current signal gone out is connected to outside port I by nmos switch pipe M28o2；As clock signal clk5High level and remaining clock are believed During number low level, NMOS tube M5, M13, M21 and M29 conducting, the cut-off of remaining NMOS tube.Bias current sources Ib1The biased electrical of outflow Flow IbiasThe e ports of hall device are flowed into by nmos switch pipe M5, then bias current IbiasAgain from a ports of hall device Outflow, bias current sources I is flowed into by nmos switch pipe M13b2.The current signal of hall device port g outputs is opened by NMOS Close pipe M21 and be connected to outside port Io1, and the current signal of hall device port c outputs is connected to outside by nmos switch pipe M29 Port Io2；As clock signal clk6High level and during remaining clock signal low level, NMOS tube M6, M14, M22 and M30 conducting, Remaining NMOS tube is ended.Bias current sources Ib1The bias current I of outflowbiasThe f of hall device is flowed into by nmos switch pipe M6 Port, then bias current IbiasFlowed out again from the b ports of hall device, bias current sources are flowed into by nmos switch pipe M14 Ib2.The current signal of hall device port h outputs is connected to outside port I by nmos switch pipe M22o1, and hall device port The current signal of d outputs is connected to outside port I by nmos switch pipe M30o2；As clock signal clk7High level and remaining clock During signal low level, NMOS tube M7, M15, M23 and M31 conducting, the cut-off of remaining NMOS tube.Bias current sources Ib1The biasing of outflow Electric current IbiasThe g ports of hall device are flowed into by nmos switch pipe M7, then bias current IbiasAgain from the c ends of hall device Mouth outflow, bias current sources I is flowed into by nmos switch pipe M15b2.The current signal of hall device port a outputs passes through NMOS Switching tube M23 is connected to outside port Io1, and the current signal of hall device port e outputs is connected to outer by nmos switch pipe M31 Portion port Io2；As clock signal clk8High level and during remaining clock signal low level, NMOS tube M8, M16, M24 and M32 are led It is logical, the cut-off of remaining NMOS tube.Bias current sources Ib1The bias current I of outflowbiasHall device is flowed into by nmos switch pipe M8 H ports, then bias current IbiasFlowed out again from the d ports of hall device, bias current is flowed into by nmos switch pipe M16 Source Ib2.The current signal of hall device port b outputs is connected to outside port I by nmos switch pipe M24o1, and hall device end The current signal of mouth f outputs is connected to outside port I by nmos switch pipe M32o2.Outside port Io1And Io2The electricity of difference output Stream signal is Hall current IhWith offset current IopAliasing signal be Io1-Io2=Ih+Iop.Eight are carried out to octal hall device During phase rotatory current is operated, Hall current signal IhPolarity remain constant, and offset current Iop1~Iop8Polarity Change with clock signal generating period.
The present invention also proposes the dynamically imbalance removing method of the eight phase rotatory currents based on current-mode, and Fig. 5 mutually rotates for eight The dynamic imbalance removing method schematic diagram of current technique, Fig. 6 is the clock signal figure needed for Fig. 5.Eight based on current-mode The dynamic imbalance removing method of phase rotatory current is as described below：The differential current signal I of eight phase rotatory current circuit outputso1With Io2Send into current integration amplifier and carry out electric current to the conversion of voltage, export the differential voltage of aliasing Hall voltage and offset voltage Signal Vo1And Vo2.During eight phase rotatory currents are operated, the differential voltage signal of current integration amplifier output is respectively Vo1= 8Vh+Vop1+Vop3+Vop5+Vop7, and Vo2=Vop2+Vop4+Vop6+Vop8.Wherein VhFor Hall current IhExported by integral amplifier Hall voltage signal, and Vop1~Vop8For eight phase Hall offset current Iop1~Iop8The imbalance electricity exported by integral amplifier Press signal.The differential voltage signal of current integration amplifier output is through over-sampling, and/retainer sample/is re-fed into after keeping and subtracted Musical instruments used in a Buddhist or Taoist mass carries out phase reducing, and the signal of subtracter output is Vout=Vo1-Vo2=8Vh+(Vop1+Vop3+Vop5+Vop7-Vop2-Vop4- Vop6-Vop8).The Hall voltage finally obtained filters out high frequency harmonic components by low pass filter again, after final output amplification Hall voltage signal, and misalignment signal is effectively eliminated, and obtains low-down residual offset voltage △ Vop=Vop1+Vop3+Vop5+ Vop7-Vop2-Vop4-Vop6-Vop8。
Specific method is illustrated in conjunction with accompanying drawing：As clock signal clkSFor between high period, eight phase sequence clocks clk1~clk8High level is followed successively by, so as to control eight phase rotatory current circuits to carry out rotatory current operation, eight phase rotatory currents electricity The differential current signal I of road outputo1And Io2Send into current integration amplifier.In clock signal clkSFor between high period, electric current NMOS tube switch M1 and M2 conductings in integral amplifier, and NMOS tube switchs M3 and M4 because of clock signal clkRCut for low level Only.Then current integration amplifier carries out electric current to input current to the conversion of voltage, and the differential voltage of output is respectively Vo1= 8Vh+Vop1+Vop3+Vop5+Vop7, and Vo2=Vop2+Vop4+Vop6+Vop8.Wherein VhFor Hall current IhExported by integral amplifier Hall voltage signal, and Vop1~Vop8For eight phase Hall offset current Iop1~Iop8The imbalance electricity exported by integral amplifier Press signal.As clock signal clkSWhen being changed into low level, NMOS tube switch M1 and M2 cut-offs in current integration amplifier, eight mutually revolve The electric current for turning current circuit output is not re-fed into current integration amplifier.Now, eight phase sequence clock clk1~clk8It is low electricity Flat, eight phase rotatory current circuits also no longer carry out rotatory current operation.In signal clkSIt is changed into after low level, sampling/retainer Clock signal clkS/HFirst it is changed into high level, now NMOS tube switch M5 and M6 conductings in sampling/retainer, to current integration The differential voltage V of amplifier outputo1And Vo2Sampled and kept；The both-end differential electrical that subtracter exports sampling/retainer Press signal to carry out phase reducing, obtain output voltage for Vout=Vo1-Vo2=8Vh+(Vop1+Vop3+Vop5+Vop7-Vop2-Vop4- Vop6-Vop8), the voltage signal that subtracter is exported is again after low pass filter filters out the amplification of high frequency harmonic components final output Hall voltage signal, and misalignment signal is effectively eliminated, and obtains low-down residual offset voltage △ Vop=Vop1+Vop3+Vop5+ Vop7-Vop2-Vop4-Vop6-Vop8.As clock signal clkS/HIt is changed into clock signal clk after low levelRHigh level is just begun to change into, NMOS tube switch M3 and M4 conductings in current integration amplifier, and on now NMOS tube switch M1 and M2 cut-offs, electric capacity C1 and C2 Electric charge be cleared, prepare next time eight phase rotatory currents and current integration operation.

Claims (4)

1. a kind of eight phase rotatory current circuits for Hall sensor, it is characterised in that circuit comprising 32 NMOS tube M1~ M32, octal hall device, clock signal clk1~clk8, bias current sources and outside port, wherein M1~M8 biases for control Electric current IbiasThe switching tube of octal hall device is flowed into, M9~M16 is control bias current IbiasFlow out opening for octal hall device Guan Guan, M17~M24 flow into outside port I for control hall device current output signalo1Switching tube, M25~M32 for control Hall device current output signal flows into outside port Io2Switching tube, NMOS tube M1~M8 drain electrode is connected to input biasing jointly Current source Ib1Output end, NMOS tube M1~M8 grid is connected to clock signal clk successively respectively1~clk8, NMOS tube M1~ M8 source electrode connects a ports, b ports, c ports, d ports, e ports, f ports, g ports, the h ends of octal hall device successively respectively Mouthful；NMOS tube M9~M16 source electrode is connected to output bias current source I jointlyb2Input, NMOS tube M9~M16 grid point It is not connected to clock signal clk successively1~clk8, NMOS tube M9~M16 drain electrode is connected to the e ends of octal hall device successively respectively Mouth, f ports, g ports, h ports, a ports, b ports, c ports, d ports；NMOS tube M17~M24 source electrode is connected to outside jointly Port Io1, NMOS tube M17~M24 grid is connected to clock signal clk successively respectively1~clk8, NMOS tube M17~M24 leakage Pole is connected to c ports, d ports, e ports, f ports, g ports, h ports, a ports, the b ports of octal hall device successively respectively； NMOS tube M25~M32 source electrode is connected to outside port I jointlyo2, NMOS tube M25~M32 grid is connected to clock successively respectively to be believed Number clk1~clk8, NMOS tube M25~M32 drain electrode is connected to the g ports of octal hall device, h ports, a ports, b successively respectively Port, c ports, d ports, e ports, f ports；All 32 NMOS tubes M1~M32 Substrate ground, two bias current sources Ib1 And Ib2It is equal there is provided bias current size be Ibias, it is ensured that the bias current for flowing in and out octal hall device is equal.
2. the eight phase rotatory current circuits according to claim 1 for Hall sensor, it is characterised in that the octal 8 ports of hall device are 45 ° of rotational symmetry structures.
3. the eight phase rotatory current circuits according to claim 1 for Hall sensor, it is characterised in that the clock clk1~clk8For eight phase sequence clock signals, output polarity is carried out after the operation of eight phase rotatory currents not by octal hall device The Hall current signal and the misalignment signal of change in polarity of change.
4. a kind of eight phase rotatory current circuits for Hall sensor utilized described in claim 1 enter disappearing for Mobile state imbalance Except method, it is characterised in that comprise the steps of：
S1：The differential current signal I of eight phase rotatory current circuit outputso1And Io2Send into current integration amplifier and carry out electric current to electricity The differential voltage signal V of the conversion of pressure, output aliasing Hall voltage and offset voltageo1And Vo2；
S2：During eight phase rotatory currents are operated, the differential voltage signal of current integration amplifier output is respectively Vo1=8Vh+ Vop1+Vop3+Vop5+Vop7, Vo2=Vop2+Vop4+Vop6+Vop8, wherein VhFor Hall current IhExported suddenly by integral amplifier That voltage signal, and Vop1~Vop8For eight phase Hall offset current Iop1~Iop8The offset voltage letter exported by integral amplifier Number；
S3：The differential voltage signal of current integration amplifier output is through over-sampling, and/retainer sample/is re-fed into after keeping and subtracted Musical instruments used in a Buddhist or Taoist mass carries out phase reducing, and the signal of subtracter output is Vout=Vo1-Vo2=8Vh+(Vop1+Vop3+Vop5+Vop7-Vop2-Vop4- Vop6-Vop8)；
S4：Obtained Hall voltage filters out high frequency harmonic components by low pass filter again, the Hall electricity after final output amplification Signal is pressed, misalignment signal is effectively eliminated, and obtains low-down residual offset voltage △ Vop=Vop1+Vop3+Vop5+Vop7-Vop2- Vop4-Vop6-Vop8。
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6278271B1 (en) * 1998-03-30 2001-08-21 Sentron Ag Three dimensional magnetic field sensor
WO2005073744A1 (en) * 2003-12-19 2005-08-11 Xensor Integration B.V. Magnetic field sensor, support for such a magnetic field sensor and a compass provided with such a magnetic field sensor
WO2006028426A1 (en) * 2004-09-08 2006-03-16 Inessa Antonovna Bolshakova Magnetic field measuring sensor
CN104165649A (en) * 2014-08-28 2014-11-26 西北工业大学 Power-on self-detection method for brushless direct-current motor hall sensor
US20150207061A1 (en) * 2011-07-21 2015-07-23 Infineon Technologies Ag Electronic device with ring-connected hall effect regions
CN108137074A (en) * 2015-09-04 2018-06-08 看门人系统公司 The estimation of wheeled vehicle

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6278271B1 (en) * 1998-03-30 2001-08-21 Sentron Ag Three dimensional magnetic field sensor
WO2005073744A1 (en) * 2003-12-19 2005-08-11 Xensor Integration B.V. Magnetic field sensor, support for such a magnetic field sensor and a compass provided with such a magnetic field sensor
WO2006028426A1 (en) * 2004-09-08 2006-03-16 Inessa Antonovna Bolshakova Magnetic field measuring sensor
US20150207061A1 (en) * 2011-07-21 2015-07-23 Infineon Technologies Ag Electronic device with ring-connected hall effect regions
CN104165649A (en) * 2014-08-28 2014-11-26 西北工业大学 Power-on self-detection method for brushless direct-current motor hall sensor
CN108137074A (en) * 2015-09-04 2018-06-08 看门人系统公司 The estimation of wheeled vehicle

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