CN107315107A - Semiconductor device, battery monitor system and detection method - Google Patents
Semiconductor device, battery monitor system and detection method Download PDFInfo
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- CN107315107A CN107315107A CN201710284961.3A CN201710284961A CN107315107A CN 107315107 A CN107315107 A CN 107315107A CN 201710284961 A CN201710284961 A CN 201710284961A CN 107315107 A CN107315107 A CN 107315107A
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- capacitor
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- switching device
- battery core
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/25—Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques
- G01R19/2516—Modular arrangements for computer based systems; using personal computers (PC's), e.g. "virtual instruments"
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/36—Arrangements for testing, measuring or monitoring the electrical condition of accumulators or electric batteries, e.g. capacity or state of charge [SoC]
- G01R31/382—Arrangements for monitoring battery or accumulator variables, e.g. SoC
- G01R31/3835—Arrangements for monitoring battery or accumulator variables, e.g. SoC involving only voltage measurements
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R17/00—Measuring arrangements involving comparison with a reference value, e.g. bridge
- G01R17/02—Arrangements in which the value to be measured is automatically compared with a reference value
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/36—Arrangements for testing, measuring or monitoring the electrical condition of accumulators or electric batteries, e.g. capacity or state of charge [SoC]
- G01R31/396—Acquisition or processing of data for testing or for monitoring individual cells or groups of cells within a battery
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
Abstract
A kind of semiconductor device, battery monitor system and detection method, with low consumption electric current and can realize miniaturization.Semiconductor device includes：1st capacitor group, comprising the 1st capacitor and the 2nd capacitor, the changeable wherein pole being connected in the positive pole of battery battery core and negative pole in one end of the 1st capacitor, one end of the 2nd capacitor is changeable to be connected to another pole；Comparator, possesses the non-inverting input terminal that battery battery core can be connected to via the 1st capacitor and the reversed input terminal of battery battery core can be connected to via the 2nd capacitor, compares the cell voltage and detection threshold value voltage of the battery battery core of connection；2nd capacitor group includes the 3rd capacitor and the 4th capacitor, 3rd capacitor is located between the 1st switch of the connection status of first node and switching and any of ground voltage supplies and reference voltage source, and the 4th capacitor is located between the 2nd switch of the connection status of second node and switching and any of ground voltage supplies and reference voltage source.
Description
Technical field
The present invention relates to a kind of semiconductor device, battery monitor system and detection method.
Background technology
In the past, the cell voltage of the battery battery core (cell) of the secondary cells such as Ni-MH battery or lithium battery was detected.
By detecting the cell voltage of battery battery core, such as can detect whether the state of battery battery core is different as overcharge condition
Normal state, to protect battery battery core itself.
It is used as the technology of the cell voltage of such detection battery battery core, it is known to which one kind detection circuit 126, it is such as Figure 13 institutes
Show, be the differential amplifier 126A comprising resistance R1~R4 and comparator A0 is combined with comparator (comparator) C0 and
Into.As the battery voltage detector using such a detection circuit, for example, there is the technology described in patent document 1.
In conventional art, as shown in figure 13, by possessing switch SW's corresponding with battery battery core V1~Vn battery battery core V
Battery core selecting switch 124 is selected, as detection object battery battery core cathode voltage and cathode voltage via resistance R1,
R2 and input to differential amplifier 126A input terminal.Comparator C0 is by differential amplifier 126A output and reference voltage
VREF is compared the comparative result output of gained as detection signal.
Prior art literature
Patent document
Patent document 1：Japanese Patent Laid-Open 2012-47520 publications
The content of the invention
[invention problem to be solved]
In conventional detection circuit 126 shown in Figure 13, conducting state, battery battery core V are turned into battery core selecting switch 124
Cathode voltage and cathode voltage be supplied in the state of differential amplifier 126A, there is electric current to flow through resistance R1~R4 all the time,
Therefore cell voltage is consumed.In order to suppress resistance R1~R4 consumption electric current, it is necessary to increase resistance R1~R4 resistance value, but
If increasing resistance value, the area needed for resistance R1~R4 setting will become big.Therefore, when the resistance value for increasing resistance R1~R4
When, the overall area of detection circuit 126 will become big, so that the diminution of circuit area can be hampered.
It is an object of the invention to provide a kind of low consumption electric current and the semiconductor device of miniaturization, battery cell monitoring can be realized
System and detection method.
[technological means for solving problem]
In order to reach the purpose, semiconductor device of the invention includes：1st capacitor group, includes the 1st capacitor and the
2 capacitors, the changeable wherein pole being connected in the positive pole of battery battery core and negative pole in one end of the 1st capacitor is described
One end of 2nd capacitor is changeable to be connected to the extremely opposite another pole connected with the 1st capacitor；Comparing section, possesses
Can be connected to via the 1st capacitor battery battery core the 1st input terminal and can be via the 2nd capacitor
The 2nd input terminal of the battery battery core is connected to, the cell voltage of battery battery core and defined detection to being connected
Voltage is compared；And the 2nd capacitor group, comprising the 3rd capacitor and the 4th capacitor, the 3rd capacitor is in first node
Between the 1st switching device, it is connected in series with the 1st switching device, the 4th capacitor is in second node and the 2nd switching member
Between part, it is connected in series with the 2nd switching device, wherein the first node is located at the 1st capacitor and the comparing section
The 1st input terminal between, the 1st switching device switching and the ground voltage supplies comprising supply ground voltage with least
The connection status of any one in one reference voltage source, the second node is located at the 2nd capacitor and the institute of the comparing section
State between the 2nd input terminal, the 2nd switching device switches and the ground voltage supplies and an at least reference voltage source
In the connection status of any one.
Moreover, the battery monitor system of the present invention includes：The multiple batteries being connected in series；And semiconductor device.Partly lead
Body device includes：1st capacitor group, includes the 1st capacitor and the 2nd capacitor, the changeable connection in one end of the 1st capacitor
A wherein pole into the positive pole and negative pole of battery battery core, one end of the 2nd capacitor is changeable to be connected to and the described 1st electricity
Extremely opposite another pole that container is connected；Comparing section, the battery battery core can be connected to via the 1st capacitor by possessing
The 1st input terminal and the 2nd input terminal of the battery battery core can be connected to via the 2nd capacitor, to being connected
Battery battery core the cell voltage with it is defined detection voltage be compared；2nd capacitor group, comprising the 3rd capacitor and
4th capacitor, the 3rd capacitor is connected in series between first node and the 1st switching device with the 1st switching device,
4th capacitor is connected in series, wherein the described 1st between second node and the 2nd switching device with the 2nd switching device
Node is located between the 1st capacitor and the 1st input terminal of the comparing section, the 1st switching device switching with
Ground voltage supplies comprising supply ground voltage and the connection status of any one in an at least reference voltage source, described Section 2
Point is located between the 2nd capacitor and the 2nd input terminal of the comparing section, the 2nd switching device switching and institute
State the connection status of any one in ground voltage supplies and an at least reference voltage source；Switching device group, cuts comprising the 5th
Element and the 6th switching device are changed, one end switching of the 1st capacitor can be connected to the battery by the 5th switching device
One end switching of 2nd capacitor can be connected to by the wherein pole in the positive pole and negative pole of battery core, the 6th switching device
The extremely opposite another pole connected with the 1st capacitor of the battery battery core；And control unit, following controls are carried out,
That is, the ground voltage supplies of the supply ground voltage are made by the 1st switching device and the 2nd switching device
And the other end of reference voltage source, the other end with the 3rd capacitor and the 4th capacitor be connected in the state of pass through
Cross after the stipulated time, the other end with the 3rd capacitor is made by the 1st switching device and the 2nd switching device
And the ground voltage supplies and the different ground voltage supplies of reference voltage source and reference voltage of the other end connection of the 4th capacitor
The other end in source, the other end with the 3rd capacitor and the 4th capacitor is connected.
Moreover, the detection method of the present invention is the detection method of the cell voltage by semiconductor device, battery battery core,
The semiconductor device includes：1st capacitor group, comprising the 1st capacitor and the 2nd capacitor, one end of the 1st capacitor can
Switching is connected to the wherein pole in the positive pole of the battery battery core and negative pole, the changeable connection in one end of the 2nd capacitor
To the extremely opposite another pole connected with the 1st capacitor；Comparing section, possessing can connect via the 1st capacitor
To the battery battery core the 1st input terminal and the battery battery core can be connected to via the 2nd capacitor it is the 2nd defeated
Enter terminal, the cell voltage of the battery battery core to being connected is compared with defined detection voltage；And the 2nd electricity
Container group, comprising the 3rd capacitor and the 4th capacitor, the 3rd capacitor is between first node and the 1st switching device, with institute
State the 1st switching device to be connected in series, the 4th capacitor is between second node and the 2nd switching device, with the described 2nd switching member
Part is connected in series, wherein the first node is located between the 1st capacitor and the 1st input terminal of the comparing section,
The 1st switching device switching and the ground voltage supplies comprising supply ground voltage and any one in an at least reference voltage source
Connection status, the second node be located between the 2nd capacitor and the 2nd input terminal of the comparing section, it is described
The switching of 2nd switching device and the connection status of any one in the ground voltage supplies and an at least reference voltage source,
The detection method includes following processing：By the 1st switching device and the 2nd switching device, the ground connection will be supplied
The ground voltage supplies of voltage and reference voltage source, it is connected with the 3rd capacitor and the 4th capacitor,
, will be with the 3rd capacitor and described by the 1st switching device and the 2nd switching device after the stipulated time
The ground voltage supplies and the different ground voltage supplies of reference voltage source and reference voltage source and the described 3rd electricity of 4th capacitor connection
Container and the 4th capacitor are connected.
[The effect of invention]
According to the present invention, the effect that can realize low consumption electric current and miniaturization is played.
Brief description of the drawings
Fig. 1 is the structure chart of the outline of one of the battery monitor system for representing the 1st embodiment.
Fig. 2 is the battery core selecting switch for representing the 1st embodiment and the circuit diagram of one for detecting circuit.
Fig. 3 is that the battery core selecting switch of the 1st embodiment and charging (charge) state of detection circuit are illustrated
Figure.
Fig. 4 is that the battery core selecting switch of the 1st embodiment and comparison (comparate) state of detection circuit are said
Bright figure.
Fig. 5 is the voltage Vinp and node i nn that illustrate node i np voltage Vinn, the song with cell voltage Vn relation
Line chart.
Fig. 6 is the timing diagram for the sequential (timing) for representing that detection to the cell voltage in the 1st embodiment is related
(timing chart)。
Fig. 7 is the battery core selecting switch for representing the 2nd embodiment and the circuit diagram of one for detecting circuit.
Fig. 8 is the figure illustrated to the battery core selecting switch of the 2nd embodiment and the charged state of detection circuit.
Fig. 9 is the figure illustrated to the battery core selecting switch of the 2nd embodiment and the comparison state of detection circuit.
Figure 10 is the timing diagram for representing the sequential related to the detection of the cell voltage in the 2nd embodiment.
Figure 11 is the battery core selecting switch for representing the 3rd embodiment and the circuit diagram of one for detecting circuit.
Figure 12 is the timing diagram for representing the sequential related to the detection of the cell voltage in the 3rd embodiment.
Figure 13 is the circuit diagram of one for representing conventional battery core selecting switch and detecting circuit.
[explanation of symbol]
10：Battery monitor system
12：Battery battery core group
14：Battery cell monitoring large scale integrated circuit
16：Microcomputer
210~21n、211_1、211_2、212_1、212_2, 23, a~x：Terminal
24、124：Battery core selecting switch
26、126：Detect circuit
30：Chip internal control portion
126A：Differential amplifier
A0：Comparator
C1~C4, C3 ', C3 ", C4 ', C4 "：Capacitor
C0、CMP0：Comparator
GND：Ground voltage supplies/ground voltage
inn、inp、VN0、VN1、VN2、VNn、VNn-1、VNn-2：Node
L1、L2：Signal wire
OUT：Detect signal
R1~R4：Resistance
S1~S6, SW1_1~SWn_1, SW1_2~SWn_2, SW2_2, SWn-1_1：Switch
V1、V2、Vn：Battery battery core/cell voltage
VCOM、VREF、VREF1、VREF2、VREFc~VREFx：Reference voltage source/reference voltage
Vinn：Node i nn voltage
Vinp：Node i np voltage
Vn-1_total：Battery battery core V1~Vn-1 cell voltage it is total
Vn_th：Detection threshold value voltage
CMP+：Linking objective is comparator CMP0 non-inverting input terminal
CMP-：Linking objective is comparator CMP0 reversed input terminal
Embodiment
Hereinafter, each embodiment is described in detail with reference to the attached drawings.
[the 1st embodiment]
First, the battery monitor system of present embodiment is illustrated.Fig. 1 shows the battery for representing present embodiment
The structure chart of the outline of one of monitoring system 10.
Battery monitor system 10 is as shown in figure 1, possess battery battery core group 12, battery cell monitoring large scale integrated circuit (large
Scale integrated circuit, LSI) 14 and microcomputer (micro computer) 16.
As one, battery battery core group 12 as shown in figure 1, possessing n battery battery core V1~Vn being connected in series.Battery electricity
Core V1~Vn from low potential side according to V1, V2 ..., Vn order and configure.In addition, it is following, do not differentiating between battery battery core V1
~Vn respective and during general name, omit the record for the 1~n of symbol for recognizing each battery battery core and be referred to as " battery battery core V ".Separately
Outside, in Fig. 1, n represents more than 3 situation, but the battery battery core V quantity n that battery battery core group 12 possesses is any, and infinitely
It is fixed.
Microcomputer 16 carries out the electricity to each battery battery core V contained in battery battery core group 12 with battery cell monitoring LSI 14
The control of the detection correlation of cell voltage.In addition, in present embodiment, battery cell monitoring LSI 14 and microcomputer 16 are independently
Ground is configured to semiconductor chip.
Battery cell monitoring LSI 14 is monitored to the respective voltage status of battery battery core V contained in battery battery core group 12.
In present embodiment, battery cell monitoring LSI 14 corresponds to the semiconductor device of the present invention.Battery cell monitoring LSI 14 as shown in figure 1,
Possesses terminal 210~21n, terminal 23, battery core selecting switch 24, detection circuit 26 and chip internal control portion 30.
Terminal 210~21nIt is the electronic pads (pad) that power supply cell monitoring LSI 14 is connected with battery battery core group 12.Terminal
210It is connected to battery battery core V1 negative pole and ground connection.Terminal 211_1And terminal 211_2It is connected to battery battery core V1 positive pole (electricity
Pond battery core V2 negative pole).Terminal 212_1And terminal 212_2The positive pole for being connected to battery battery core V2 (eliminates the battery battery core of diagram
V3 negative pole).Terminal 21nIt is connected to battery battery core Vn positive pole.In addition, it is following, do not differentiating between terminal 210~21nIt is respective and
During general name, omit the record for the symbol for recognizing each terminal and be referred to as " terminal 21 ".In addition, in present embodiment, it is so-called " to connect
Connect ", refer to electrical connection.
Terminal 23 is the electronic pads that power supply cell monitoring LSI 14 is connected with microcomputer 16.Exported from terminal 23 from core
Control unit 30 is sent to the signal of microcomputer 16 in piece.Moreover, being sent from microcomputer 16 to chip internal control portion 30
Signal be input to terminal 23.
Details battery core selecting switch 24 described later is connected to terminal 210~21n, basis is exported from chip internal control portion
The control signals of 30 supplies and a battery battery core V cathode voltage and cathode voltage selected from battery battery core group 12, and
Feed these to detection circuit 26.
Details it is described later detection circuit 26 battery battery core V export from battery core selecting switch 24 cathode voltage and
The difference of cathode voltage be cell voltage be more than detection threshold value voltage Vn_th when, export high level detection signal OUT, when
During less than detection threshold value voltage Vn_th, low level detection signal OUT is exported.In addition, in present embodiment, so-called battery electricity
The detection of core V cell voltage, is not that battery battery core V specific magnitude of voltage is detected, and is referred to by detecting electricity
Road 26 come with it is defined detection voltage be that detection threshold value voltage Vn_th is compared.
Chip internal control portion 30 controlled according to the control signal supplied from microcomputer 16 battery core selecting switch 24 and
Detect circuit 26.Moreover, chip internal control portion 30 sends detection signal OUT of cell voltage exported from detection circuit 26 etc.
To microcomputer 16.
Next, describing the battery core selecting switch 24 and detection circuit 26 of present embodiment in detail.
Fig. 2 represents battery core selecting switch 24 and detects one of the circuit structure of circuit 26.In addition, in Fig. 2, for the ease of
Diagram, for battery battery core V and battery core selecting switch 24, only describes the content related to battery battery core V1, V2, Vn.Moreover,
In Fig. 2, the record of terminal 21 is eliminated.
When setting y=1~n, battery battery core Vy negative pole is connected to node VNy-1, and positive pole is connected to node VNy.For example,
As shown in Fig. 2 battery battery core V1 (y=1) negative pole is connected to node VN0, positive pole is connected to node VN1.
Moreover, battery core selecting switch 24 possess switch SW1_1~SWn_1, SW1_2 corresponding with each battery battery core V~
SWn_2.Controls of the SW1_1~SWn_1 by chip internal control portion 30 is switched, by each battery battery core V negative or positive electrode and letter
Number line L1 connections.Moreover, switch controls of the SW1_2~SWn_2 by chip internal control portion 30, by each battery battery core V positive pole
Or negative pole is connected with signal wire L2.In addition, following, do not differentiate between switch SW1_1~SWn_1, SW1_2~SWn_2 respective and
During general name, omit the record for the symbol for recognizing each switch and be referred to as " switch SW ".
When setting y=1~n, switch SWy_1 a terminals are connected to node VNy, b terminal and are connected to node VNy-1, c ends
Son is connected to capacitor C1 a terminals via signal wire L1.Moreover, switch SWy-2 a terminals are connected to node VNy-1, b
Terminal is connected to a terminals that node VNy, c terminal is connected to capacitor C2 via signal wire L2.For example, as shown in Fig. 2 opening
The a terminals for closing SW1_1 are connected to node VN1, b terminal and are connected to node VN0, c terminal and are connected to electric capacity via signal wire L1
Device C1 a terminals.Moreover, switch SW1_2 a terminals are connected to node VN0, b terminal and are connected to node VN1, c terminal via letter
Number line L2 and a terminals for being connected to capacitor C2.
Moreover, detection circuit 26 is as shown in Fig. 2 possess capacitor C1~C4, switch S1~S4 and comparator CMP0.
Capacitor C1 b terminals are connected to capacitor C3 a terminals and switch S3 a terminals.Switch S3 passes through in chip
The control of control unit 30, supply reference voltage V is connected to by capacitor C1 b terminalsCOMReference voltage source VCOMOr comparator
CMP0 non-inverting input terminal.Switch S3 b terminals are connected to reference voltage source VCOM, c terminals are connected to comparator CMP0's
Non-inverting input terminal.Capacitor C3 b terminals are connected to switch S1 a terminals.Switch S1 passes through chip internal control portion 30
Control, capacitor C3 b terminals is connected to supply ground voltage GND ground voltage supplies GND or supply reference voltage VREF's
Reference voltage source VREF.Switch S1 b terminals are connected to ground voltage supplies GND, c terminal and are connected to reference voltage source VREF。
Capacitor C2 b terminals are connected to capacitor C4 a terminals and switch S4 a terminals.Switch S4 passes through in chip
The control of control unit 30, reference voltage source V is connected to by capacitor C2 b terminalsCOMOr comparator CMP0 inverting input
Son.Switch S4 b terminals are connected to reference voltage source VCOM, c terminals are connected to comparator CMP0 reversed input terminal.Electric capacity
Device C4 b terminals are connected to switch S2 a terminals.Controls of the S2 by chip internal control portion 30 is switched, by capacitor C4 b ends
Son is connected to ground voltage supplies GND or reference voltage source VREF.Switch S2 b terminals are connected to ground voltage supplies GND, c terminal company
It is connected to reference voltage source VREF。
Next, the detection operation to the cell voltage in the detection circuit 26 of present embodiment is illustrated.Hereinafter, join
According to Fig. 3 and Fig. 4, situation about being detected using the cell voltage to n-th of battery battery core Vn is illustrated as concrete example.Separately
Outside, in Fig. 3 and Fig. 4, for the ease of diagram, the record in unwanted each portion during explanation is eliminated.
When carry out n-th of battery battery core Vn cell voltage detection when, chip internal control portion 30 as shown in Figures 3 and 4,
Control each switch SW of battery core selecting switch 24 and detect switch S1~S4 of circuit 26.If in addition, ignoring error, in chip
The sequential that control unit 30 carries out switch SW and switch S1~S4 control is identical.
First, chip internal control portion 30 by battery core selecting switch 24 and detection circuit 26 as shown in figure 3, be set to the shape that charges
State.
Specifically, chip internal control portion 30 makes the switch SWn_1 of battery core selecting switch 24 select node VNn (a terminals),
The switch SWn_2 of battery core selecting switch 24 is selected node VNn-1 (a terminals), and other switches SW is set to nonselection mode
(a terminals and b terminals non-selected state).
And then, chip internal control portion 30 makes the switch S1 of detection circuit 26 select ground voltage supplies GND (b terminals), makes out
Close S2 selection reference voltage sources VREF(c terminals), makes switch S3 select reference voltage source VCOM(b terminals), makes switch S4 select base
Reference voltage source VCOM(b terminals).
Herein, if the cell voltage for setting battery battery core Vn cell voltage as Vn, battery battery core V1~Vn-1 adds up to Vn-
1_total, capacitor C1~C4 each electric capacity are Cp1~Cp4, then to quantity of electric charge Q1~Q4 of capacitor C1~each self-chargings of C4
Represented with following (1) formula~(4) formulas.
Q1=Cp1 × (Vn+Vn-1_total-VCOM)…(1)
Q2=Cp2 × VCOM…(2)
Q3=Cp3 × (Vn-1_total-VCOM)…(3)
Q4=Cp4 × (VCOM-VREF)…(4)
If setting to capacitor C1 b terminals and switching the quantity of electric charge of the node i np chargings between S3 a terminals as Qp, right
The quantity of electric charge of node i nn chargings between capacitor C2 b terminals and a terminals for switching S4 is Qn, then quantity of electric charge Qp, below Qn
(5) formula and (6) formula is stated to represent.
Qp=Q2-Q1=Cp2 × VCOM-Cp1×(Vn+Vn-1_total-VCOM)…(5)
Qn=Q4-Q3=Cp4 × (VCOM-VREF)-Cp3×(Vn-1_total-VCOM)…(6)
In the charge state, in each capacitor C after abundant accumulated charge, chip internal control portion 30 is as shown in figure 4, control
System switchs SW and switch S1~S4 to switch to and compare state battery core selecting switch 24 and detection circuit 26 by charged state.
Specifically, chip internal control portion 30 makes the switch SWn_1 of battery core selecting switch 24 select node VNn-1 (b ends
Son), switch SWn_2 is selected node VNn (b terminals), other switches SW of battery core selecting switch 24 is set to nonselection mode
(a terminals and b terminals non-selected state).
And then, chip internal control portion 30 makes the switch S1 of detection circuit 26 select reference voltage source VREF(c terminals), makes out
S2 selection ground voltage supplies GND (b terminals) are closed, switch S3 is selected comparator CMP0 non-inverting input terminal (c terminals), makes
Switch S4 selection comparators CMP0 reversed input terminal (c terminals).
Herein, if it is Vinn to set node i np voltage as Vinp, node i nn voltage, compare under state to electric capacity
Quantity of electric charge Q1 '~Q4 ' of device C1~each self-chargings of C4 is represented with following (7) formula~(10) formulas.
Q1 '=Cp1 × (Vn-1_total-Vinp) ... (7)
Q2 '=Cp2 × (Vinp-VREF)…(8)
Q3 '=Cp3 × (Vn+Vn-1_total-Vinn) ... (9)
Q4 '=Cp4 × Vinn ... (10)
If it is Qn ' to set the quantity of electric charge charged to node i np as Qp ', to the node i nn quantities of electric charge charged, compare state
Under quantity of electric charge Qp ', Qn ' represented with following (11) formulas and (12) formula.
Qp '=Q2 '-Q1 '=Cp2 × (Vinp-VREF)-Cp1×(Vn-1_total-Vinp)…(11)
Qn '=Q4 ' Q3 '=Cp4 × Vinn-Cp3 × (Vn+Vn-1_total-Vinn) ... (12)
If assuming, the input impedance (impedance) of comparator CMP0 non-inverting input terminal and reversed input terminal is filled
It is point high, compare state even if being then converted to from charged state, the quantity of electric charge Qp that is accumulated in node i np and be accumulated in node i nn
In quantity of electric charge Qn will not also change, therefore following (13) formulas and (14) formula are set up.
Qp=Qp ' ... (13)
Qn=Qn ' ... (14)
According to (5) formula, (11) formula and (13) formula, for voltage Vinp, following (15) formulas are obtained.Moreover, according to institute
(6) formula, (12) formula and (14) formula are stated, for voltage Vinn, following (16) formulas are obtained.
Vinp=VCOM-Cp1/(Cp1+Cp2)×Vn+Cp2/(Cp1+Cp2)×VREF…(15)
Vinn=VCOM+Cp3/(Cp3+Cp4)×Vn-Cp4/(Cp3+Cp4)×VREF…(16)
According to (15) formula, voltage Vinp has negative slope relative to cell voltage Vn, according to (16) formula, voltage Vinn
There is positive slope relative to cell voltage Vn.Voltage Vinp, the Vinn and battery obtained by (15) formula and (16) formula
Voltage Vn relation turns into as illustrated in Fig. 5.
As illustrated in Figure 5, represent voltage Vinn line with expression voltage Vinp line when cell voltage Vn is Vn_th
(Vn=Vn_th) intersect.Thus, the electricity of (Vinn=Vinp) when voltage Vinn is become equal by comparator CMP0 with voltage Vinp
Pressure is acted as detection threshold value voltage Vn_th.Comparator CMP0 voltage Vinn be more than voltage Vinp when (Vinn >=
Vinp), the detection signal of high level is exported, when voltage Vinn is less than voltage Vinp (Vinn ＜ Vinp), is exported low level
Detect signal.
According to (15) formula and (16) formula, comparator CMP0 detection threshold value voltage Vn_th is come with following (17) formulas
Represent.
Vn_th={ Cp2/ (Cp1+Cp2)+Cp4/ (Cp3+Cp4) }/{ Cp1/ (Cp1+Cp2)+Cp3/ (Cp3+Cp4) } ×
VREF…(17)
It can be seen from (17) formula, detection threshold value voltage Vn_th depends on capacitor C1~C4 electric capacity Cp1~Cp4 and base
Quasi- voltage VREF.Thus, the comparator CMP0 of present embodiment can be according to capacitor C1~C4 electric capacity Cp1~Cp4 and benchmark
Voltage VREFValue set arbitrary detection threshold value voltage Vn_th.
And then, for capacitor C1~C4 electric capacity Cp1~Cp4, if being represented down using using arbitrary constant j, k, m
(18)~(19) formula is stated, then described (17) formula can be represented with following (21) formulas.
Cp2=j × Cp1 ... (18)
Cp3=k × Cp1 ... (19)
Cp4=m × Cp1 ... (20)
Vn_th={ j/ (1+j)+m/ (k+m) }/{ 1/ (1+j)+1/ (k+m) } × VREF…(21)
It can be seen from (21) formula, detection threshold value voltage Vn_th depends on capacitor C1~C4 capacity ratio (j, k, m) and base
Quasi- voltage VREF.Thus, the comparator CMP0 of present embodiment can be according to capacitor C1~C4 electric capacity when reference voltage
VREFValue set arbitrary detection threshold value voltage Vn_th.
Thus, capacitor C1~C4 electricity is selected by way of turning into required size with detection threshold value voltage Vn_th
Hold when reference voltage VREF, so as to carry out cell voltage V detection using circuit 26 is detected.
For example, by the way that detection threshold value voltage Vn_th level is set into the level suitable with overcharging electro-detection voltage, so that
Under relatively state from comparator CMP0 export detection signal be high level when, can detect battery battery core V be overcharge shape
State.
In addition, in described, the situation of the detection of the cell voltage to carrying out battery battery core Vn is illustrated, but for it
His battery battery core V similarly, can compare state by being switched to from charged state, so that under relatively state, based on from than
The detection of cell voltage is carried out compared with the level of the device CMP0 detection signals exported.
Fig. 6, which is shown, represents, battery core selection related to the detection of the cell voltage of the battery battery core V in present embodiment
Switch 24 switch SW and detect circuit 26 switch S1~S4 linking objective (selection target) timing diagram, wherein CMP+ and
CMP- represents non-inverting input terminal and reversed input terminal of the linking objective as comparator CMP0 respectively.
As shown in fig. 6, when carrying out the battery battery core V detection of each cell voltage, being opened from the battery battery core V of low voltage side
Begin in turn, chip internal control portion 30 is to charged state (" charging " of reference picture 6) and compares state (" comparison " of reference picture 6)
Control is repeated, thus, the detection of cell voltage is carried out to timesharing to each battery battery core V.During specific needed for each state
Between according to battery core selecting switch 24, switch S1~S4 conducting resistance and capacitor C1~C4 time constant depending on.
Detect that switch S1~S4 of circuit 26, for each battery battery core V, switches linking objective (selection mesh as described above
Mark), thus recharge state is with being compared state.Moreover, in the switch SW of battery core selecting switch 24, the electricity only with being detected
Pond battery core V switch accordingly SW become as described above linking objective (selection target) battery battery core V negative side section
Point and the node of side of the positive electrode are in charged state with being compared switching between state.
Also, in the battery cell monitoring LSI 14 of present embodiment, for example, as described above, when comparator CMP0 detection threshold
Threshold voltage Vn_th level be the level suitable with overcharging electro-detection voltage when, under relatively state, based on from detection circuit 26
Comparator CMP0 outputs detection signal OUT level, chip internal control portion 30 detects whether each battery battery core V is overcharge
State.In addition, can also export detection signal OUT from chip internal control portion 30 to microcomputer 16, microcomputer 16 is based on
Signal OUT level is detected to detect whether battery battery core V is overcharge condition.
[the 2nd embodiment]
In the detection circuit 26 of 1st embodiment, the detection threshold value voltage V_th that comparator CMP0 can be set as
One, therefore according to the detection circuit 26 of the 1st embodiment, whether the state that can detect the cell voltage of battery battery core is specific
State.
On the other hand, in the detection circuit 26 of present embodiment, multiple detection threshold value electricity can be set to comparator CMP0
Press V_th.
The overall structure of battery monitor system 10 is substantially same with the 1st embodiment, therefore omits the description, to this embodiment party
The detection circuit 26 of formula is illustrated.
Fig. 7 represents the battery core selecting switch 24 of present embodiment and detects one of the circuit structure of circuit 26.In addition, figure
In 7, for the ease of diagram, for battery battery core V and battery core selecting switch 24, only describe related to battery battery core V1, V2, Vn
Content.Moreover, eliminating the record of terminal 21 in Fig. 7.
As shown in fig. 7, the battery core selecting switch 24 of the battery core selecting switch 24 and the 1st embodiment of present embodiment is same
Sample, therefore omit the description.
As shown in fig. 7, in the detection circuit 26 of present embodiment, switching S1, S2 structure and the switch of the 1st embodiment
S1, S2 structure are different.Switch S1, S2 of 1st embodiment possess a terminals~c terminals, but the switch S1 of present embodiment,
S2 possesses a terminals~x-terminal, and the number of terminals possessed is more than switch S1, S2 of the 1st embodiment.
Switch S1, S2 b terminals are connected to ground voltage supplies GND.On the other hand, c terminals~x-terminal is connected to supply respectively
The reference voltage V differedREF(VREFc~VREFx) reference voltage source VREFc~VREFx.Switch S1 passes through chip internal control portion 30
Control, capacitor C3 b terminals are connected to ground voltage supplies GND or reference voltage source VREFc~VREFxIn any one.And
And, controls of the S2 by chip internal control portion 30 is switched, capacitor C4 b terminals are connected to ground voltage supplies GND or benchmark
Voltage source VREFc~VREFxIn any one.
That is, in the detection circuit 26 of present embodiment, the reference voltage that the b terminals with capacitor C3, C4 can be connected
Source switches to reference voltage source VREFc~VREFxIn any one.
In addition, reference voltage source VREFc~VREFxQuantity and the position that is arranged be not particularly limited, in present embodiment
Diagram is eliminated, but as one, is disposed in outside the detection circuit 26 inside battery cell monitoring LSI 14.
Detection operation to the cell voltage in the detection circuit 26 of present embodiment is illustrated.Hereinafter, reference picture 8 and
Fig. 9, with reference voltage VREF1、VREF2And situation about being detected to n-th of battery battery core Vn cell voltage is concrete example
To illustrate.In addition, in Fig. 8 and Fig. 9, for the ease of diagram, eliminating the record in unwanted each portion during explanation.
In the same manner as detection operation with the cell voltage in the detection circuit 26 of the 1st embodiment, in present embodiment
In the detection operation for detecting the cell voltage in circuit 26, compare state by being switched to from charged state, can also compare
The detection of cell voltage is carried out based on the level from the comparator CMP0 detection signals exported under state.
When carry out n-th of battery battery core Vn cell voltage detection when, chip internal control portion 30 as can be seen from figures 8 and 9,
Control each switch SW of battery core selecting switch 24 and detect switch S1~S4 of circuit 26.If in addition, ignoring error, in chip
The sequential that control unit 30 carries out switch SW and switch S1~S4 control is identical.
First, using reference voltage VREF1, chip internal control portion 30 as shown in figure 8, by battery core selecting switch 24 and detection
Circuit 26 is set to charged state.
Specifically, chip internal control portion 30 in a same manner as in the first embodiment, makes the switch SWn_ of battery core selecting switch 24
1 selection node VNn (a terminals), makes switch SWn_2 select node VNn-1 (a terminals), and other switches SW is set into non-selection shape
State (a terminals and b terminals non-selected state).
And then, chip internal control portion 30 makes the switch S1 of detection circuit 26 select ground voltage supplies GND (b terminals), makes out
Close S2 selection reference voltage sources VREF1(c terminals) (solid line of the switch S2 in reference picture 8), makes switch S3 select reference voltage source
VCOM(b terminals), makes switch S4 select reference voltage source VCOM(b terminals).
In the charge state, in each capacitor C after abundant accumulated charge, chip internal control portion 30 is as shown in figure 9, control
System switchs SW and switch S1~S4 to be switched to and compare state battery core selecting switch 24 and detection circuit 26 by charged state.
Specifically, in a same manner as in the first embodiment, chip internal control portion 30 makes the switch SWn_ of battery core selecting switch 24
1 selection node VNn-1 (b terminals), makes switch SWn_2 select node VNn (b terminals), other by battery core selecting switch 24 are opened
Close SW and be set to nonselection mode (a terminals and b terminals non-selected state).
And then, chip internal control portion 30 makes the switch S1 of detection circuit 26 select reference voltage source VREF1(c terminals) (reference
The solid line of switch S1 in Fig. 9), switch S2 is selected ground voltage supplies GND (b terminals), switch S3 is selected comparator CMP0
Non-inverting input terminal (c terminals), switch S4 is selected comparator CMP0 reversed input terminal (c terminals).
Based on (21) formula described in the 1st embodiment, detection threshold value voltage now can be with following (22) Shi Laibiao
Show.
Vn_th1={ j/ (1+j)+m/ (k+m) }/{ 1/ (1+j)+1/ (k+m) } × VREF1…(22)
Next, using reference voltage VREF2, chip internal control portion 30 as shown in figure 8, by battery core selecting switch 24 and inspection
Slowdown monitoring circuit 26 is set to charged state again.Control on chip internal control portion 30 to battery core selecting switch 24, charged state
Situation and it is aftermentioned compare state with use the reference voltage VREF1Situation it is same, therefore omit the description.
On the other hand, chip internal control portion 30 makes the switch S1 of detection circuit 26 select ground voltage supplies GND (b terminals),
Switch S2 is set to select reference voltage source VREF2(d terminals) (dotted line of the switch S2 in reference picture 8), makes switch S3 select benchmark electricity
Potential source VCOM(b terminals), makes switch S4 select reference voltage source VCOM(b terminals).
In the charge state, in each capacitor C after abundant accumulated charge, chip internal control portion 30 is as shown in figure 9, control
System switchs SW and switch S1~S4 to be switched to and compare state battery core selecting switch 24 and detection circuit 26 by charged state.
Chip internal control portion 30 makes the switch S1 of detection circuit 26 select reference voltage source VREF2(d terminals) is (in reference picture 9
Switch S1 dotted line), switch S2 is selected ground voltage supplies GND (b terminals), make switch S3 select comparator CMP0's non-anti-
Phase input terminal (c terminals), makes switch S4 select comparator CMP0 reversed input terminal (c terminals).
Based on (21) formula described in the 1st embodiment, detection threshold value voltage now can be with following (23) Shi Laibiao
Show.
Vn_th2={ j/ (1+j)+m/ (k+m) }/{ 1/ (1+j)+1/ (k+m) } × VREF2…(23)
, can be according to reference voltage according to the detection circuit 26 of present embodiment according to (21) formula and (22) formula
VREF1、VREF2To set arbitrary detection threshold value voltage Vn_th1, Vn_th2.Thus, by switching reference voltage VREF1、VREF2
To carry out detection operation, so as to each carry out cell voltage V inspection using two detection threshold value voltages Vn_th1, Vn_th2
Survey.
For example, by the way that detection threshold value voltage Vn_th1 level is set into the level suitable with overcharging electro-detection voltage, from
And when from the detection signal that comparator CMP0 is exported being high level under relatively state, it is capable of detecting when battery battery core V to overcharge
Electricity condition.Moreover, by the way that detection threshold value voltage Vn_th2 level is set into the level suitable with overdischarge detection voltage, so that
Under relatively state from comparator CMP0 export detection signal be low level when, be capable of detecting when battery battery core V be overdischarge
State.
In addition, in described, the situation of the detection of the cell voltage to carrying out battery battery core Vn is illustrated, but for it
His battery battery core V similarly, compares state by being switched to from charged state, so as under relatively state, based on from than
The detection of cell voltage is carried out compared with the level of the device CMP0 detection signals exported.
Figure 10, which is shown, represents, battery core choosing related to the detection of the cell voltage of the battery battery core V in present embodiment
The timing diagram of the switch SW for selecting switch 24 and the switch S1~S4 for detecting circuit 26 linking objective (selection target).
As shown in Figure 10, when carrying out the battery battery core V detection of each cell voltage, from the battery battery core V of low voltage side
Start in turn, chip internal control portion 30 is to charged state (" charging " in reference picture 10) and compares state (in reference picture 10
" comparison ") control is repeated, and be repeated and use reference voltage VREF1Detection " 1 " and use reference voltage VREF2
Detection " 2 " so that timesharing carry out the detection of cell voltage for each battery battery core V.
So it is controlled by chip internal control portion 30, so that in the battery cell monitoring LSI14 of present embodiment, example
Such as, as described above, when comparator CMP0 detection threshold value voltage Vn_th1 level is the electricity suitable with overcharging electro-detection voltage
It is flat, it is respective in detection 1 and detection 2 when detection threshold value voltage Vn_th2 level is the level suitable with overdischarge detection voltage
Comparison state under, the level of the detection signal OUT based on the comparator CMP0 outputs from detection circuit 26, chip internal control portion
Whether 30 each battery battery core V of detection are overcharge condition, moreover, detecting whether as over-discharge state.
In addition, in timing diagram shown in Figure 10, illustrating and being in turn repeated since the battery battery core V of low voltage side
Detection 1 and the situation of detection 2, but carry out detection 1 and detect that 2 sequential is not limited to this.For example, also can be from the electricity of low voltage side
Pond battery core V starts to carry out detection 1 successively, after to all battery battery core V detection of end 1, from the battery battery core V of low voltage side
Start to carry out detection 2 successively.
[the 3rd embodiment]
In the detection circuit 26 of 2nd embodiment, switch S1 and switch S2 will connect with capacitor C3, C4 b terminals
The reference voltage source connect switches to reference voltage source VREFc~VREFxIn any one, so as to comparator CMP0 set it is many
Individual detection threshold value voltage V_th.
On the other hand, in the detection circuit 26 of present embodiment, multiple capacitor C3, the C4s different by possessing electric capacity,
So as to set multiple detection threshold value voltage V_th to comparator CMP0.
The overall structure of battery monitor system 10 is substantially same with the 1st embodiment, therefore omits the description, to this embodiment party
The detection circuit 26 of formula is illustrated.
Figure 11 represents the battery core selecting switch 24 of present embodiment and detects one of the circuit structure of circuit 26.In addition,
In Figure 11, for the ease of diagram, for battery battery core V and battery core selecting switch 24, only describe and battery battery core V1, V2, Vn
Related content.Moreover, in Figure 11, eliminating the record of terminal 21.
As shown in figure 11, the battery core selecting switch 24 of the battery core selecting switch 24 and the 1st embodiment of present embodiment is same
Sample, therefore omit the description.
As shown in figure 11, in the detection circuit 26 of present embodiment, capacitor C3 include be connected in parallel capacitor C3 ',
C3″.Moreover, in the detection circuit 26 of present embodiment, capacitor C4 possesses capacitor C4 ', the C4 " being connected in parallel.
And then, the detection circuit 26 of present embodiment possesses switch S5, S6.Switch controls of the S5 by chip internal control portion 30
System, a terminals of capacitor C3 ' a terminals or capacitor C3 " are connected with node i np.Specifically, S5 a ends are switched
Son is connected to a terminals that node i np, b terminal is connected to capacitor C3 ', and c terminals are connected to capacitor C3 " a terminals.
The respective b terminals of capacitor C3 ', C3 " are connected to switch S1 a terminals.
Moreover, switch controls of the S6 by chip internal control portion 30, by capacitor C4 ' a terminals or capacitor C4 " a
Terminal is connected with node i nn.Specifically, switch S6 a terminals are connected to node i nn, b terminal and are connected to capacitor
C4 ' a terminals, c terminals are connected to capacitor C4 " a terminals.
The respective b terminals of capacitor C4 ', C4 " are connected to switch S2 a terminals.
Understood as described in (21) formula using the 1st embodiment, comparator CMP0 detection threshold value voltage Vn_th is depended on
Capacitor C1~C4 capacity ratio (j, k, m) and reference voltage VREF。
For example, by making the electric capacity capacitor C3 " different from capacitor C3 ' and node i np connections carry out detection operation,
Because the capacity ratio in the capacity ratio in capacitor C1, C2, C3 ', C4 ' and capacitor C1, C2, C3 ", C4 " is different, therefore, it is possible to
The different arbitrary detection threshold value voltage Vn_th of setting.
Thus, according to the detection circuit 26 of present embodiment, according to required detection threshold value voltage Vn_th, possess electric capacity
Than different capacitor C3 ', C3 " or capacity ratio different capacitor C4 ', C4 ", thus allow for and multiple detection threshold values electricity
Press the corresponding battery battery core V of V_th detection.For example, based on the capacity ratio in capacitor C1, C2, C3 ', C4 ', according to described
(21) formula, can set detection threshold value voltage Vn_th1 corresponding with overcharging electro-detection voltage, based on capacitor C1, C2, C3 ",
Capacity ratio in C4 ", according to (21) formula, can set detection threshold value voltage Vn_ corresponding with overdischarge detection voltage
th2。
Figure 12, which is shown, represents, battery core choosing related to the detection of the cell voltage of the battery battery core V in present embodiment
The timing diagram of the switch SW for selecting switch 24 and the switch S1~S4 for detecting circuit 26 linking objective (selection target).
As shown in figure 12, when carrying out the battery battery core V detection of each cell voltage, from the battery battery core V of low voltage side
Start in turn, chip internal control portion 30 is to charged state (" charging " in reference picture 10) and compares state (in reference picture 10
" comparison ") be repeated control, and be repeated using capacitor C3 ', C4 ' detection " 1 " and using capacitor C3 ",
C4 " detection " 2 ", thus timesharing carry out the detection of cell voltage for each battery battery core V.
By chip internal control portion 30 so as be controlled so that in the battery cell monitoring LSI 14 of present embodiment,
For example, as described above, when comparator CMP0 detection threshold value voltage Vn_th1 level is suitable with overcharging electro-detection voltage
Level, it is each in detection 1 and detection 2 when detection threshold value voltage Vn_th2 level is the level suitable with overdischarge detection voltage
From comparison state under, the level of the detection signal OUT based on the comparator CMP0 outputs from detection circuit 26, chip internal control system
Portion 30 detects whether each battery battery core V is overcharge condition, moreover, detecting whether as over-discharge state.
In addition, in timing diagram shown in Figure 12, illustrating and being in turn repeated since the battery battery core V of low voltage side
Detection 1 and the situation of detection 2, but carry out detection 1 and detect that 2 sequential is not limited to this.For example, also can be from the electricity of low voltage side
Pond battery core V starts in turn to carry out detection 1, after to all battery battery core V detection of end 1, from the battery of low voltage side
Battery core V starts in turn to carry out detection 2.
In addition, in detection circuit 26 shown in Figure 11, illustrate can be connected with node i np two capacitor C3 (C3 ',
C3 "), the two capacitor C4 that can be connected with node i nn (C4 ', C4 "), but detect the quantity for the capacitor that circuit 26 possesses
It is not limited to this.For example, also can only possess multiple capacitors that can be connected with node i np and the electric capacity that can be connected with node i nn
Any one of device.Moreover, for example, by by the capacitor that can be connected with node i np and the capacitor that can be connected with node i nn
Quantity be set to more than three, so as to set more detection threshold value voltage Vn_th to comparator CMP0.
As described above, the battery cell monitoring LSI 14 of present embodiment detection circuit 26 includes：1st capacitor
Group, includes capacitor C1 and capacitor C2, the changeable positive pole and negative pole for being connected to battery battery core V in one end of the capacitor C1
In a wherein pole, one end of the capacitor C2 is changeable to be connected to the extremely opposite another pole connected with capacitor C1；
And comparator CMP0, possess non-inverting input terminal that battery battery core V can be connected to via capacitor C1 and can be via electricity
Container C2 and the reversed input terminal for being connected to battery battery core V, to the battery battery core V cell voltage and detection threshold value connected
Voltage Vn_th is compared.Moreover, detection circuit 26 possesses the 2nd capacitor group, the 2nd capacitor group includes capacitor C3
And capacitor C4, the capacitor C3 are between node i np and switch S1, it is connected in series with switch S1, the capacitor C4 exists
Between node i nn and switch S2, it is connected in series with switch S2, wherein the node i np is located at capacitor C1 and comparator CMP0
Non-inverting input terminal between, switch S1 switching and ground voltage supplies GND and reference voltage source VREFIn any one
Connection status, the node i nn is located between capacitor C2 and comparator CMP0 reversed input terminal, the switch S2 switchings
With ground voltage supplies GND and reference voltage source VREFIn the connection status of any one.
In conventional battery cell monitoring LSI shown in Figure 13, conducting state, battery battery core V are turned into battery core selecting switch 124
Cathode voltage and cathode voltage be supplied in the state of differential amplifier 126A, there is electric current to flow through resistance R1~R4 all the time,
Therefore cell voltage is consumed.In order to suppress resistance R1~R4 consumption electric current, it is necessary to increase resistance R1~R4 resistance value, but
If increasing resistance value, the problem of area needed for there is resistance R1~R4 setting becomes big.
On the other hand, the detection circuit 26 of each embodiment includes capacitor C1~C4 and switch S1~S4, not
Possesses resistance R1~R4 such as conventional detection circuit 126.Therefore, conducting state, battery electricity are turned into battery core selecting switch 124
Core V cathode voltage is supplied in the state of differential amplifier 126A with cathode voltage, can suppress consumed battery electricity
Pressure.
Thus, according to the detection circuit 26 of each embodiment, low consumption electric current and miniaturization can be realized.
Moreover, according to the detection circuit 26 of each embodiment, compared with conventional detection circuit 126, can replace
Two comparators (A0, C0) and only realized with a comparator CMP0, therefore, it is possible to further miniaturization.
Moreover, according to the detection circuit 26 of each embodiment, can according to capacitor C1~C4 capacity ratio come pair
Comparator CMP0 set detection threshold value voltage Vn_th, therefore, it is possible to reduce each capacitor C1~C4 electric capacity its own.Therefore,
According to the detection circuit 26 of each embodiment, can further it minimize.
Moreover, in conventional detection circuit 126, when using circuit 126 is detected to carry out detection operation, due to electric current stream
The switch SW of battery core selecting switch 124 through conducting state, therefore in order to reduce the conducting resistance of battery core selecting switch 124, must
It must amplify.On the other hand, according to the detection circuit 26 of each embodiment, in the charge state by charge charging to electricity
After container C1~C4, the detection of cell voltage is carried out under relatively state, therefore leading for battery core selecting switch 24 can not be considered
Be powered resistance.Thus, according to the detection circuit 26 of each embodiment, the size of battery core selecting switch 24 can be reduced.
In addition, however it is not limited to the detection circuit 26 of each embodiment, for example also it can be combined using each embodiment
Detect the structure of circuit 26.For example, the 2nd embodiment can also be combined with the 3rd embodiment and be configured to switching
Into multiple reference voltage VsREFAnd allow hand over as the different capacitor of capacity ratio (C3, C3 ' and C4, C4 ') detection circuit 26.
Moreover, can also have the work(of the microcomputer 16 described in each embodiment by chip internal control portion 30
Energy.For example, chip internal control portion 30 also can directly control battery core selecting switch 24 and detection circuit 26.Now, battery cell monitoring system
System 10 can not also possess microcomputer 16.
Moreover, in each embodiment, to the detection electricity of the battery cell monitoring LSI14 suitable for battery monitor system 10
Road 26 is illustrated, but be applicable detection circuit 26 device be not limited to present embodiment, as long as detection two-terminal between
Voltage detection means it is just applicable.
Moreover, in each embodiment, the situation that detection circuit 26 possesses capacitor C1~C4 is illustrated, but
Capacitor C1~C4 part or all of position arranged is not limited in detection circuit 26.For example, can also be disposed in
In the region outside detection circuit 26 in battery cell monitoring LSI 14, moreover, for example can also be disposed in outside battery cell monitoring LSI 14, and
It is connected via terminal etc. with detection circuit 26.
Moreover, battery monitor system 10 illustrated in other each embodiments and battery cell monitoring LSI 14 knot
Structure and action be one, can be changed without departing from the scope of the subject in the invention according to situation certainly.
Claims (11)
1. a kind of semiconductor device, it is characterised in that including：
1st capacitor group, comprising the 1st capacitor and the 2nd capacitor, one end of the 1st capacitor is changeable to be connected to battery
A wherein pole in the positive pole and negative pole of battery core, one end of the 2nd capacitor is changeable to be connected to and the 1st capacitor institute
Extremely opposite another pole of connection；
Comparing section, possesses the 1st input terminal that the battery battery core can be connected to via the 1st capacitor and can be via
2nd capacitor and the 2nd input terminal for being connected to the battery battery core, to the battery electricity of the battery battery core connected
Pressure is compared with defined detection voltage；And
2nd capacitor group, comprising the 3rd capacitor and the 4th capacitor, the 3rd capacitor is in first node and the 1st switching device
Between, it is connected in series with the 1st switching device, the 4th capacitor is and described between second node and the 2nd switching device
2nd switching device is connected in series, wherein the first node is located at the 1st capacitor and the 1st input of the comparing section
Between terminal, the 1st switching device switching and ground voltage supplies and an at least reference voltage source comprising supply ground voltage
In the connection status of any one, the second node is located at the 2nd input of the 2nd capacitor and the comparing section
Between son, the 2nd switching device switching and any one in the ground voltage supplies and an at least reference voltage source
Connection status.
2. semiconductor device according to claim 1, it is characterised in that also include：
One end switching of 1st capacitor, can be connected to the 1st input terminal of the comparing section by the 3rd switching device
Any one of and defined reference voltage source；And
One end switching of 2nd capacitor, can be connected to the 2nd input terminal of the comparing section by the 4th switching device
Any one of and the defined reference voltage source.
3. semiconductor device according to claim 1 or 2, it is characterised in that also include：
Switching device group, comprising the 5th switching device and the 6th switching device, the 5th switching device can be by the 1st capacitor
One end switching be connected to a wherein pole in the positive pole of the battery battery core and negative pole, the 6th switching device can will described in
One end switching of 2nd capacitor is connected to the extremely opposite another pole connected with the 1st capacitor of the battery battery core.
4. semiconductor device according to claim 3, it is characterised in that
The comparing section is directed to each battery battery core for the multiple battery battery cores being connected in series, to the cell voltage and the rule
Fixed detection voltage is compared,
The switching device group includes the 5th switching device and institute for each battery battery core of the multiple battery battery core
State the 6th switching device.
5. semiconductor device according to any one of claim 1 to 4, it is characterised in that
Detection voltage as defined in described is according to the 1st capacitor, the 2nd capacitor, the 3rd capacitor and described the
The capacity ratio of each electric capacity of 4 capacitors is determined.
6. semiconductor device according to any one of claim 1 to 5, it is characterised in that
3rd capacitor has the different multiple capacitors of electric capacity,
The semiconductor device also includes the 7th switching device, and first node switching can be connected to by the 7th switching device
The respective either end of multiple capacitors of 3rd capacitor.
7. semiconductor device according to any one of claim 1 to 6, it is characterised in that
4th capacitor has the different multiple capacitors of electric capacity,
The semiconductor device also includes the 8th switching device, and second node switching can be connected to by the 8th switching device
The respective either end of multiple capacitors of 4th capacitor.
8. semiconductor device according to any one of claim 1 to 7, it is characterised in that also include：
Control unit, carries out following controls, i.e. make described in supply by the 1st switching device and the 2nd switching device
The ground voltage supplies of ground voltage and reference voltage source, an other end and the 4th electric capacity with the 3rd capacitor
In the state of the other end connection of device after the stipulated time, made by the 1st switching device and the 2nd switching device
The ground voltage supplies and reference voltage source being connected with the other end of the 3rd capacitor and the other end of the 4th capacitor are not
The other end of same ground voltage supplies and reference voltage source, the other end with the 3rd capacitor and the 4th capacitor connects
Connect.
9. semiconductor device according to any one of claim 1 to 8, it is characterised in that also include：
Test section, the cell voltage of the battery battery core is detected based on the level of the signal exported from the comparing section
State.
10. a kind of battery monitor system, it is characterised in that including：
The multiple batteries being connected in series；And
Semiconductor device, including：
1st capacitor group, comprising the 1st capacitor and the 2nd capacitor, one end of the 1st capacitor is changeable to be connected to battery
A wherein pole in the positive pole and negative pole of battery core, one end of the 2nd capacitor is changeable to be connected to and the 1st capacitor institute
Extremely opposite another pole of connection；
Comparing section, possesses the 1st input terminal that the battery battery core can be connected to via the 1st capacitor and can be via
2nd capacitor and the 2nd input terminal for being connected to the battery battery core, to the battery electricity of the battery battery core connected
Pressure is compared with defined detection voltage；
2nd capacitor group, comprising the 3rd capacitor and the 4th capacitor, the 3rd capacitor is in first node and the 1st switching device
Between, it is connected in series with the 1st switching device, the 4th capacitor is and described between second node and the 2nd switching device
2nd switching device is connected in series, wherein the first node is located at the 1st capacitor and the 1st input of the comparing section
Between terminal, the 1st switching device switching and ground voltage supplies and an at least reference voltage source comprising supply ground voltage
In the connection status of any one, the second node is located at the 2nd input of the 2nd capacitor and the comparing section
Between son, the 2nd switching device switching and any one in the ground voltage supplies and an at least reference voltage source
Connection status；
Switching device group, comprising the 5th switching device and the 6th switching device, the 5th switching device can be by the 1st capacitor
One end switching be connected to a wherein pole in the positive pole of the battery battery core and negative pole, the 6th switching device can will described in
One end switching of 2nd capacitor is connected to the extremely opposite another pole connected with the 1st capacitor of the battery battery core；
And
Control unit, carries out following controls, i.e. make described in supply by the 1st switching device and the 2nd switching device
The ground voltage supplies of ground voltage and reference voltage source, an other end and the 4th electric capacity with the 3rd capacitor
In the state of the other end connection of device after the stipulated time, made by the 1st switching device and the 2nd switching device
The ground voltage supplies and reference voltage source being connected with the other end of the 3rd capacitor and the other end of the 4th capacitor are not
The other end of same ground voltage supplies and reference voltage source, the other end with the 3rd capacitor and the 4th capacitor connects
Connect.
11. a kind of detection method, is the detection method of the cell voltage by semiconductor device, battery battery core, described partly to lead
Body device includes：1st capacitor group, includes the 1st capacitor and the 2nd capacitor, the changeable connection in one end of the 1st capacitor
A wherein pole into the positive pole and negative pole of the battery battery core, one end of the 2nd capacitor is changeable be connected to it is described
Extremely opposite another pole that 1st capacitor is connected；Comparing section, the electricity can be connected to via the 1st capacitor by possessing
1st input terminal of pond battery core and the 2nd input terminal that the battery battery core can be connected to via the 2nd capacitor, it is right
The cell voltage of the battery battery core connected is compared with defined detection voltage；And the 2nd capacitor group, bag
Containing the 3rd capacitor and the 4th capacitor, the 3rd capacitor is between first node and the 1st switching device, with the described 1st switching
Element is connected in series, and the 4th capacitor is between second node and the 2nd switching device, company of being connected with the 2nd switching device
Connect, wherein the first node is located between the 1st capacitor and the 1st input terminal of the comparing section, the described 1st
Switching device switches and the ground voltage supplies comprising supply ground voltage and the connection of any one in an at least reference voltage source
State, the second node is located between the 2nd capacitor and the 2nd input terminal of the comparing section, and the described 2nd cuts
Change element switching and the connection status of any one in the ground voltage supplies and an at least reference voltage source, the inspection
Survey method is characterised by including following processing：
By the 1st switching device and the 2nd switching device, by supply the ground voltage the ground voltage supplies and
One reference voltage source, it is connected with the 3rd capacitor and the 4th capacitor,
After the stipulated time, by the 1st switching device and the 2nd switching device, will with the 3rd capacitor and
The ground voltage supplies and the different ground voltage supplies of reference voltage source and reference voltage source of 4th capacitor connection, with it is described
3rd capacitor and the 4th capacitor are connected.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2016-089658 | 2016-04-27 | ||
| JP2016089658A JP6767769B2 (en) | 2016-04-27 | 2016-04-27 | Semiconductor devices, battery monitoring systems, and detection methods |
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| Publication Number | Publication Date |
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| CN107315107A true CN107315107A (en) | 2017-11-03 |
| CN107315107B CN107315107B (en) | 2020-11-27 |
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| CN201710284961.3A Active CN107315107B (en) | 2016-04-27 | 2017-04-26 | Semiconductor device, battery monitoring system and detection method |
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| US (1) | US10228423B2 (en) |
| JP (1) | JP6767769B2 (en) |
| CN (1) | CN107315107B (en) |
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| CN109669144A (en) * | 2017-10-13 | 2019-04-23 | 矢崎总业株式会社 | The method of secondary cell state detector and detection secondary cell state |
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| KR102256602B1 (en) * | 2017-12-14 | 2021-05-26 | 주식회사 엘지에너지솔루션 | Apparatus and method for measuring voltage |
| US10491204B1 (en) * | 2018-07-26 | 2019-11-26 | Texas Instruments Incorporated | Programmable time-division multiplexed comparator |
| JP7345497B2 (en) | 2018-11-22 | 2023-09-15 | 株式会社半導体エネルギー研究所 | battery pack |
| US20220052387A1 (en) * | 2018-12-20 | 2022-02-17 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and battery pack |
| DE102019103277A1 (en) * | 2019-02-11 | 2020-08-13 | Dr. Ing. H.C. F. Porsche Aktiengesellschaft | Cell module and method for operating the cell module |
| KR20220100332A (en) * | 2021-01-08 | 2022-07-15 | 주식회사 엘지에너지솔루션 | Battery apparatus and method of supplying voltage |
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Also Published As
| Publication number | Publication date |
|---|---|
| JP6767769B2 (en) | 2020-10-14 |
| US10228423B2 (en) | 2019-03-12 |
| JP2017198546A (en) | 2017-11-02 |
| US20170315176A1 (en) | 2017-11-02 |
| CN107315107B (en) | 2020-11-27 |
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