CN107305896B - The preparation method of semiconductor devices - Google Patents
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- CN107305896B CN107305896B CN201610256875.7A CN201610256875A CN107305896B CN 107305896 B CN107305896 B CN 107305896B CN 201610256875 A CN201610256875 A CN 201610256875A CN 107305896 B CN107305896 B CN 107305896B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
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Abstract
The present invention provides a kind of preparation method of semiconductor devices; at least one layer of ONO laminated construction is first formed by alternating deposit oxide layer and nitration case in semi-conductive substrate; then the ONO laminated construction is etched and forms channel through-hole; then one layer of medium protective layer is formed in channel through-hole surfaces; the constant corrosion in subsequent wet technique of ONO laminated construction is protected using medium protective layer; to guarantee the width of the channel through-hole obtained and its flatness of sidewall surfaces, the performance and yield of device are improved.
Description
Technical field
The present invention relates to semiconductor device processing technology field more particularly to a kind of preparation methods of semiconductor devices.
Background technique
With the development of plane flash memories, the production technology of semiconductor achieves huge progress.But recently
Several years, the development of plane flash memory encountered various challenges: physics limit, the existing developing technique limit and storage electron density
Limit etc..In this context, to solve the difficulty that encounters of planar flash memory and pursue being produced into for lower unit storage unit
This, a variety of different three-dimensional (3D) flash memories structures are come into being, such as 3D NAND-flash memory.3D nand flash memory
Memory is a kind of novel product based on plane nand flash memory, the main characteristics of this product multi-layer data that has been vertical stacking
Plane result is converted stereochemical structure by storage unit, can create memory capacity than similar NAND technology and be up to depositing for several times
Store up equipment.The technology can be supported to receive more high storage capacity in smaller space content, and then bring very big cost savings, energy consumption
It reduces, and significantly need of the performance boost to meet numerous consumer mobile devices comprehensively and most harsh enterprise is required to dispose
It asks.
Industry typical 3D nand memory part at present, usually its memory cell of arrangement in the row direction perpendicular to
Semiconductor substrate and stack, so its structure includes the vertical-channel for being substantially perpendicular to semiconductor substrate, specific manufacturer
Method include the following:
Figure 1A is please referred to, firstly, the two layer shape different by alternating deposit dielectric constant over the semiconductor substrate 10
At multi-layer laminate structure 11 (such as oxide 111 and the alternate multiple ONO structures of nitride 112), the multi-layer laminate structure
11 can be used for being subsequently formed the charge storage layer of each memory transistor in 3D nand memory part memory array；
Then, the multi-layer laminate structure 11 in semiconductor substrate 10 is etched by anisotropic dry etch process
It is formed along the distribution of memory cell wordline (WL) extending direction, perpendicular to multiple channel through-holes on 10 surface of semiconductor substrate
12,12 bottom of channel through-hole goes directly and 10 surface of semiconductor substrate or has certain over etching, and each channel through-hole 12 can use
In the pipe gate and polysilicon gate of each memory transistor formed in 3D nand memory part memory array；
Then, formed on 10 surface of semiconductor substrate of each 12 bottom of channel through-hole certain thickness silicon epitaxial layers with
It is filled in each channel through-hole 12, the silicon epitaxial layers are used as each storage in 3D nand memory part memory array
The pipe gate of device transistor.Usually 12 bottom of channel through-hole 10 surface of semiconductor substrate carry out epitaxial silicon growth it
Before, need to remove oneself on 10 surface of semiconductor substrate of 12 bottom of channel through-hole come wet process using corrosive liquids such as diluted HF acid
Right oxide.
Due in above process, removing the semiconductor that 12 bottom-exposed of channel through-hole goes out using wet-cleanings such as HF acid solutions
While natural oxide on substrate 10, the oxide 111 in laminated construction 11 that 12 side wall of channel through-hole exposes also can
Fallen by partial corrosion, this can cause the width of channel through-hole to become larger, while cause the 12 sidewall surfaces out-of-flatness of channel through-hole, in turn
The filling effect for influencing filler in subsequent channel through-hole 12 causes device performance and yield to decline.
Therefore, it is necessary to the preparation methods to the current semiconductor devices such as 3D NAND with multi-layer laminate structure
It is improved further, to eliminate the above problem.
Summary of the invention
The purpose of the present invention is to provide a kind of preparation method of semiconductor devices, it can guarantee the channel through-hole obtained
The flatness of width and its sidewall surfaces improves the performance and yield of device.
To solve the above problems, the present invention proposes a kind of preparation method of semiconductor devices, comprising the following steps:
There is provided semi-conductive substrate, on the semiconductor substrate by alternating deposit oxide layer and nitration case formed to
Few one layer of ONO laminated construction；
ONO laminated construction in the semiconductor substrate is performed etching, to be formed along semiconductor substrate cross direction profiles and
Perpendicular to multiple channel through-holes of the semiconductor substrate surface；
One layer of medium protective layer is formed in the entire semiconductor device surface comprising the channel through-hole；
Etching removes the medium protective layer of the channel via bottoms, to expose described the half of the channel via bottoms
Conductor substrate surface, and retain the medium protective layer of the channel through-hole side wall；
Wet-cleaning is carried out to the channel via bottoms, to remove the semiconductor substrate of the channel via bottoms
The natural oxide on surface；And
After the medium protective layer for removing the channel through-hole side wall, in the semiconductor of each channel via bottoms
Certain thickness extension conductive layer is formed on substrate surface.
Further, before being performed etching to the ONO laminated construction in the semiconductor substrate, also to the ONO lamination
Structure carries out silicon doping.
Further, it is formed on the semiconductor substrate between the ONO laminated construction, first in the semiconductor substrate
One layer of etching barrier layer is formed on surface.
Further, the etching barrier layer is silicon nitride layer or silicon oxynitride layer.
Further, when performing etching to the ONO laminated construction in the semiconductor substrate, the etching goes directly described half
Conductor substrate surface has certain over etching.
Further, using plasma dry etch process carries out the ONO laminated construction in the semiconductor substrate
Etching.
Further, it in the plasma dry etch process, is generated using fluorocarbon gases, nitrogen and fluorine nitrogen
Plasma needed for etching；Or using hydrogen, bromination hydrogen and gas of nitrogen trifluoride and include appropriate hydrocarbon gas, fluorohydrocarbon gas
At least any one in body and fluorocarbon gas etches required plasma to generate.
Further, the fluorocarbon gases are CH2F2Gas, CH3F gas or CHF3Gas；The fluorocarbon gas
Body is C4F6Gas, C4F8Gas or CF4Gas.
Further, the medium protective layer is silicon nitride layer or silicon oxynitride layer, using chemical vapor deposition process or
Person's atom layer deposition process is formed, and technological temperature is 100 DEG C~600 DEG C, with a thickness of
Further, the medium protective layer of the channel via bottoms is removed using dry etch process etching.
Further, the process gas of the use in the dry etch process includes carbon fluorine base gas, oxidizing gas
And dilution property gas.
Further, the carbon fluorine base gas is selected from CHF3、CH2F2And CH3At least one in F；The oxidizing gas choosing
From CO, O2In at least one；The dilution property gas is Ar.
Further, the natural oxygen of semiconductor substrate surface in the channel via bottoms is removed with HF wet corrosion technique
Compound.
Further, the channel is removed using hot phosphoric acid wet corrosion technique or SiCoNi pre-cleaning processes wet process to lead to
The medium protective layer of hole side wall.
Further, one layer is formed in the entire device surface comprising the channel through-hole using chemical vapor deposition process
Extension conductive layer, and etch and remove extra extension conductive layer, to retain the extension conductive layer being filled in the channel through-hole.
Further, using selective epitaxial growth process each channel via bottoms semiconductor substrate surface
It is upper to form certain thickness extension conductive layer.
Further, the extension conductive layer is pure silicon layer, germanium silicon layer or carbon silicon layer.
Further, the semiconductor devices is 3D nand flash memory device.
Further, the extension conductive layer is the pipe gate of the 3D nand flash memory device.
Compared with prior art, the preparation method of semiconductor devices of the invention, the ONO in etching semi-conductive substrate
Laminated construction and formed after channel through-hole, first the channel through-hole surfaces formed one layer of medium protective layer, then using be situated between
The high etching selection ratio between natural oxide on quality guarantee sheath and channel via bottoms semiconductor substrate surface, it is sudden and violent to etch
Expose natural oxide described in natural oxide and the protection wet-cleaning on the semiconductor substrate surface of channel via bottoms
The oxide of channel through-hole side wall in the process, and further using between medium protective layer and the oxide of channel through-hole side wall
High etching selection ratio, come guarantee the medium protective layer on channel through-hole side wall removing after obtain channel through-hole final width
The flatness of degree and its sidewall surfaces, to improve the performance and yield of device.
Detailed description of the invention
Figure 1A to 1B is the device architecture diagrammatic cross-section in a kind of 3D nand memory manufacturing process in the prior art；
Fig. 2 is the preparation method flow chart of the semiconductor devices of the specific embodiment of the invention；
Fig. 3 A to Fig. 3 E is that the device architecture section in the preparation method of the semiconductor devices of the specific embodiment of the invention shows
It is intended to.
Specific embodiment
To be clearer and more comprehensible the purpose of the present invention, feature, a specific embodiment of the invention is made with reference to the accompanying drawing
Further instruction, however, the present invention can be realized with different forms, it should not be to be confined to the embodiment described.
Referring to FIG. 2, the present invention proposes a kind of preparation method of semiconductor devices, comprising the following steps:
S21 provides semi-conductive substrate, passes through alternating deposit oxide layer and nitration case shape on the semiconductor substrate
At at least one layer of ONO laminated construction；
S22 performs etching the ONO laminated construction in the semiconductor substrate, is laterally divided with being formed along semiconductor substrate
Cloth and multiple channel through-holes perpendicular to the semiconductor substrate surface；
S23 forms one layer of medium protective layer in the entire semiconductor device surface comprising the channel through-hole；
S24, etching removes the medium protective layer of the channel via bottoms, to expose the institute of the channel via bottoms
Semiconductor substrate surface is stated, and retains the medium protective layer of the channel through-hole side wall；
S25 carries out wet-cleaning to the channel via bottoms, to remove the semiconductor of the channel via bottoms
The natural oxide of substrate surface；
S26, after the medium protective layer for removing the channel through-hole side wall, the half of each channel via bottoms
Certain thickness extension conductive layer is formed on conductor substrate surface.
Fig. 3 A is please referred to, the semiconductor substrate 30 provided in the step s 21 can be silicon monocrystalline substrate, germanium single crystal substrate or silicon
Germanium single crystal substrate.Alternatively, also silicon can be laminated for silicon-on-insulator (SOI) substrate, on insulator in semiconductor substrate 30
(SSOI), on insulator be laminated SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI), germanium on insulator (GeOI),
Substrate, compound semiconductor substrate or the alloy semiconductor substrate of silicon upper epitaxial layer structure, the compound semiconductor substrate packet
Include silicon carbide, GaAs, gallium phosphide, indium phosphide, indium arsenide or dysprosium indium, the alloy semiconductor substrate include SiGe,
GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP or their combination, the SOI substrate include that setting exists
Semiconductor layer (such as silicon layer, germanium silicon layer, carbon silicon layer or germanium layer) on insulating layer, the dielectric protection layer are arranged in semiconductor layer
On transistor.By chemical vapor deposition (ChemicalVaporDeposition, CVD) technique in the semiconductor substrate
Replace deposition oxide (O) 311, nitride (N) 312 on 30, to form at least one layer of oxide (O)-nitride (N)-oxygen
It is folded to show the three layers of ONO formed in semiconductor substrate 30 in Fig. 3 A for compound (O) laminated construction 31, i.e. ONO laminated construction 31
Layer structure 31.In the present embodiment, for the monitoring of subsequent etching precision, ONO laminated construction 31 is formed in semiconductor substrate 30
Before, one layer of etching barrier layer 310 is first formed on 30 surface of semiconductor substrate, the etching barrier layer 310 can be nitridation
Silicon or silicon oxynitride, are formed by chemical vapor deposition process.
Further, in order to improve the performance of the subsequent channel through-hole finally obtained, can using ion implantation technology or
Person original position doping process carries out Si doping to the nitride 312 in the ONO laminated construction 31 and is used for improving its compactness
Nitride 312 in the ONO laminated construction 31 described in subsequent etching process is not etched damage.
Fig. 3 B is please referred to, in step S22, (is not schemed firstly, forming a patterned mask layer on ONO laminated construction 31
Show), which can be photoresist or silicon nitride etc., define the position of each channel through-hole to be formed
It sets and size；Then, using the patterned mask layer as exposure mask, using plasma dry etch process is to the semiconductor substrate
ONO laminated construction 31 on 30 carries out high-aspect-ratio (High Aspect Ratio along the direction perpendicular to semiconductor substrate 30
Process, HARP) etching, the etching go directly 30 surface of semiconductor substrate or have certain over etching, thus in ONO
It is formed in laminated construction 31 and laterally (i.e. the direction wordline WL in Fig. 3 C) is distributed and is partly led perpendicular to described along semiconductor substrate 30
Multiple channel through-holes 32 on 30 surface of body substrate.Wherein, in the plasma dry etch process, fluorohydrocarbon gas can be used
Plasma needed for body, nitrogen and fluorine nitrogen generate etching, can also use hydrogen, bromination hydrogen and Nitrogen trifluoride
Gas and comprising at least any one in appropriate hydrocarbon gas, fluorocarbon gases and fluorocarbon gas come generate etching needed for etc. from
Daughter, the fluorocarbon gases are CH2F2Gas, CH3F gas or CHF3Gas, the fluorocarbon gas are C4F6Gas,
C4F8Gas or CF4Gas.The diameter range of the channel through-hole 32, i.e. width are 20nm~100nm.
Please refer to Fig. 3 C, in step S23, using atom layer deposition process (Atomic Layer Deposition,
ALD) or chemical vapor deposition (CVD) technique is in entire device surface one layer of media protection of formation comprising the channel through-hole 32
Layer 33.The medium protective layer 33 in the ONO laminated construction 31 oxide 311, nitride 312 and subsequent expose
32 bottom of channel through-hole 30 surface of semiconductor substrate on the natural oxide that is formed compare, all have high etching selection ratio.
The medium protective layer 33 can be silicon nitride layer or silicon oxynitride layer, and deposition process temperature is 100 DEG C~600 DEG C, with a thickness ofIts compactness is low compared to the nitride 312 in ONO laminated construction 31.The medium protective layer 33 is used for subsequent
32 side wall of channel through-hole is protected in the wet cleaning processes of step S24.
Fig. 3 D is please referred to, in step s 24, using plasma dry etch process etches Jie of 32 bottom of channel through-hole
Quality guarantee sheath 33 is also remained on 32 side wall of channel through-hole with exposing 30 surface of semiconductor substrate of 32 bottom of channel through-hole
Medium protective layer 33 is to protect ONO laminated construction 31.The process gas of use in the dry plasma etch technique includes carbon
Fluorine base gas, oxidizing gas and dilution property gas, the carbon fluorine base gas can be selected from CHF3、CH2F2And CH3In F at least
One；The oxidizing gas can be selected from CO, O2In at least one；The dilution property gas is Ar.
Please continue to refer to Fig. 3 D, in step s 25, it is sudden and violent that 32 bottom of channel through-hole is removed using HF wet corrosion technique
The natural oxide on 30 surface of semiconductor substrate of exposing, the natural oxide be after step S24 due to expose half
The semiconductor materials such as the silicon on 30 surface of conductor substrate react with the oxygen chemical gas in locating atmosphere and are formed.The HF is wet
The solution that method etching process uses includes diluted hydrofluoric acid (HF), and the mass concentration of the hydrofluoric acid is 0.1%~50%, described dilute
The temperature range of hydrofluoric acid is 5 DEG C~80 DEG C.In the present embodiment, the solution that the HF wet corrosion technique uses can be selected often
BOE or BHF of rule etc., the BOE and BHF are comprising ammonium fluoride (NH4F) and the fluorochemical of hydrofluoric acid (HF) is molten
Ammonium fluoride (NH in liquid, BOE and BHF4F) and the content of hydrofluoric acid (HF) is than different, but concrete content can be according to partly leading than
The natural oxide degree on body substrate surface 30 is chosen.In the step, due to the oxide 311 in 32 side wall of channel through-hole
It is protected by medium protective layer 33, in HF wet etching pendular ring border, corrosion rate can be much smaller than 32 bottom of channel through-hole
30 surface of semiconductor substrate natural oxide, therefore on 30 surface of semiconductor substrate for removing 32 bottom of channel through-hole
Natural oxide during, the side wall of the channel through-hole 32 will not be affected substantially, and flatness is higher, and channel through-hole
32 width (i.e. diameter) is basically unchanged, and is required so as to reach device manufacture.
Fig. 3 E is please referred to, in step S26, firstly, pre- clear using hot phosphoric acid (HPO) wet corrosion technique or SiCoNi
It washes technique wet process and removes the remaining medium protective layer of 32 side wall of channel through-hole, wherein due to the medium protective layer 33
Compactness ratio ONO laminated construction 31 in nitride 312 it is low, therefore in hot phosphoric acid wet etching pendular ring border, the medium
Protective layer 33 compared in ONO laminated construction 31 oxide 311 and nitride 312 all have higher etching ratio, be easy from ditch
The removing of 32 side wall of road through-hole, and 32 side wall of channel through-hole will not be caused to corrode, to ensure that the channel through-hole finally obtained
32 sidewall surfaces flatness and the width (i.e. diameter) of channel through-hole 32.It, then can be using chemical gas in step S26
Phase depositing operation forms one layer of extension conductive layer 34 in the entire device surface comprising the channel through-hole 32, then etching removal
Extra extension conductive layer 34, only to retain the extension conductive layer being filled in the channel through-hole 32.The chemical vapor deposition
SiH can be used in product technique4, DCS and Si2H6One of or it is a variety of be used as silicon source, to form the extension conductive layer 34.
In step S26, selective epitaxial growth process, the directly semiconductor in each 32 bottom of channel through-hole can also be used
Form certain thickness extension conductive layer 34 on 30 surface of substrate, it, can be in process warm in the selective epitaxial growth process
Under the conditions of degree is 500 DEG C~900 DEG C, SiH is used4(monosilane), DCS (dichlorosilane) and Si2H6One of (disilane)
Or it is a variety of as silicon source, use GeH4(germane) is used as ge source, and uses B2H6(diborane) is used as boron source, to form germanium silicon
Layer is as the extension conductive layer 34.
Semiconductor devices manufactured in the present embodiment can be 3D nand flash memory device, and the extension formed in step S26 is conductive
Layer 34 can be used as the pipe gate of the 3D nand flash memory device.
The preparation method of the semiconductor devices of the present embodiment, ONO laminated construction 31 on etch semiconductor substrates 30 and
It is formed after channel through-hole 32, first one layer of medium protective layer 33 is formed on 32 surface of channel through-hole, to protect channel through-hole
The oxide of 32 side walls wet process removal 32 base semiconductor substrate of channel through-hole, 30 surface on natural oxide during not
Corroded, thus finally ensure that the flatness of 32 width of channel through-hole and its sidewall surfaces, to greatly improve the property of device
Energy and yield.
Obviously, those skilled in the art can carry out various modification and variations without departing from spirit of the invention to invention
And range.If in this way, these modifications and changes of the present invention belong to the claims in the present invention and its equivalent technologies range it
Interior, then the present invention is also intended to include these modifications and variations.
Claims (18)
1. a kind of preparation method of semiconductor devices, which comprises the following steps:
Semi-conductive substrate is provided, forms at least one by alternating deposit oxide layer and nitration case on the semiconductor substrate
Layer ONO laminated construction, and silicon doping is carried out to the ONO laminated construction；
ONO laminated construction in the semiconductor substrate is performed etching, to be formed along semiconductor substrate cross direction profiles and vertical
In multiple channel through-holes of the semiconductor substrate surface；
One layer of medium protective layer is formed in the entire semiconductor device surface comprising the channel through-hole, the medium protective layer
Compactness is low compared to the nitration case in the ONO laminated construction；
Etching removes the medium protective layer of the channel via bottoms, to expose the semiconductor of the channel via bottoms
Substrate surface, and retain the medium protective layer of the channel through-hole side wall；
Wet-cleaning is carried out to the channel via bottoms, to remove the semiconductor substrate surface of the channel via bottoms
Natural oxide；And
After the medium protective layer for removing the channel through-hole side wall, in the semiconductor substrate of each channel via bottoms
Certain thickness extension conductive layer is formed on surface.
2. the preparation method of semiconductor devices as described in claim 1, which is characterized in that formed on the semiconductor substrate
Before the ONO laminated construction, one layer of etching barrier layer is first formed on the semiconductor substrate surface.
3. the preparation method of semiconductor devices as claimed in claim 2, which is characterized in that the etching barrier layer is silicon nitride
Layer or silicon oxynitride layer.
4. the preparation method of semiconductor devices as claimed any one in claims 1 to 3, which is characterized in that partly led to described
When ONO laminated construction in body substrate performs etching, it is described etching go directly the semiconductor substrate surface or have certain mistake
Etching.
5. the preparation method of semiconductor devices as described in claim 1, which is characterized in that using plasma dry etching work
Skill performs etching the ONO laminated construction in the semiconductor substrate.
6. the preparation method of semiconductor devices as claimed in claim 5, which is characterized in that the plasma dry etch work
In skill, plasma needed for generating etching using fluorocarbon gases, nitrogen and fluorine nitrogen；Or use hydrogen, hydrogen bromide
It gas and gas of nitrogen trifluoride and generates comprising at least any one in appropriate hydrocarbon gas, fluorocarbon gases and fluorocarbon gas
Plasma needed for etching.
7. the preparation method of semiconductor devices as claimed in claim 6, which is characterized in that the fluorocarbon gases are CH2F2Gas
Body, CH3F gas or CHF3Gas；The fluorocarbon gas is C4F6Gas, C4F8Gas or CF4Gas.
8. the preparation method of semiconductor devices as described in claim 1, which is characterized in that the medium protective layer is silicon nitride
Layer or silicon oxynitride layer, formed using chemical vapor deposition process or atom layer deposition process, technological temperature be 100 DEG C~
600 DEG C, with a thickness of
9. the preparation method of semiconductor devices as described in claim 1, which is characterized in that gone using dry etch process etching
Except the medium protective layer of the channel via bottoms.
10. the preparation method of semiconductor devices as claimed in claim 9, which is characterized in that in the dry etch process
The process gas of use includes carbon fluorine base gas, oxidizing gas and dilution property gas.
11. the preparation method of semiconductor devices as claimed in claim 10, which is characterized in that the carbon fluorine base gas is selected from
CHF3、CH2F2And CH3At least one in F；The oxidizing gas is selected from CO, O2In at least one；The dilution property gas is
Ar。
12. the preparation method of semiconductor devices as described in claim 1, which is characterized in that removed with HF wet corrosion technique
The natural oxide of semiconductor substrate surface in the channel via bottoms.
13. the preparation method of semiconductor devices as described in claim 1, which is characterized in that use hot phosphoric acid wet etching work
Skill or SiCoNi pre-cleaning processes wet process remove the medium protective layer of the channel through-hole side wall.
14. the preparation method of semiconductor devices as described in claim 1, which is characterized in that use chemical vapor deposition process
One layer of extension conductive layer is formed in the entire device surface comprising the channel through-hole, and etches and removes extra extension conduction
Layer, to retain the extension conductive layer being filled in the channel through-hole.
15. the preparation method of semiconductor devices as described in claim 1, which is characterized in that use selective epitaxial growth work
Skill forms certain thickness extension conductive layer on the semiconductor substrate surface of each channel via bottoms.
16. the preparation method of semiconductor devices as described in claim 1, which is characterized in that the extension conductive layer is pure silicon
Layer, germanium silicon layer or carbon silicon layer.
17. the preparation method of semiconductor devices as described in claim 1, which is characterized in that the semiconductor devices is 3D
Nand flash memory device.
18. the preparation method of semiconductor devices as claimed in claim 17, which is characterized in that the extension conductive layer is described
The pipe gate of 3D nand flash memory device.
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| CN107731735B (en) * | 2017-11-21 | 2020-02-14 | 长江存储科技有限责任公司 | SEG preparation process for improving SEG growth form through mild wet etching |
| CN109192731B (en) * | 2018-08-27 | 2021-04-13 | 长江存储科技有限责任公司 | Manufacturing method of three-dimensional memory and three-dimensional memory |
| CN109496359B (en) | 2018-10-08 | 2020-04-28 | 长江存储科技有限责任公司 | Method for forming three-dimensional memory device with channel structure by using native oxide layer |
| KR102640185B1 (en) | 2018-10-09 | 2024-02-22 | 양쯔 메모리 테크놀로지스 씨오., 엘티디. | Method for reducing defects in semiconductor plugs in 3D memory devices |
| CN109904165B (en) * | 2019-01-31 | 2022-03-18 | 长江存储科技有限责任公司 | Manufacturing method of three-dimensional memory and three-dimensional memory |
| US11127760B2 (en) * | 2019-02-01 | 2021-09-21 | Applied Materials, Inc. | Vertical transistor fabrication for memory applications |
| CN110047749B (en) * | 2019-03-21 | 2020-12-18 | 中国电子科技集团公司第五十五研究所 | Method for removing silicon nitride in radio frequency LDMOS planarization process |
| EP3931868A4 (en) * | 2019-04-12 | 2023-01-04 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional memory device with deposited semiconductor plugs and methods for forming the same |
| CN117119786A (en) * | 2022-05-13 | 2023-11-24 | 长鑫存储技术有限公司 | Semiconductor structure, manufacturing method thereof and memory |
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