CN107301123A - A kind of signature arithmetic code error detection algorithm of table- driven - Google Patents
A kind of signature arithmetic code error detection algorithm of table- driven Download PDFInfo
- Publication number
- CN107301123A CN107301123A CN201710367340.1A CN201710367340A CN107301123A CN 107301123 A CN107301123 A CN 107301123A CN 201710367340 A CN201710367340 A CN 201710367340A CN 107301123 A CN107301123 A CN 107301123A
- Authority
- CN
- China
- Prior art keywords
- instruction
- node
- basic block
- cfid
- signature
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/362—Software debugging
- G06F11/3636—Software debugging by tracing the execution of the program
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/3604—Software analysis for verifying properties of programs
- G06F11/3612—Software analysis for verifying properties of programs by runtime analysis
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Software Systems (AREA)
- Management, Administration, Business Operations System, And Electronic Commerce (AREA)
Abstract
The invention discloses a kind of signature arithmetic code error detection algorithm of table- driven, the algorithm is theoretical based on finite-state automata（FSM）, in bivariate table（CFID tables）The information of middle storage controlling stream graph, goes out illegal instruction by the signature detection for comparing the signature in basic block and being stored in CFID tables and redirects.Illegal instruction for the non-detectable shared branch's fan-in node of CFCSS algorithms redirects mistake, and the present invention can successfully detect this kind of mistake.Experimental result shows that average error detection coverage rate of the present invention reaches 98.1%, and the error detection that the present invention is inserted in each basic block is instructed compared with less in CFCSS.
Description
Technical field
The present invention relates to pure software error detection techniques field, the signature error detection of specifically a kind of table- driven is calculated
Method (EDSS), applied to legal branch, illegal branch and the illegal branch with two shared branch's fan-in nodes
Deng error detection.
Background technology
With the development of technology, the improvement of microprocessor performance will be increasingly dependent on that volume is smaller, speed is brilliant faster
Body pipe, and low threshold voltage and stricter noise margin are realized simultaneously.However, this to improving performance, reducing power consumption
Conventional requirement but frequently results in the appearance of many integrity problems.The mistake frequently produced different from manufacture and design mistake etc.
By mistake, provisional mistake（Also often it is referred to as soft error）, come from the environment of electromagnetic interference, voltage glitch or high energy particle etc.
Influence, can frequently result in uncertain behavior.Most typical soft error is single-particle inversion（SEU）, the mistake refer to hair
Life is in sequential logic and single-event transients（SET）In bit flipping, tolerate that these mistakes are most primary and most important steps just
It is to detect these mistakes, considerable error detection techniques is had at present.
Error detection can be achieved by pure hardware mode, software and hardware combining mode and pure software mode.It is a kind of
Conventional pure hardware error detection mode has used house dog coprocessor, and the processor is by monitoring external bus and primary processor
Behavior, realizes concurrent system-level errors detection, but result in the increase of time and area overhead, and with inside
The extensive use of the microprocessor of cache and modern pipelining, this pure hardware error detection mode has seemed unnecessary
.Being currently used for the error detection mode of the software and hardware mixed type of error detection also has a lot, such as Argus and CRAFT.Argus bases
In von Neumann type processor core, it can detect that and input and output, exception, other mistakes of interrupt unit are removed in core.However, including
The control-flow detection signed by pure software（CFCSS）, control-flow detection by asserting（ACFC）, it is enhanced with what is asserted
Control-flow detection（ECCA）, pass through the error detection of redundant instruction（EDDI）Pure software processes method Deng including, than above-mentioned
It is more extensive that both concepts are used, because these pure software error detection modes do not require that specific hardware device provides support.
ACFC assigns each basic block one parity check bit in the process of implementation, can detect that parity error；EDDI passes through multiple
System instruction, and being verified by the suitable detection instruction of insertion, but this method be easily caused code capacity increase nearly 100% with
And the loss of aspect of performance.
The content of the invention
It is an object of the invention to provide a kind of signature arithmetic code error detection algorithm EDSS of table- driven, the algorithm uses CFID table energy
Detect illegally to redirect mistake in controlling stream graph, the requirement for using bivariate table is also relatively simple.When there is illegal redirect, lead to
The signature that detection assigns the destination node stored in variable R eg signature and table is crossed, controlling stream mistake can be detected reliably.Root
According to this method, illegal instruction redirects mistake and can also detected by the algorithm caused by shared more than two fan-in node.Should
Algorithm well solve legal branch, illegal branch and the illegal branch with two shared branch's fan-in nodes
Deng erroneous detection problem.
The object of the present invention is achieved like this：
A kind of signature arithmetic code error detection algorithm of table- driven, feature is that the detection algorithm includes step in detail below：
Step 1：All basic blocks, i.e. node are determined, program P controlling stream graph is set up, is each node serial number, i.e. basic block
Identification number, is started in controlling stream graph with natural number, i.e. vi, i=1,2 ... .N；
Step 2：A signature SSi is assigned to each node vi, if i ≠ j, SSi ≠ SSj, wherein i, j=1,2 ...
N；Each signature SSi is equal with the i in corresponding basic block identification vi；
Step 3：To each vi, i=1,2,3 ..., proceed as follows：
a）To each branch bri, j, its predecessor node is vi, and descendant node is vj；These branches are by a bivariate table
Represent, the bivariate table is referred to as CFID [i, j]；In the table, row i represents predecessor node, and row j represents descendant node；
b）If branch bri, j are in controlling stream graph, the signature SSj of descendant node is inserted into the corresponding positions of CFID [i, j]；
Otherwise CFID [i, j] position should insert 0 value；
c）The global variable stored in Reg registers basic block perform each time its detection instruction when all updates once, with
The change signed in track program process；
d）A decision instruction, " if SSi ≠ CFID [Reg, SSi] error else are inserted in the initial position of basic block
Reg=SSi ", that is, judge whether SSi and CFID [Reg, SSi] is equal, if equal, SSi is assigned into Reg, if not phase
Deng then reporting an error.
The bivariate table is a two-dimensional array, and the numerical value on correspondence i row j column positions is CFID [i, j], represents control
Station location marker in stream and redirect path；Line number value i represents the identification number of predecessor node, and columns value j represents the mark of present node
Knowledge number；
The basic block refers to a string of continuous instructions, and program is performed since first instruction in basic block, performed
Basic block is left after complete the last item instruction；In addition to the last item instruction in basic block is not required, its in basic block
Remaining instruction does not allow for branch instruction, jump instruction or call instruction.
The controlling stream graph by node set V=v1, v2 ..., vi ... vn } and set of paths E=e1, e2 ...,
Ei ..., em } constitute, controlling stream graph accurate description program P controlling stream, i.e. program P is expressed as P={ V, E }；One node vi table
Show a basic block, wherein i is positive integer, represents the position of basic block in a program；One paths represent point from vi to vj
Branch bri, j；Bri, j represent branch instruction, jump instruction, subroutine call instruction or return instruction.
The present invention is in the controlling stream error detection mode by software signature（CFCSS）On the basis of, it is proposed that one kind is based on table
The signature arithmetic code error detection algorithm of driving.The algorithm is theoretical based on finite-state automata（FSM）, in bivariate table（CFID tables）In
The information of controlling stream graph is stored, illegal finger is gone out by the signature detection for comparing the signature in basic block and being stored in CFID tables
Order is redirected.Illegal instruction for the non-detectable shared branch's fan-in node of CFCSS algorithms redirects mistake, the present invention (EDSS
Algorithm) it can successfully detect this kind of mistake.
The present invention is theoretical with reference to finite-state automata on the basis of CFCSS（FSM）With the general principle of controlling stream graph,
It is entirely different with the method that was previously used in CFCSS.During compiling, the pass between the information in controlling stream graph, including each node
System, is expressed by building a two dimension CFID table.The label of destination node in the legal path of controlling stream graph are store in table
Name.When there is illegal redirect, by detecting the signature of the destination node stored in the signature and table of assign variable R eg, control
Stream mistake can be detected reliably.
Beneficial effects of the present invention：
The present invention with CFID tables can detect in controlling stream graph it is illegal redirect mistake, and the requirement used bivariate table also compared with
To be simple.
The invention has the advantages that its terseness, in detection instruction, dynamic is calculated without the instruction of step-by-step xor operation
Signature, and only need to be compared operation on each basic block.
The present invention can be realized to legal branch, illegal branch and with two shared branch's fan-in nodes
The error detection of illegal branch etc..
Although typical reliable system is required to position provisional mistake by hardware technology, pure software technology can
More low consumption and more flexible selection are provided.Technology proposed by the present invention is exactly a pure software error detection techniques, the technology
Carry out the controlling stream of monitoring objective program using a bivariate table and signature.When program is compiled, each basic block has been assigned number
The different integer value signature of value, these signatures are stored in the correspondence position of corresponding basic block and a bivariate table.By this
The comparison signed a bit, system can detect that controlling stream graph（CFG）In any abnormal conditions, and suitable measure can be taken to keep away
Exempt from the output of error result.
The present invention is not increasing code space expense and to program feature in contrast to existing CFCSS error detection techniques
On the premise of influence is smaller, solve that the non-detectable two or more shared fan-in nodes of CFCSS algorithms illegally redirect asks
Topic, improves the coverage rate of controlling stream error detection.The average error detection coverage rate of the present invention is 98.1%（Than CFCSS technology
It is higher by 1.3%）, and the instruction number for error detection insertion in each basic block is relatively less.
Brief description of the drawings
The detects schematic diagram that Fig. 1 redirects for valid instruction in the present invention；
Fig. 2 for the present invention in illegally instruct the detects schematic diagram redirected；
The detects schematic diagram that Fig. 3 redirects for the illegal instruction of two shared branch's fan-in nodes in the present invention；
Fig. 4 is compared figure for the present invention with CFCSS error detection coverage rate；
Fig. 5 is compared figure for CFCSS in many fan-in node problems in the present invention with the error detecing capability of the present invention.
Embodiment
The present invention is described in detail below in conjunction with accompanying drawing.
Accompanying drawing 1 is to allowing all basic blocks in the detection of execution branch, figure all to be marked without shared fan-in node
Know and number.As shown in the left side of accompanying drawing 1, each basic block has been assigned different and equal with its own station location marker
Numerical value.The right of accompanying drawing 1 indicates detection instruction is how to carry out error detection.When program goes to v3, then performing
Before instruction in v3, SS3 and CFID [Reg, SS3] comparison should be first carried out.Reg, which is one, to be used to store dynamic signature
Global variable, the global variable is stored in the register distributed.If SS3 and CFID's [Reg, SS3] is equal
Relation is set up, even brReg, and 3 be a legal branch, then Reg will be updated to the former instruction in SS3, and the basic block
It will continue to perform, until program goes to next basic block v6.Subsequent SS6 and CFID [Reg, SS6] relatively ibid
Individual basic block is equally performed.If brReg, 6 be an illegal branch, the corresponding values one of CFID [Reg, SS6] be set to 0 and
It is not SS6, mistake sentence is performed, so that controlling stream mistake is detected.
How the execution of the one illegal jump instruction of expression of accompanying drawing 2 and the mistake are detected.In this case
Controlling stream mistake can be divided into two kinds of situations：A kind of the illegal of sensing if conditional statements redirects；It is another to point to next basic block
The illegal of centre position redirects.Br1 illegally is being redirected, before 4 are performed, Reg has initial value SS1.Under the previous case, when program is held
When row arrives v4 if sentences, read in two-dimentional CFID tables of the CFID [Reg, SS4] from buffer cache is stored in, and by
It is not allowed in br1,4, the corresponding values of CFID [Reg, SS4] are 0.Therefore, this mismatch causes subsequent
Controlling stream is transferred in error handler by " error " instruction.
And in the latter case, jump to the illegal of basic block center section and redirect in the present invention（EDSS algorithms）Under
It can be detected.But it is due to the detection instruction that v4 has skipped in branch, detection produces delay.Illegally production is redirected from v1 to v4
It is raw, an instruction of the program control transfer into v4.Reg keeps the signature in v1 constant, until program is in v4 is performed
V7 is run to after instruction.Obviously, CFID [Reg, v7] respective value is 0 in this case, and this is different from SS7, so, condition point
" if SS7 ≠ CFID [Reg, SS7] error else Reg=SS7 " should jump to error handler to Zhi Zhiling.
Accompanying drawing 3 shows the multiple branch's fan-in nodes of multiple nodes sharings as the situation of destination node.In CFCSS technologies
Lower easily generation instruction redirects the problem of obscuring, but the present invention（EDSS algorithms）It is provided for simple solution, it is to avoid
The appearance of confounding issues.In accompanying drawing 3, v7, which is one, 3 predecessor nodes v3, v4, v5 (pred (v7)={ v3, v4, v5 })
Branch's fan-in node.According to the algorithm of the present invention, SS7 is respectively filled in CFID [3,7], CFID [4,7] and CFID [5,7]
In.Node v8 is also branch's fan-in node, but only two predecessor nodes v4, v5, not including v3, i.e. and pred (v8)=
{v4, v5}.Therefore, SS8 is store in CFID [4,8] and CFID [5,8], and 0 value is store in CFID [3,8].Journey
Jump instruction br4,7, br5,8 that sequence allows are detected and performed with the same way shown in Fig. 2.Assuming that one illegally redirects
Br3,8 occur, and go to the v8 detection location of instruction, and CFID [Reg, 8] and SS8 comparison is carried out in the position.Reg is at this
The illegal value redirected before performing is SS3, and respective values of the CFID [3,8] in two-dimentional CFID tables is 0, therefore the controlling stream mistake
Just it is detected, if illegal instruction branches point to other in addition to if-else detects instruction in target basic block
Position, can be detected wherein the controlling stream mistake produced is the same by the global variable Reg not being updated in v8.Thus
Apparently, as long as each node has been assigned signature, the present invention is established（EDSS algorithms）Two-dimentional CFID tables, so that it may avoid
The illegal instruction that can not be detected newly produced in CFCSS redirects mistake.
Similar CFCSS algorithm design, the present invention（EDSS algorithms）It is more succinct and efficient by contrast.Do not have in node
It is embedded to instruct to calculate signature during dynamic operation, equally, signature is also adjusted in the process of running without unnecessary instruction.When one
When individual program is compiled, the present invention imparts a signature to each node in program control flowchart, and N is equal in program
Node total number.
Accompanying drawing 4 shows the present invention（EDSS algorithms）There is the error detection coverage rate as CFCSS, it follows that this hair
It is bright to possess the same error detection capabilities of CFCSS, meet the requirement of error detection.
Accompanying drawing 5 shows the comparison in terms of the increased code space expense of algorithm, the present invention（EDSS algorithms）It is better than
CFCSS.The present invention does not require to insert the instruction for calculating dynamic signature in a program in terms of the calculating to signature, and this is just correspondingly
Reduce the number of inserting instruction.In this respect, CFCSS technologies are provided with 3 instructions to each basic block, and the present invention is to every
Individual basic block only sets 2 instructions.
The protection content of the present invention is not limited to above example.Under the spirit and scope without departing substantially from inventive concept, this
Art personnel it is conceivable that change and advantage be all included in the present invention, and using appended claims as protect
Protect scope.
Claims (4)
1. the signature arithmetic code error detection algorithm of a kind of table- driven, it is characterised in that the detection algorithm includes step in detail below：
Step 1：All basic blocks, i.e. node are determined, program P controlling stream graph is set up, is each node serial number, i.e. basic block
Identification number, is started in controlling stream graph with natural number, i.e. vi, i=1,2 ... .N；
Step 2：A signature SSi is assigned to each node vi, if i ≠ j, SSi ≠ SSj, wherein i, j=1,2 ...
N；Each signature SSi is equal with the i in corresponding basic block identification vi；
Step 3：To each vi, i=1,2,3 ..., proceed as follows：
a）To each branch bri, j, its predecessor node is vi, and descendant node is vj；These branches are by a bivariate table
Represent, the bivariate table is referred to as CFID [i, j]；In the table, row i represents predecessor node, and row j represents descendant node；
b）If branch bri, j are in controlling stream graph, the signature SSj of descendant node is inserted into the corresponding positions of CFID [i, j]；
Otherwise CFID [i, j] position should insert 0 value；
c）The global variable stored in Reg registers basic block perform each time its detection instruction when all updates once, with
The change signed in track program process；
d）A decision instruction is inserted in the initial position of basic block, judges whether SSi and CFID [Reg, SSi] is equal, if
It is equal, then SSi is assigned to Reg, if unequal, reported an error.
2. detection algorithm according to claim 1, it is characterised in that the bivariate table is a two-dimensional array, correspondence i rows
Numerical value on j column positions is CFID [i, j], represents the station location marker in controlling stream and redirects path；Line number value i represents forerunner
The identification number of node, columns value j represents the identification number of present node.
3. detection algorithm according to claim 1, it is characterised in that the basic block refers to a string of continuous instructions,
Program is performed since first instruction in basic block, and basic block is left after the last item instruction has been performed；Except basic
The last item instruction in block does not require outer, remaining instruction in basic block do not allow for branch instruction, jump instruction or
Person's call instruction.
4. detection algorithm according to claim 1, it is characterised in that the controlling stream graph by node set V=v1,
V2 ..., vi ... vn } and set of paths E={ e1, e2 ..., ei ..., em } compositions, controlling stream graph accurate description program P control
Stream, i.e. program P is expressed as P={ V, E }；One node vi represents a basic block, and wherein i is positive integer, represents basic block in journey
Position in sequence；One paths represent the branch bri from vi to vj, j；Bri, j represent branch instruction, jump instruction, subprogram
Call instruction or return instruction.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710367340.1A CN107301123A (en) | 2017-05-23 | 2017-05-23 | A kind of signature arithmetic code error detection algorithm of table- driven |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710367340.1A CN107301123A (en) | 2017-05-23 | 2017-05-23 | A kind of signature arithmetic code error detection algorithm of table- driven |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107301123A true CN107301123A (en) | 2017-10-27 |
Family
ID=60137304
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710367340.1A Pending CN107301123A (en) | 2017-05-23 | 2017-05-23 | A kind of signature arithmetic code error detection algorithm of table- driven |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107301123A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111221670A (en) * | 2019-10-21 | 2020-06-02 | 西安空间无线电技术研究所 | Single-particle soft error protection design method for relieving detection conflict |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040034794A1 (en) * | 2000-05-28 | 2004-02-19 | Yaron Mayer | System and method for comprehensive general generic protection for computers against malicious programs that may steal information and/or cause damages |
| CN101763291A (en) * | 2009-12-30 | 2010-06-30 | 中国人民解放军国防科学技术大学 | Method for detecting error of program control flow |
| CN101944064A (en) * | 2010-10-12 | 2011-01-12 | 中国人民解放军国防科学技术大学 | Control flow error detection optimizing method based on reconstructed control flow graph |
-
2017
- 2017-05-23 CN CN201710367340.1A patent/CN107301123A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040034794A1 (en) * | 2000-05-28 | 2004-02-19 | Yaron Mayer | System and method for comprehensive general generic protection for computers against malicious programs that may steal information and/or cause damages |
| CN101763291A (en) * | 2009-12-30 | 2010-06-30 | 中国人民解放军国防科学技术大学 | Method for detecting error of program control flow |
| CN101944064A (en) * | 2010-10-12 | 2011-01-12 | 中国人民解放军国防科学技术大学 | Control flow error detection optimizing method based on reconstructed control flow graph |
Non-Patent Citations (1)
| Title |
|---|
| 陈建 等: ""表驱动的纯软件签名错误检测算法"", 《HTTP://WWW.DOC88.COM/P-3973568240860.HTML》 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111221670A (en) * | 2019-10-21 | 2020-06-02 | 西安空间无线电技术研究所 | Single-particle soft error protection design method for relieving detection conflict |
| CN111221670B (en) * | 2019-10-21 | 2023-03-28 | 西安空间无线电技术研究所 | Single-particle soft error protection design method for relieving detection conflict |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7398419B2 (en) | Method and apparatus for seeding differences in lock-stepped processors | |
| US7721066B2 (en) | Efficient encoding for detecting load dependency on store with misalignment | |
| CN106021040B (en) | A kind of DSP soft error detection method based on the transformation of linear assembly instruction otherness | |
| US9348681B2 (en) | Apparatus and method for detecting fault of processor | |
| US9880787B2 (en) | System and method for memory patching circuits | |
| US20050108509A1 (en) | Error detection method and system for processors that employs lockstepped concurrent threads | |
| CN104035895A (en) | Apparatus and Method for Memory Operation Bonding | |
| US7500138B2 (en) | Simplified event selection for a performance monitor unit | |
| EP3140730A1 (en) | Detecting data dependencies of instructions associated with threads in a simultaneous multithreading scheme | |
| CN104142889B (en) | A kind of test point of the single-particle soft error of assembly level is arranged and optimization method | |
| CN107301123A (en) | A kind of signature arithmetic code error detection algorithm of table- driven | |
| CN101539852A (en) | Processor and information processing apparatus | |
| Jianli et al. | A software-implemented configurable control flow checking method | |
| KR20100084605A (en) | Processors | |
| CN108334903B (en) | Instruction SDC vulnerability prediction method based on support vector regression | |
| CN104035898A (en) | Memory access system based on VLIW (Very Long Instruction Word) type processor | |
| Sedaghat et al. | A software-based error detection technique using encoded signatures | |
| US9003198B2 (en) | Method and apparatus for data processing | |
| CN203164952U (en) | Single transmitting assembly line processor | |
| CN112765609A (en) | Multi-bit SDC fragile instruction identification method based on single-class support vector machine | |
| US10176074B2 (en) | Computed call/jump target resolution via behavior computation | |
| CN105843589B (en) | A kind of storage arrangement applied to VLIW type processors | |
| CN105183697A (en) | Embedded RSIC-DSP processor system and construction method | |
| Dong et al. | A new method of software clone detection based on binary instruction structure analysis | |
| US20040230626A1 (en) | Computer system method for a one cycle implementation of test under mask instructions |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20171027 |
|
| WD01 | Invention patent application deemed withdrawn after publication |