CN107301102A - A kind of processor debugging method and system - Google Patents
A kind of processor debugging method and system Download PDFInfo
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- CN107301102A CN107301102A CN201710479816.0A CN201710479816A CN107301102A CN 107301102 A CN107301102 A CN 107301102A CN 201710479816 A CN201710479816 A CN 201710479816A CN 107301102 A CN107301102 A CN 107301102A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
- G06F11/0721—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0751—Error or fault detection not based on redundancy
- G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
- G06F11/0757—Error or fault detection not based on redundancy by exceeding limits by exceeding a time limit, i.e. time-out, e.g. watchdogs
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
Abstract
The embodiments of the invention provide a kind of processor debugging method and system, in order to realize the execution state that processor instruction is obtained when processor is stuck, first, when processor is run, by the PC value synchronized transmissions in processor to FIFO memory, when processor reset, logic controller judges whether to get the reseting mark signal from WDT, if, then illustrate that processor there occurs stuck and be resetted by WDT, logic controller stops the synchronized transmission PC values into FIFO memory, therefore, all the time PC values when processor occurs stuck are store in FIFO memory, this programme regard PC value of processor when stuck as target PC values；Then, processor obtains target PC values from FIFO memory；Instruction in target PC values can just reflect the execution state instructed when processor is stuck, so that, the problem of processor instruction performs state can not be determined when processor is stuck by solving prior art.
Description
Technical field
The present invention relates to field of computer technology, more particularly to a kind of processor debugging method and system.
Background technology
In field of computer technology, SoC (System on Chip：System on Chip/SoC) system refers to computer or other electronics
The system integration is often applied in embedded system to the IC system of one chip.The list weakened with simple structure, function
Chip system is compared, and SoC circuit structures are more complicated, generally reaches millions of doors to several ten million, function is more powerful, can be with
Handle data signal, analog signal, the even more high-frequency signal of mixed signal.
In SoC systems, processor is the critical elements of SoC systems, for execute program instructions, realizes data operation,
Specific SoC systemic-functions are realized jointly with other modules in SoC systems.In the prior art, processor is provided with program meter
Number device (PC：Program Counter), program counter is a register inside processor, for sequential storage processing
The a plurality of instruction that device current time is carrying out and was just performed, this command sequence is referred to as a plurality of in PC values, PC values
The sequencing instructed according to computing device is instructed to store, when processor is run, the instruction in PC values is continuous by processor
Ground takes out, meanwhile, new instruction also can be sequentially added in PC values, enabled a processor to constantly to get new program and referred to
Order.
Outside by bus annexation in SoC systems, bus running status, module running status, system running environment, system
The influences of many factors such as quality is write in portion's environment, artificial maloperation, instruction, and processor in operation, runs into sometimes
The problem of can not correctly performing instructs, and the instruction of these problems can cause processor operation exception, result even in processor
Stuck and whole SoC systems of paralysing.In the prior art, when processor operation exception, generally by the debugging interface of processor,
Debugging instruction is sent to processor, processor is debugged, the state that instruction is performed when processor is abnormal is determined, so that according to
The execution state of instruction, finds problem instruction；But, when processor occurs stuck, processor can not receive any debugging and refer to
Order, therefore, prior art can not determine the state that processor instruction is performed when processor is stuck.
The content of the invention
The invention provides a kind of processor debugging method and system, to solve problems of the prior art.
In a first aspect, the embodiments of the invention provide a kind of processor debugging method, applied in SoC, methods described bag
Include：When computing device working procedure, logic controller is by the PC value synchronized transmissions of processor to FIFO memory；Work as processing
When device resets, the logic controller judges whether to get the reseting mark signal from WDT (Watch Dog Timer)；If
It is that then the logic controller stops into the FIFO memory in PC values described in synchronized transmission, the FIFO memory
The PC values deposited are target PC values；Processor obtains the target PC values from the FIFO memory.
With reference in a first aspect, in first aspect in the first possible implementation, described when processor is run, logic
Controller by the PC values synchronized transmission of processor to FIFO memory the step of before, in addition to：Processor configures the WDT's
The maximum count time, and open the WDT countings；WDT generations when counting down to up to the maximum count time reset letter
Number and reseting mark signal；When the WDT is counted, processor resets the WDT gate times at preset timed intervals；It is described default
Time is less than the maximum count time of the WDT；Processor starts to perform work order.
It is described when computing device works journey with reference in a first aspect, in second of possible implementation of first aspect
During sequence, logic controller by the PC values synchronized transmission of processor to FIFO memory the step of, including：The logic controller is obtained
The PC values of processor are taken, the logic controller is sent out the instruction recorded in the PC values by computing device order one by one
Give the FIFO memory.
With reference to second of possible implementation of first aspect, in first aspect in the third possible implementation, institute
State logic controller and the instruction recorded in the PC values is sent to the FIFO memory one by one by computing device order
After step, in addition to：Label information is added to the instruction being finally sent in the FIFO memory.
With reference in a first aspect, in the 4th kind of possible implementation of first aspect, the FIFO memory, which can be stored, to be referred to
The quantity of order is more than the instruction number recorded in the PC values.
It is described when processor reset with reference in a first aspect, in the 5th kind of possible implementation of first aspect, it is described
After the step of logic controller judges whether to get the reseting mark signal from WDT, in addition to：If it is not, then described
Logic controller continues the PC values described in synchronized transmission into the FIFO memory.
With reference in a first aspect, in the 6th kind of possible implementation of first aspect, the processor is deposited from the FIFO
After the step of target PC values are obtained in reservoir, in addition to：Remove the reseting mark signal of the WDT.
With reference in a first aspect, in the 7th kind of possible implementation of first aspect, the FIFO memory is by first entering
First go out the register or SRAM of method data storage.
Second aspect, the embodiments of the invention provide a kind of processor debugging system, applied in SoC, the system bag
Include：Processor, logic controller, FIFO memory and WDT；The logic controller, for when computing device working procedure
When, by the PC value synchronized transmissions of processor to FIFO memory；And, for getting the reseting mark signal from WDT
When, stop the PC values described in synchronized transmission into the FIFO memory；The FIFO memory, for receiving and storing described patrol
Collect the PC values of controller synchronized transmission；The WDT, for generating the reseting mark signal, and by the reseting mark
Signal is sent to the logic controller；The processor, for obtaining target PC values from the FIFO memory.
With reference to second aspect, in second aspect in the first possible implementation, the processor is additionally operable to：Configuration institute
The WDT maximum count time is stated, and opens the WDT and is counted；The WDT is generated when counting down to up to the maximum count time
Reset signal and reseting mark signal；And, when the WDT is counted, the WDT gate times are reset at preset timed intervals；Institute
State the maximum count time that preset time is less than the WDT；And, perform working procedure.
Technical scheme provided in an embodiment of the present invention, in order to be instructed when realizing that acquisition processor is stuck when processor is stuck
Execution state, first, when processor is run, logic controller by the PC value synchronized transmissions of processor to FIFO memory,
When processor reset, logic controller judges whether to get the reseting mark signal from WDT, if it is, at explanation
Reason device there occurs and resetted by WDT that logic controller stops the synchronized transmission PC values into FIFO memory, therefore, FIFO stuck
All the time PC values when processor occurs stuck are store in memory, this programme regard PC values of processor when stuck as target PC
Value；Then, processor obtains target PC values from FIFO memory；Instruction in target PC values can just reflect processor card
The execution state instructed when dead, so that, solving prior art can not determine what processor instruction was performed when processor is stuck
The problem of state.
Brief description of the drawings
In order to illustrate more clearly of technical scheme, letter will be made to the required accompanying drawing used in embodiment below
Singly introduce, it should be apparent that, for those of ordinary skills, without having to pay creative labor,
Other accompanying drawings can also be obtained according to these accompanying drawings.
Fig. 1 is a kind of flow chart of processor debugging method provided in an embodiment of the present invention；
Fig. 2 is a kind of processor debugging method and step S110 flow chart provided in an embodiment of the present invention；
Fig. 3 is a kind of block diagram of processor debugging system provided in an embodiment of the present invention.
Embodiment
In order that those skilled in the art more fully understand the technical scheme in the present invention, below in conjunction with of the invention real
The accompanying drawing in example is applied, the technical scheme in the embodiment of the present invention is clearly and completely described, it is clear that described implementation
Example only a part of embodiment of the invention, rather than whole embodiments.Based on the embodiment in the present invention, this area is common
The every other embodiment that technical staff is obtained under the premise of creative work is not made, should all belong to protection of the present invention
Scope.
This area explanation of nouns
Watch Dog Timer (WDT：watchdog timer)：Watch Dog Timer is a kind of hardware timing device, and it is real
It is a timer conter on border.In use, to one numeral of Watch Dog Timer, that is, being configured with the maximum of Watch Dog Timer
Gate time；When computing device program, house dog starts countdown counting, and processor can send replacement at the appointed time
The instruction of Watch Dog Timer, resets Watch Dog Timer, and starts counting up again；If the countdown of Watch Dog Timer
Counting reduces to 0, that is, reaches the maximum count time, and Watch Dog Timer will send reset signal and reseting mark signal, should
Reset signal is sent to processor, can make processor reset and restart.
FIFO memory：FIFO is First Input First Output abbreviation, and Chinese is construed to：FIFO team
Row, FIFO memory is the memory using First Input First Output method data storage.FIFO memory can press programmed instruction
The sequencing shone into memory lines up storage, when the programmed instruction queue in FIFO memory is booked, whenever there is one
New programmed instruction enters fashionable, and positioned at queue, programmed instruction will be removed from FIFO memory foremost, other instruction according to
One position of secondary forward movement, queue least significant end is due to the position that instruction is moved forward and is vacated, by the instruction cover newly entered.
Figuratively, this process is similar to the process in supermarket's queuing checkout, and the people first queued up, which first settles accounts, to be left, and troop end is continuous
Someone is added in the troop of queuing.
Embodiment one
It is a kind of flow chart of processor debugging method provided in an embodiment of the present invention referring to Fig. 1.Methods described include with
Lower step：
Step S110, when computing device working procedure, logic controller gives the PC value synchronized transmissions of processor
FIFO memory.
PC values order in the present embodiment contains the instruction and be just performed that processor current time is carrying out
A plurality of instruction, and the instruction number included in PC values is constant, and the sequencing that these instructions are instructed according to computing device is deposited
Storage, logic controller to FIFO memory, makes PC values synchronized transmission in FIFO memory a plurality of in also sequential storage PC values
Instruction.Because the PC values that processor is continually performed in instruction, logic controller can be constantly updated, therefore, in order to ensure FIFO
The instruction of middle storage, can reflect the state of the current execute instruction of processor, and logic controller needs synchronously to send out PC values
It is sent in FIFO memory, PC value of the PC values with being stored in FIFO memory in processor is remained synchronous.
Step S120, when processor reset, the logic controller judges whether to get the reseting mark from WDT
Signal.
Occur in the process of running in view of processor due to it is stuck cause Watch Dog Timer reach maximum count when
Between, so that sending reset signal causes the situation of processor reset, and, processor is actively multiple due to performing reset instruction
The situation of position, the present embodiment employs the side for judging whether to get the reseting mark signal from WDT by logic controller
Method, determines whether processor is due to stuck and is resetted.Because WDT is when reaching the maximum count time, it can be simultaneously emitted by resetting
Signal and reseting mark signal, therefore, if processor resets, logic controller have received the reset from WDT
Marking signal, illustrates that processor is due to stuck and resetted, if processor resets, and logic controller, which is not received, to be come
From WDT reseting mark signal, then it is due to perform reset instruction and positive return to illustrate processor.
Step S130, if it is, the logic controller stops the PC described in synchronized transmission into the FIFO memory
The PC values deposited in value, the FIFO memory are target PC values.
In this step, if the result that logic controller judges whether to get the reseting mark signal from WDT is yes,
Then illustrate that processor there occurs stuck, therefore, logic controller stops the synchronized transmission PC values into FIFO memory, deposits FIFO
The PC values stored in reservoir no longer change.Held due to containing processor current time in the PC values in the present embodiment
Capable instruction and a plurality of instruction being just performed, when processor generation is stuck, logic controller stops to FIFO memory
During middle synchronized transmission PC values, the instruction included in PC values stored in FIFO memory is exactly that processor is carrying out when stuck
Instruction and the stuck preceding instruction just performed, these instructions reflect processor it is abnormal when the state that performs of instruction, therefore,
The PC values now deposited in FIFO memory are used as target PC values.
Step S140, processor obtains the target PC values from the FIFO memory.
In this step, computing device obtains the instruction of target PC values, and target PC values are got from FIFO memory, and
It is output in external equipment, the external equipment in the present embodiment, can is that the debugging with screen used for technical staff is set
It is standby or for storing the external memory storages of the target PC values got；Those skilled in the art is by analyzing this
The target PC values got in step, can find out causes the problem of processor is stuck to instruct, and is determined according to problem instruction
The reason for processor is stuck.
The present embodiment is further comprising the steps of before step S110 is performed：
Step S010, processor configures the maximum count time of the WDT, and opens the WDT countings；The WDT exists
It count down to up to generation reset signal and reseting mark signal during the maximum count time.
The purpose of this step is the tally function for opening WDT, when WDT is not turned on counting, the processing that the present embodiment is provided
Device adjustment method is closed；When WDT, which is opened, to be counted, the processor debugging method that the present embodiment is provided is opened.
Step S020, when the WDT is counted, processor resets the WDT gate times at preset timed intervals；It is described default
Time is less than the maximum count time of the WDT.
In this step, processor is arranged to reset WDT gate time at preset timed intervals, processor is normally being run
In the case of, WDT counting will be reset before the maximum count time is reached, and WDT will not send reset signal and reset
Marking signal, and when processor is stuck, processor would not reset WDT gate time according to preset time, WDT is reached
Reset signal and reseting mark signal are generated during the maximum count time.Therefore, this step is realized when processor occurs stuck,
WDT can generate reset signal and reseting mark signal.
Step S030, processor starts to perform work order.
In this step, work order is the instruction in order to realize SoC systems specific function and perform, by total in SoC systems
Line annexation, bus running status, module running status, system running environment, its exterior environment, artificial maloperation, refer to
The influence of many factors such as quality is write in order, may be instructed in instruction comprising some problems, also, the instruction of some problems can be led
Processor is caused to occur stuck, the present embodiment performs step S030, make processor after step S010 and step S020 is performed
Perform work order, it is possible to the shape that instruction is performed when determining that processor is stuck by follow-up step S110 to step S140
State, so that the state performed according to instruction, finds problem instruction.
Further, it is a kind of step S110 of processor debugging method provided in an embodiment of the present invention stream referring to Fig. 2
Step S110 in Cheng Tu, the present embodiment, comprises the following steps：
Step S111, the logic controller obtains the PC values of processor.
In the present embodiment, logic controller gets the PC values of processor from the program counter inside processor, by
Work order is operationally continually performed in processor, therefore, logic controller constantly obtains new instruction from processor,
The order that the instruction included in the PC values that i.e. logic controller is got is instructed with computing device is continuously updated, and makes PC values
In be carrying out and a plurality of instruction that was just performed comprising processor current time all the time.
Step S112, the logic controller is sent the instruction recorded in the PC values by computing device order one by one
To the FIFO memory.
In the present embodiment, as processor is continually performed work order, logic controller is constantly obtained from processor
PC values in call instruction, processor are constantly updated, and when an instruction is have updated in the PC values of processor, logic controller is all
This command synchronization can be sent to FIFO memory, the transmission process is continuously sent out as processor constantly performs work order
It is raw.
Further, in the present embodiment, after step sl 12, in addition to：
Step S113, label information is added to the instruction being finally sent in the FIFO memory.
The purpose of this step, be by the instruction that is finally sent in the FIFO memory is added label information come
The sequencing that the instruction that PC values are included in FIFO memory is executed by processor is determined, that is, the instruction for being added label information is
The instruction being finally executed by processor, other queue positions of execution sequence instructed according to instruction in FIFO memory
Draw.Due to as logic controller constantly sends instructions to FIFO memory, being finally sent in FIFO memory
Instruction constantly change, therefore, in this step, the instruction for being added label information is also constantly changing, when one newly
Instruction when being sent to FIFO memory, the label information of the previous bar instruction stored in FIFO memory will be transferred to newly
Instruction on.
Alternatively, in the present embodiment, the FIFO memory can the quantity of store instruction be more than in the PC values and record
Instruction number.The alternative can make the more instructions of FIFO memory storage, when stuck, logic controller occurs for processor
During no longer PC values synchronized transmission to FIFO memory, processor stuck moment, target PC values can be preserved in FIFO memory
In all instructions, and the instruction that some processors are performed earlier so that, provide more command informations for technical staff,
Contribute to technical staff's more fully analysis instruction information, find out problem instruction.
Alternatively, the present embodiment is after step S120, in addition to：
Step S131, if it is not, then the logic controller continues the PC described in synchronized transmission into the FIFO memory
Value.
Due to processor operationally, it is also possible to resetted due to performing reset instruction, WDT is to give birth in this case
Judged result into reseting mark signal, therefore step S120 is no.The reset instruction when computing device and when resetting, place
Reason device do not occur it is stuck, so, in this step, when step S120 judged result for it is no when, logic controller continue to
PC values described in synchronized transmission in FIFO memory.
Further, in the present embodiment, after step s 140, in addition to：
Step S150, removes the reseting mark signal of the WDT.
Due in step S140, having got target PC values from FIFO memory, in step S150, remove
WDT reseting mark signal, makes logic controller restart the PC value synchronized transmissions by processor to FIFO memory, so that
Continue the debugging process of the present embodiment.
Furthermore, it is necessary to which the FIFO memory in explanation, the present embodiment can be used by first-in first-out method data storage
Register or SRAM, it is of course also possible to which other storage mediums of FIFO memory function can be realized using other.
Technical scheme provided in an embodiment of the present invention, in order to be instructed when realizing that acquisition processor is stuck when processor is stuck
Execution state, first, when processor is run, logic controller by the PC value synchronized transmissions of processor to FIFO memory,
When processor reset, logic controller judges whether to get the reseting mark signal from WDT, if it is, at explanation
Reason device there occurs and resetted by WDT that logic controller stops the synchronized transmission PC values into FIFO memory, therefore, FIFO stuck
All the time PC values when processor occurs stuck are store in memory, this programme regard PC values of processor when stuck as target PC
Value；Then, processor obtains target PC values from FIFO memory；Instruction in target PC values can just reflect processor card
The execution state instructed when dead, so that, solving prior art can not determine what processor instruction was performed when processor is stuck
The problem of state.
Embodiment two
It is a kind of block diagram of processor debugging system provided in an embodiment of the present invention referring to Fig. 3.The system includes：Place
Manage device 210, logic controller 220, FIFO memory 230 and WDT240；
The logic controller 220, it is for when processor 210 performs working procedure, the PC values of processor 210 is synchronous
It is sent to FIFO memory 230；
And, for when getting the reseting mark signal from WDT240, stopping into the FIFO memory 230
PC values described in synchronized transmission；
The FIFO memory 230, the PC values for receiving and storing the synchronized transmission of logic controller 220；
The WDT240, described patrol is sent to for generating the reseting mark signal, and by the reseting mark signal
Collect controller 220；
The processor 210, for obtaining target PC values from the FIFO memory 230.
Further, in the present embodiment, the processor 210 is additionally operable to：
The maximum count time of the WDT240 is configured, and opens the WDT240 and is counted；The counting of the WDT240 exists
Generation reset signal and reseting mark signal when reaching the maximum count time；
And, when the WDT240 is counted, the WDT240 gate times are reset at preset timed intervals；The preset time
The maximum count time less than the WDT240；
And, perform working procedure.
Technical scheme provided in an embodiment of the present invention, in order to be instructed when realizing that acquisition processor is stuck when processor is stuck
Execution state, first, when processor is run, logic controller by the PC value synchronized transmissions of processor to FIFO memory,
When processor reset, logic controller judges whether to get the reseting mark signal from WDT, if it is, at explanation
Reason device there occurs and resetted by WDT that logic controller stops the synchronized transmission PC values into FIFO memory, therefore, FIFO stuck
All the time PC values when processor occurs stuck are store in memory, this programme regard PC values of processor when stuck as target PC
Value；Then, processor obtains target PC values from FIFO memory；Instruction in target PC values can just reflect processor card
The execution state instructed when dead, so that, solving prior art can not determine what processor instruction was performed when processor is stuck
The problem of state.
The present invention can be used in numerous general or special purpose computing system environments or configuration.For example：Personal computer, service
Device computer, handheld device or portable set, laptop device, multicomputer system, the system based on microprocessor, top set
Box, programmable consumer-elcetronics devices, network PC, minicom, mainframe computer including any of the above system or equipment
DCE etc..
The present invention can be described in the general context of computer executable instructions, such as program
Module.Usually, program module includes performing particular task or realizes routine, program, object, the group of particular abstract data type
Part, data structure etc..The present invention can also be put into practice in a distributed computing environment, in these DCEs, by
Remote processing devices connected by communication network perform task.In a distributed computing environment, program module can be with
Positioned at including in the local and remote computer-readable storage medium including storage device.
It should be noted that herein, term " comprising ", "comprising" or its any other variant are intended to non-row
His property is included, so that process, method, article or equipment including a series of key elements not only include those key elements, and
And also including other key elements being not expressly set out, or also include for this process, method, article or equipment institute inherently
Key element.In the absence of more restrictions, the key element limited by sentence "including a ...", it is not excluded that including institute
Also there is other identical element in process, method, article or the equipment of stating key element.
Those skilled in the art will readily occur to its of the present invention after considering specification and putting into practice invention disclosed herein
Its embodiment.It is contemplated that cover the present invention any modification, purposes or adaptations, these modifications, purposes or
Person's adaptations follow the general principle of the present invention and including undocumented common knowledge in the art of the invention
Or conventional techniques.Description and embodiments are considered only as exemplary, and true scope and spirit of the invention are by following
Claim is pointed out.
It should be appreciated that the invention is not limited in the precision architecture for being described above and being shown in the drawings, and
And various modifications and changes can be being carried out without departing from the scope.The scope of the present invention is only limited by appended claim.
Claims (10)
1. a kind of processor debugging method, applied in SoC (System on Chip/SoC) system, it is characterised in that methods described includes：
When computing device working procedure, logic controller deposits the PC values synchronized transmission of processor to FIFO (FIFO)
Reservoir；
When processor reset, the logic controller judges whether to get the reset mark from WDT (Watch Dog Timer)
Will signal；
If it is, the logic controller stops the PC values described in synchronized transmission into the FIFO memory, the FIFO is deposited
The PC values deposited in reservoir are target PC values；
Processor obtains the target PC values from the FIFO memory.
2. according to the method described in claim 1, it is characterised in that described when computing device working procedure, logic control
Device by the PC values synchronized transmission of processor to FIFO memory the step of before, in addition to：
Processor configures the maximum count time of the WDT, and opens the WDT countings；The WDT is being count down to described in most
Generation reset signal and reseting mark signal during big gate time；
When the WDT is counted, processor resets the WDT gate times at preset timed intervals；The preset time is less than described
The WDT maximum count time；
Processor starts to perform work order.
3. according to the method described in claim 1, it is characterised in that described when computing device working procedure, logic control
Device by the PC values synchronized transmission of processor to FIFO memory the step of, including：
The logic controller obtains the PC values of processor；
The instruction recorded in the PC values is sent to the FIFO by computing device order and deposited by the logic controller one by one
Reservoir.
4. method according to claim 3, it is characterised in that the instruction that the logic controller will be recorded in the PC values
After the step of FIFO memory being sent to one by one by computing device order, in addition to：
Label information is added to the instruction being finally sent in the FIFO memory.
5. according to the method described in claim 1, it is characterised in that
The FIFO memory can the quantity of store instruction be more than the instruction number that records in the PC values.
6. according to the method described in claim 1, it is characterised in that described when processor reset, the logic controller is sentenced
It is disconnected the step of whether get the reseting mark signal from WDT after, in addition to：
If it is not, then the logic controller continues the PC values described in synchronized transmission into the FIFO memory.
7. according to the method described in claim 1, it is characterised in that the processor obtains described from the FIFO memory
After the step of target PC values, in addition to：
Remove the reseting mark signal of the WDT.
8. according to the method described in claim 1, it is characterised in that the FIFO memory is by first-in first-out method data storage
Register or SRAM (static RAM).
9. a kind of processor debugging system, applied in SoC, it is characterised in that the system includes：Processor, logic control
Device, FIFO memory and WDT；
The logic controller, for when computing device working procedure, the PC value synchronized transmissions of processor to be deposited to FIFO
Reservoir；
And, for when getting the reseting mark signal from WDT, stopping the synchronized transmission institute into the FIFO memory
State PC values；
The FIFO memory, the PC values for receiving and storing the logic controller synchronized transmission；
The WDT, the logic control is sent to for generating the reseting mark signal, and by the reseting mark signal
Device；
The processor, for obtaining target PC values from the FIFO memory.
10. system according to claim 9, it is characterised in that the processor is additionally operable to：
The maximum count time of the WDT is configured, and opens the WDT and is counted；The WDT is being count down to up to the maximum count
Reset signal and reseting mark signal are generated during the time；
And, when the WDT is counted, the WDT gate times are reset at preset timed intervals；The preset time is less than described
The WDT maximum count time；
And, perform working procedure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710479816.0A CN107301102B (en) | 2017-06-22 | 2017-06-22 | Processor debugging method and system |
Applications Claiming Priority (1)
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| CN109101355A (en) * | 2018-06-26 | 2018-12-28 | 天津飞腾信息技术有限公司 | A kind of processor debugging method for extracting wrong presence feature test and excitation |
| CN112084050A (en) * | 2019-06-14 | 2020-12-15 | 北京北方华创微电子装备有限公司 | Information recording method and system |
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