CN107293594B - Metal floating gate MTP device and preparation method thereof - Google Patents

Metal floating gate MTP device and preparation method thereof Download PDF

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CN107293594B
CN107293594B CN201610207922.9A CN201610207922A CN107293594B CN 107293594 B CN107293594 B CN 107293594B CN 201610207922 A CN201610207922 A CN 201610207922A CN 107293594 B CN107293594 B CN 107293594B
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floating gate
layer
metal floating
dielectric layer
metal
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CN107293594A (en
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施森华
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Tianjin Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Tianjin Corp
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
    • H—ELECTRICITY
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    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H01L29/7883—Programmable transistors with only two possible levels of programmation charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
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Abstract

The invention discloses a metal floating gate MTP device, which comprises: a substrate; the shallow doped channel enhancement region is formed on the surface of the substrate; an oxide layer and a nitride layer which are sequentially formed on the shallow doped channel enhancement region of the substrate; a high-k dielectric layer formed on the nitride layer; and a metal floating gate formed on the high-k dielectric layer. The invention discloses a preparation method of a metal floating gate MTP device. The floating gate of the metal floating gate MTP device provided by the invention is a metal floating gate, and the size of the metal floating gate MTP device is favorably reduced.

Description

Metal floating gate MTP device and preparation method thereof
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a metal floating gate MTP device and a preparation method thereof.
Background
A Multi-Time Program Memory (MTP) has the advantages that, compared with a one-Time programmable Memory (OTP), the Multi-Time Program Memory can store, read, erase data for multiple times, and the stored data will not disappear after power is turned off, and is gradually a Memory device widely used in the fields of personal computers, electronic devices, mobile storage, and the like. As shown in fig. 1, a conventional MTP device 1 includes: a floating gate 110 and an erase gate 120 are disposed on the substrate 100, the floating gate 110 is made of polysilicon, and the erase gate 120 is used for controlling erasing charges in the floating gate 110. By controlling whether electrons exist in the floating gate 110 or not, the MTP device 1 realizes 0 and 1 storage.
With the continuous development of integrated circuit manufacturing technology, the feature size of the transistor is smaller and smaller, and under the condition that the feature size of the MOS transistor is continuously reduced, in order to reduce the parasitic capacitance of the transistor gate and improve the device speed, a metal gate is introduced into the transistor. However, since the metal gate cannot store electrons, the metal gate is not used in the MTP device, which is not favorable for realizing the small size of the MTP device.
Disclosure of Invention
The invention aims to provide a metal floating gate MTP device and a preparation method thereof, which can use a metal gate as a floating gate in the MTP device and is beneficial to realizing the small size of the MTP device.
In order to solve the above technical problem, the present invention provides a metal floating gate MTP device, including:
a substrate;
the shallow doped channel enhancement region is formed on the surface of the substrate;
an oxide layer and a nitride layer which are sequentially formed on the shallow doped channel enhancement region of the substrate;
a high-k dielectric layer formed on the nitride layer; and
and the metal floating gate is formed on the high-k dielectric layer.
Further, in the metal floating gate MTP device, the doping dosage of the shallow doped channel enhancement region is 5e14cm-3~1e15cm-3。
Furthermore, in the metal floating gate MTP device, the doping depth of the shallow doping channel enhancement region is 350 Å -500 Å.
Furthermore, in the metal floating gate MTP device, the thickness of the oxide layer is 30 Å -50 Å, and the thickness of the nitride layer is 50 Å -70 Å.
Furthermore, in the metal floating gate MTP device, the characteristic size of the oxide layer and the characteristic size of the nitride layer are both 5 nm-10 nm larger than that of the metal floating gate.
Further, in the metal floating gate MTP device, the substrate has a deep well therein, and the shallow doped channel enhancement region is located on a surface of the deep well.
Furthermore, in the metal floating gate MTP device, the doping type of the deep well is P type, and the doping type of the shallow doping channel enhancement region is N type.
Furthermore, in the metal floating gate MTP device, the substrate further includes a source region and a drain region, and the source region and the drain region are respectively located on two sides of the oxide layer.
Furthermore, in the metal floating gate MTP device, an oxide dielectric layer is further disposed between the high-k dielectric layer and the nitride layer, and a metal blocking layer is further disposed between the high-k dielectric layer and the metal floating gate.
Further, in the metal floating gate MTP device, the dielectric constant of the high-k dielectric layer is greater than or equal to 4.0.
According to another aspect of the present invention, a method for manufacturing a metal floating gate MTP device is also provided, including:
providing a substrate;
carrying out ion implantation on the surface of the substrate to form a shallow doped channel enhancement region;
sequentially forming an oxide layer and a nitride layer on a shallow-doped channel enhancement region formed on the substrate;
forming a high-k dielectric layer on the nitride layer; and
a metal floating gate is formed on the high-k dielectric layer.
Further, in the preparation method of the metal floating gate MTP device, the doping dosage of the shallow-doped channel enhancement region is 5e14cm-3~1e15cm-3。
Further, in the preparation method of the metal floating gate MTP device, the doping depth of the shallow doping channel enhancement region is 350 Å -500 Å.
Further, in the preparation method of the metal floating gate MTP device, the thickness of the oxide layer is 30 Å -50 Å, and the thickness of the nitride layer is 50 Å -70 Å.
Further, in the preparation method of the metal floating gate MTP device, the characteristic sizes of the oxide layer and the nitride layer are 5 nm-10 nm larger than that of the metal floating gate.
Furthermore, in the preparation method of the metal floating gate MTP device, the substrate is provided with a deep well, and the shallow doped channel enhancement region is positioned on the surface of the deep well.
Furthermore, in the preparation method of the metal floating gate MTP device, the doping type of the deep well is P type, and the doping type of the shallow doping channel enhancement region is N type.
Furthermore, in the preparation method of the metal floating gate MTP device, an oxide dielectric layer is formed between the high-k dielectric layer and the nitride layer, and a metal blocking layer is formed between the high-k dielectric layer and the metal floating gate.
Further, in the method for manufacturing the metal floating gate MTP device, the step of forming the high-k dielectric layer on the nitride layer includes:
forming the oxide dielectric layer, the high-k dielectric layer, the metal barrier layer and the polysilicon layer on the nitride layer in sequence;
performing ion implantation on the surface of the substrate, and forming a source region and a drain region on two sides of the oxide layer respectively;
and removing the polysilicon layer.
Furthermore, in the preparation method of the metal floating gate MTP device, the dielectric constant of the high-k dielectric layer is more than or equal to 4.0.
Compared with the prior art, the metal floating gate MTP device and the preparation method thereof provided by the invention have the following advantages:
in the metal floating gate MTP device and the preparation method thereof provided by the invention, a shallow doping channel enhancement region is formed on the surface of a substrate, an oxide layer and a nitride layer are sequentially formed on the shallow doping channel enhancement region of the substrate, a high-k dielectric layer is formed on the nitride layer, a metal floating gate is formed on the high-k dielectric layer, the shallow doping channel enhancement region can enhance the band-to-band tunnel effect, and the nitride layer is used for storing electrons or releasing electrons to realize the storage of 0 and 1, thereby completing the programming and erasing operations.
Drawings
FIG. 1 is a schematic structural diagram of a polysilicon floating gate MTP device in the prior art;
FIG. 2 is a flowchart of a method for manufacturing a metal floating gate MTP device according to an embodiment of the invention;
fig. 3 to fig. 8 are schematic structural diagrams of a metal floating gate MTP device in a manufacturing process according to an embodiment of the present invention.
Detailed Description
The metal floating gate MTP device and method of making the same of the present invention will now be described in more detail, and with reference to the accompanying schematic drawings, in which preferred embodiments of the invention are shown, it being understood that one skilled in the art may modify the invention herein described while still achieving the advantageous effects of the invention. Accordingly, the following description should be construed as broadly as possible to those skilled in the art and not as limiting the invention.
In the interest of clarity, not all features of an actual implementation are described. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific details must be set forth in order to achieve the developer's specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art.
The invention is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
The core idea of the invention is that the metal floating gate MTP device comprises: a substrate; the shallow doped channel enhancement region is formed on the surface of the substrate;
an oxide layer and a nitride layer which are sequentially formed on the shallow doped channel enhancement region of the substrate; a high-k dielectric layer formed on the nitride layer; and a metal floating gate formed on the high-k dielectric layer. The high-k dielectric layer is formed on the nitride layer, the metal floating gate is formed on the high-k dielectric layer, the shallow doped channel enhancement region can enhance the band-to-band tunneling effect, and the nitride layer is used for storing electrons or releasing electrons to realize the storage of 0 and 1, so that the programming and erasing operations are completed.
According to the core idea, a method for manufacturing a metal floating gate MTP device is provided, as shown in fig. 2, the method includes:
step S11, providing a substrate;
step S12, performing ion implantation on the surface of the substrate to form a shallow doped channel enhancement region;
step S13, sequentially forming an oxide layer and a nitride layer on the shallow doped channel enhancement region formed on the substrate;
step S14 of forming a high-k dielectric layer on the nitride layer; and
step S15, forming a metal floating gate on the high-k dielectric layer.
Referring to fig. 3-8, a metal floating gate MTP device and a method for fabricating the same according to the present invention are described in detail.
First, step S11 is performed, as shown in fig. 3, a substrate 200 is provided, where the material of the substrate 200 may be single crystal silicon (Si), single crystal germanium (Ge), silicon germanium (GeSi), or silicon carbide (SiC), or Silicon On Insulator (SOI), Germanium On Insulator (GOI); or may be other materials such as group III-V compounds such as gallium arsenide. Preferably, the substrate 200 has a deep well 201, the doping type of the deep well 201 is a P type, and structures such as a shallow trench isolation 202 may be further disposed in the substrate 200, which is understood by those skilled in the art and will not be described herein.
Next, proceeding to step S12, with continuing reference to fig. 3, ion implantation is performed on the surface of the substrate 200 to form a shallow-doped channel enhancement region 203, where the shallow-doped channel enhancement region 203 is located on the surface of the deep well 201, and the shallow-doped channel enhancement region 203 can enhance the band-to-band tunneling effect. Preferably, the lightly doped channel enhancement region 203 is doped N-type, for example, the ion implantation may be performed using As elementThe energy is 60 to 80kev, and the dopant amount of the shallow-doped channel enhancement region 203 is 5e14cm-3~ 1e15cm-3For example, 6e14cm-3、8e14cm-3And the doping depth of the shallow-doped channel enhancement region 203 is 350 Å -500 Å, such as 400 Å, 450 Å and the like.
Then, step S13 is performed, as shown in fig. 4, an oxide layer 211 and a nitride layer 212 are sequentially formed on the lightly doped channel enhancement region 203 formed on the substrate 200, wherein the nitride layer 212 is used for storing electrons or releasing electrons, so as to achieve storage of 0 and 1, specifically, a stacked oxide film and a nitride film may be first prepared on the entire surface of the substrate 200, then a photomask is prepared on the nitride film, and the oxide film and the nitride film are patterned to form the oxide layer 211 and the nitride layer 212, preferably, the oxide layer 211 has a thickness of 30 Å to 50 Å, such as 40 Å, and the nitride layer 212 has a thickness of 50 Å to 70 Å, such as 60 Å.
Next, step S14 is performed to form a high-k dielectric layer 312 on the nitride layer 212, as shown in fig. 5. In the present embodiment, an oxide dielectric layer 311 is formed between the high-k dielectric layer 312 and the nitride layer 212, and a metal barrier layer 313 is formed on the high-k dielectric layer 312. Specifically, the step S14 includes the following substeps S141 to S143:
in substep S141, as shown in fig. 5, the oxide dielectric layer 311, the high-k dielectric layer 312, the metal barrier layer 313, and the polysilicon layer 314 are sequentially formed on the nitride layer 212. Specifically, a stacked oxide dielectric film, a high-k dielectric film, a metal barrier film, and a polysilicon film may be prepared on the entire device surface, then a photomask may be prepared on the polysilicon film, and the oxide dielectric film, the high-k dielectric film, the metal barrier film, and the polysilicon film may be patterned to form the oxide dielectric layer 311, the high-k dielectric layer 312, the metal barrier layer 313, and the polysilicon layer 314;
in sub-step S142, as shown in fig. 6, performing ion implantation on the surface of the substrate 200, and forming the source region 203 and the drain region 204 on two sides of the oxide layer 211, where in fig. 6, the source region 203 is located on the left side of the oxide layer 211, and it can be understood by those skilled in the art that the source region 203 is also located on the right side of the oxide layer 211;
substep S143, as shown in fig. 7, removes the polysilicon layer 314, and the polysilicon layer 314 may protect the metal barrier layer 313 in substep S142.
Preferably, the dielectric constant of the high-k dielectric layer 312 is equal to or greater than 4.0, for example, the material of the high-k dielectric layer 312 is hafnium oxide (HfO 2), hafnium orthosilicate (HfSiO 4), zirconium dioxide (ZrO 2), aluminum oxide (Al 2O 3), titanium dioxide (TiO 2), lanthanum oxide (La 2O 3), strontium titanate (SrTiO 3), lanthanum aluminate (LaAlO 3), cerium oxide (CeO 2), yttrium oxide (Y2O 3), and combinations thereof. The metal barrier layer 313 may include elemental metals such as tungsten (W), tantalum (Ta), aluminum (Al), ruthenium (Ru), platinum (Pt), etc., or any conductive compound including, but not limited to: titanium nitride (TiN), tantalum nitride (TaN), nickel silicide (NiSi), nickel platinum silicide (NiPtSi), titanium nitride (TiN), tantalum nitride (TaN), titanium carbide (TiC), tantalum carbide (TaC), tantalum oxycarbonitride (TaCNO), ruthenium oxide (RuO 2), and the like.
Finally, step S15 is performed, as shown in fig. 8, a metal floating gate 410 is formed on the high-k dielectric layer 312, specifically in this embodiment, the metal floating gate 410 is formed on the metal blocking layer 313. In this embodiment, the metal floating gate 410 includes a groove-shaped metal barrier layer TaN 411, a groove-shaped metal layer TiAl412 for adjusting work function, a groove-shaped barrier metal layer TiN 413, and a metal aluminum 414 filled in the barrier metal layer TiN 413, which are sequentially stacked, and a metal titanium layer may be further disposed between the barrier metal layer TiN 413 and the metal aluminum 414. The process of fabricating the metal floating gate 410 is well known to those skilled in the art and will not be described herein.
Preferably, the feature sizes of the oxide layer 211 and the nitride layer 212 are both CD1, and the feature size CD1 of the oxide layer 211 and the nitride layer 212 is 5nm to 10nm, for example, 8nm, larger than the feature size CD2 of the metal floating gate 410, so that the alignment deviation in the photolithography process can be effectively prevented.
Through the above steps, the metal floating gate MTP device 2 shown in fig. 8 is formed, in the metal floating gate MTP device 2, the shallow doped channel enhancement region 203 is formed on the surface of the substrate 200, the oxide layer 211 and the nitride layer 212 are sequentially formed on the shallow doped channel enhancement region 203 of the substrate 200, the high-k dielectric layer 312 is formed on the nitride layer 212, and the metal floating gate 410 is formed on the high-k dielectric layer 312.
In this embodiment, the substrate 200 may further include a deep well 201 and a shallow trench isolation 202, the source region 203 and the drain region 204 are respectively formed in the deep well 201 on two sides of the oxide layer 211, the oxide dielectric layer 311 is formed between the high-k dielectric layer 312 and the nitride layer 212, and the metal barrier layer 313 is formed on the high-k dielectric layer 312. In addition, structures such as an erase gate may be formed on the substrate 200, which is understood by those skilled in the art and will not be described herein.
When the metal floating gate MTP device 2 is programmed, hot electrons between energy bands enter the nitride layer 212, the threshold voltage is increased, and the current between a source electrode and a drain electrode is reduced;
when the metal floating gate MTP device 2 is erased, hot holes between energy bands enter the nitride layer 212, the threshold voltage is reduced, and the current between the source and the drain is increased.
The floating gate of the metal floating gate MTP device 2 is a metal floating gate, so that the size of the metal floating gate MTP device 2 is reduced.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims (18)

1. A metal floating gate MTP device is characterized by comprising:
a substrate;
the shallow doped channel enhancement region is formed on the surface of the substrate;
an oxide layer and a nitride layer which are sequentially formed on the shallow doped channel enhancement region of the substrate;
the high-k dielectric layer is formed on the nitride layer, and an oxide dielectric layer is arranged between the high-k dielectric layer and the nitride layer; and
and the metal floating gate is formed on the high-k dielectric layer, and a metal blocking layer is arranged between the high-k dielectric layer and the metal floating gate.
2. The metal floating gate MTP device of claim 1, wherein a dopant dose of the lightly doped channel enhancement region is 5e14cm-3~1e15cm-3。
3. The metal floating gate MTP device of claim 1, in which a doping depth of the shallow doped channel enhancement region is 350 Å -500 Å.
4. The metal floating gate MTP device of claim 1, wherein the oxide layer is 30 Å -50 Å thick, and the nitride layer is 50 Å -70 Å thick.
5. The metal floating gate MTP device of claim 1, wherein the feature size of the oxide layer and the feature size of the nitride layer are both 5nm to 10nm larger than the feature size of the metal floating gate.
6. The metal floating gate MTP device of claim 1, wherein the substrate has a deep well therein, and the lightly doped channel enhancement region is located at a surface of the deep well.
7. The metal floating gate MTP device of claim 6, in which a doping type of the deep well is P-type and a doping type of the shallow doped channel enhancement region is N-type.
8. The metal floating gate MTP device of any one of claims 1 to 7, further comprising a source region and a drain region in the substrate, the source region and the drain region being located on two sides of the oxide layer, respectively.
9. The metal floating gate MTP device of any one of claims 1 to 7, wherein a dielectric constant of the high-k dielectric layer is equal to or greater than 4.0.
10. A preparation method of a metal floating gate MTP device is characterized by comprising the following steps:
providing a substrate;
carrying out ion implantation on the surface of the substrate to form a shallow doped channel enhancement region;
sequentially forming an oxide layer and a nitride layer on a shallow-doped channel enhancement region formed on the substrate;
forming a high-k dielectric layer on the nitride layer, and forming an oxide dielectric layer between the high-k dielectric layer and the nitride layer; and
a metal floating gate is formed on the high-k dielectric layer, and a metal barrier layer is formed between the high-k dielectric layer and the metal floating gate.
11. The method of claim 10, in which the dopant amount of the shallow doped channel enhancement region is 5e14cm-3~1e15cm-3。
12. The method of claim 10, in which the doping depth of the shallow doped channel enhancement region is 350 Å -500 Å.
13. The method for preparing the metal floating gate MTP device according to claim 10, wherein the thickness of the oxide layer is 30 Å -50 Å, and the thickness of the nitride layer is 50 Å -70 Å.
14. The method of claim 10, wherein the oxide layer and the nitride layer both have a characteristic dimension that is 5nm to 10nm greater than the characteristic dimension of the metal floating gate.
15. The method of claim 10, wherein the substrate has a deep well therein, and the lightly doped channel enhancement region is located on a surface of the deep well.
16. The method of claim 15, wherein the deep well is P-type doped and the shallow doped channel enhancement region is N-type doped.
17. The method of manufacturing a metal floating gate MTP device of claim 10, wherein the step of forming a high-k dielectric layer on the nitride layer comprises:
forming the oxide dielectric layer, the high-k dielectric layer, the metal barrier layer and the polysilicon layer on the nitride layer in sequence;
performing ion implantation on the surface of the substrate, and forming a source region and a drain region on two sides of the oxide layer respectively;
and removing the polysilicon layer.
18. The method of any of claims 10 to 16, wherein the dielectric constant of the high-k dielectric layer is 4.0 or more.
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