CN107291003B - micro system architecture for space power management - Google Patents
micro system architecture for space power management Download PDFInfo
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B64—AIRCRAFT; AVIATION; COSMONAUTICS
- B64G—COSMONAUTICS; VEHICLES OR EQUIPMENT THEREFOR
- B64G1/00—Cosmonautic vehicles
- B64G1/22—Parts of, or equipment specially adapted for fitting in or to, cosmonautic vehicles
- B64G1/66—Arrangements or adaptations of apparatus or instruments, not otherwise provided for
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/25—Pc structure of the system
- G05B2219/25257—Microcontroller
Abstract
The invention discloses an power management microsystem architecture for space use, which comprises a system communication layer, an optimization control layer, a function setting layer and an application execution layer, wherein the function setting layer comprises a shunting module, a discharging regulation module, a partial circuit in the charging regulation module and a main error amplification module, and the application execution layer comprises another partial circuit in the shunting module, the discharging regulation module and the charging regulation module.
Description
Technical Field
The invention relates to the field of aerospace electronic power supplies, in particular to a power supply management micro-system architecture for spaces.
Background
The power supply controller is an important component of a power supply subsystem of a satellite and other spacecrafts, provides a stable -time bus for the whole satellite, and has the main functions of solar cell S3R switch shunt control, storage battery pack charging and discharging control, -time bus, storage battery and solar cell voltage, current, temperature and other parameters acquisition and measurement, a power supply test interface, storage battery balance management, wherein the weight of a satellite power supply accounts for 30% -40% of the weight of the whole satellite, the bearing capacity of a satellite platform is severely limited, and the requirement of large load cannot be met.
The SoC is a system design, chip design, software design, process design and product guarantee support environment, the SoC technology developed by using an IP library is different from the common integrated circuit, and the significant characteristic is that top-level system design and software and hardware collaborative design are emphasized, an IP core refers to circuit modules which have been designed and actually verified and have specific functions and optimized performance, the IP core is generally divided into three types, namely a hard core, a soft core and a solid core, the hard core refers to an IP core which is laid out in advance and can be directly called as a specific function module, the soft core is generally submitted in a Hardware Description Language (HDL) form, the solid core consists of RTL description and a comprehensive netlist, the IP core is an SoC application foundation, the design of the SoC system is based on IP multiplexing, the existing IP core is used for design reuse, the overall design of a target system and the simulation and verification of system functions, and the whole system function design is completed by adopting a top-down design method starting from a system behavior level.
The power integrated circuit SiP is formed by integrating power electronic devices and information electronic circuits such as protection, sensing, detection and diagnosis and the like on the same package, developing the research on the power circuit SiP integration technology, and integrating power devices with large power and volume into units, so that the volume and the weight of a power controller can be effectively reduced, and the heat control burden of the power controller is reduced.
The fast response spacecraft puts new requirements on miniaturization, easy expansion, upgradability, standardized interfaces and the like on a power supply system. The best known fast response spacecraft in the work is the tactical satellite TacSat in the united states. In addition, the system comprises an experimental small satellite XSS series, a rapid attack recognition and detection alarm system (RAIDRS), a repeatedly-butted cube satellite cube, a British synthetic aperture radar satellite (AstroSAR), an intelligent small satellite platform and the like. These fast-sounding satellite power systems have adopted SoC design concepts and technologies such as standard bus design, function modularization, interface standardization and the like.
A power supply management unit in a new generation, which is created to meet the requirements of a satellite power supply system and belongs to ETCA company in Europe Thales Alenia space group, adopts an MIL1553B external bus and an RS485 internal bus, the structure is a modular combined structure, the power supply management unit can be modularly expanded and combined according to the requirements of different powers, and each module adopts a generalized and microsystemic design mode.
Chinese patent 201480039674 describes optimized power supply architectures that provide for efficient distribution of power and fault detection in a microcontroller system the power supply architecture includes various components and a high integrity and diversity detection scheme that allows the associated control processor to operate with a high safety standard.
Disclosure of Invention
The invention aims to provide space power supply management micro-system architectures, which disassemble the function of a space power supply control single machine and carry out integrated miniaturization design by units to realize plug and play and rapid assembly of internal functional units of the space power supply management micro-system.
In order to achieve the purpose, the invention is realized by the following technical scheme:
A power management microsystem architecture for space use, which is characterized by comprising:
a system communication layer;
optimizing a control layer;
the function setting layer comprises a shunting module, a discharging regulation module, partial circuits in the charging regulation module and a main error amplification module;
and an application execution layer which comprises another partial circuits in the shunting module, the discharging regulation module and the charging regulation module.
The system communication layer is a TTE Ethernet bus.
The optimization control layer comprises: the system comprises a secondary power supply module, an intelligent data node and a balance management module;
wherein, the secondary power supply module includes: the secondary power supply comprises a secondary power supply IP core, a secondary power supply SiP, a secondary power supply connected with a secondary power supply SiP circuit, and a secondary power supply communication interface, a secondary power supply instruction control circuit and a secondary power supply sampling interface circuit which are connected with the secondary power supply IP core circuit;
the balance management module comprises: the balance management system comprises a balance management IP core, and a single sampling circuit, a balance management communication interface, a balance management instruction control circuit and a balance sampling interface which are connected with the balance management IP core circuit.
The intelligent data node comprises:
MCU, Flash, SDRAM, TTE Ethernet bus interface, ADC/DAC interface and I2C bus interface.
The intelligent data node also comprises an fault protection and time logic phase-locked loop, an intelligent data power interface and a module monitoring interface.
The shunting module specifically comprises: the system comprises a shunt IP core, a shunt SiP, a shunt communication interface, a shunt instruction control circuit, a shunt sampling interface, a shunt MEA interface and a shunt PWM control circuit which are connected with a shunt IP core circuit, and a shunt driving circuit, a shunt protection circuit and a shunt detection circuit which are connected with the shunt SiP circuit;
the discharge regulation module specifically comprises: the system comprises a discharge regulation IP core, a discharge regulation SiP, a discharge regulation communication interface, a discharge regulation instruction control circuit, a discharge regulation sampling interface, a discharge regulation MEA interface and a discharge regulation PWM control circuit, which are connected with a discharge regulation IP core circuit, and a discharge regulation driving circuit, a discharge regulation protection circuit and a discharge regulation detection circuit, which are connected with the discharge regulation SiP circuit;
the main error amplifying module specifically comprises a main error amplifying IP core, a main error communication interface connected with a main error amplifying IP core circuit, a main error instruction control circuit, a main error sampling interface and a system MEA circuit;
the charging regulation module specifically comprises: the charging regulation system comprises a charging regulation IP core, a charging regulation SiP, a charging regulation communication interface connected with a charging regulation IP core circuit, a charging regulation instruction control circuit, a charging regulation sampling interface, a charging regulation MEA interface, a charging regulation PWM control circuit, a charging regulation current sharing control circuit, a charging regulation driving circuit connected with the charging regulation SiP circuit, a charging regulation protection circuit and a charging regulation detection circuit.
The shunt IP core, the shunt communication interface, the shunt instruction control circuit, the shunt sampling interface, the shunt MEA interface and the shunt PWM control circuit in the shunt module, the discharge regulation IP core, the discharge regulation communication interface, the discharge regulation instruction control circuit, the discharge regulation sampling interface, the discharge regulation MEA interface and the discharge regulation PWM control circuit in the discharge regulation module, the main error amplification module, the charge regulation IP core, the charge regulation communication interface, the charge regulation instruction control circuit, the charge regulation sampling interface, the charge regulation MEA interface, the charge regulation PWM control circuit and the charge regulation current-sharing control circuit in the charge regulation module form an function setting layer.
The shunt SiP, the shunt driving circuit, the shunt protection circuit and the shunt detection circuit in the shunt module, and the discharge regulation SiP, the discharge regulation driving circuit, the discharge regulation protection circuit and the discharge regulation detection circuit in the discharge regulation module, and the charge regulation SiP, the charge regulation driving circuit, the charge regulation protection circuit and the charge regulation detection circuit in the charge regulation module form an application execution layer.
Compared with the prior art, the invention has the following advantages:
(1) design of open structure
The open structure has the characteristics of strong universality and expansibility, and is designed as follows:
, using the third generation space communication bus gigabit TTE Ethernet as the standard interface of the power system to expand, configuring the corresponding standard communication protocol, and the service system developed by each spacecraft subsystem according to the open bus hardware interface and the corresponding communication protocol can be seamlessly accessed into the satellite computer.
Secondly, the I2C bus specification is adopted as of the internal bus of the power system, and each power system board level module is connected with the system according to the open I2C bus specification.
(2) Interface standardized design
The standardized interface standard of the spacecraft specifies the module interface of a power supply system, a bus and load interface, a bus grounding interface and the like in detail, communication, instruction control and sampling are general parts for each IP cores, the communication, instruction control and sampling are integrated into a general IP core through an ASIC (application specific integrated Circuit), and the bus interface of an intelligent node is also standardized.
(3) Control and management IP core design
The space power supply control system mainly comprises a power supply controller (PCDU) and a lithium Battery Manager (BMU). The PCDU is responsible for the transformation, regulation, distribution and management of energy. The control part of the system relates to voltage and current sampling, an error amplifier MEA, PI regulation, PWM control, parallel current sharing and the like; the BMU is responsible for on-orbit management of the lithium battery and relates to monomer sampling, balance control and the like. These general control and management circuits are respectively IP-based. And respectively establishing a behavior-level simulation model, a physical layout-level model and a metadata model for the IP cores. The behavior-level simulation model is designed by adopting a system-level modeling language (SystemC), and comprises all functions such as functions and areas of an IP core and necessary implementation information. The model interface time sequence is based on transaction and cycle, and is respectively used for realizing SoC architecture design and performance analysis. The metadata model is designed by adopting XML (extensible Markup language) language, records various attributes of the IP core and forms the basis of the automatic integration of the IP core.
(4) Power SiP integration design
The PCDU has important parts, namely a power regulation part, besides a control management part, because a plurality of power devices such as power MOS (metal oxide semiconductor) transistors, inductors, capacitors, transformers and the like are involved, the integration mode of the PCDU is different from that of the control regulation part, the PCDU cannot be directly designed for an IP (Internet protocol) core, and is subjected to SiP (silicon-in-package) integration, wherein the power devices, a peripheral interface circuit, a protection circuit, a detection and diagnosis circuit and the like are integrated in the same module, and a power conversion component is used as an independent execution mechanism for controlling the IP core after the SiP integration.
(5) Collaborative optimization design
Different from the traditional power supply system, the high-performance power supply system also comprises an optimization control layer, which mainly comprises PI (proportion integration) regulation parameter optimization, control algorithm optimization, energy optimization distribution and scheduling, energy optimization management, health condition evaluation and fault detection, early warning and reconstruction of the power supply system and the like. The optimization adopts software and hardware cooperative analysis, cooperative design, cooperative simulation and cooperative verification, so that the hardware design risk can be greatly reduced, and the development and debugging time of embedded software can be shortened. Meanwhile, fatal problems existing in software and hardware can be found in time in a collaborative verification environment, and the software and hardware are prevented from being adjusted again in the final integrated test stage.
(6) Function addition and subtraction expansion design
The PCDU with any requirement can be realized by increasing or decreasing the function configuration of the board-level module and additionally installing the expansion unit.
1) Increase and decrease module function configuration
When the basic board-level module is actually applied, the function configuration of the module can be changed by adopting an IP core multiplexing technology according to the requirement of an actual task, and unnecessary function IP cores are removed or corresponding function IP cores are added to form the board-level module which is suitable for new requirements.
2) Add extension module
The number of basic board level modules is limited by the capability of the MEA master error amplifying module, and is also controlled by the MEA master error amplifying module system .
The expansion module selects kinds of 6 basic board-level modules with fixed quantity according to the requirement, and the kind of the used modules and the quantity of each kind of modules are designed according to the actual requirement.
The expansion module and the optimization management module can communicate in a TTE (time to live) or 1553B serial port mode (the specific communication mode can be selected), and the expansion module can communicate in an I2C serial port mode.
(7) Componentized design of control cores
The control kernel adopts a component design, constructs software middleware by packaging a driver, and provides an interface of the system for application software so as to adapt to different hardware environments and software environments.
(8) SoC chip software and hardware collaborative design based on IP core
The power system SoC includes not only digital IP, analog IP, but also power-level IP cores, and a system integration verification environment based on various IP cores needs to be established to complete the integration simulation of the IP cores.
Different from the traditional space power supply system, the power supply management micro-system SoC also comprises an optimization control layer which mainly comprises PI (proportion integration) regulation parameter optimization, control algorithm optimization, energy optimization distribution and scheduling, energy optimization management, power supply system health condition assessment and fault detection, early warning and reconstruction and the like. The optimization adopts software and hardware cooperative analysis, cooperative design, cooperative simulation and cooperative verification, so that the hardware design risk can be greatly reduced, and the development and debugging time of embedded software can be shortened. Meanwhile, fatal problems existing in software and hardware can be found in time in a collaborative verification environment, and the software and hardware are prevented from being adjusted again in the final integrated test stage.
Drawings
FIG. 1 is a block diagram of an space power management microsystem architecture;
FIG. 2 is a block diagram of an intelligent node of the present invention;
FIG. 3 is a functional diagram of a control core of the microsystem of the present invention.
Detailed Description
The present invention will now be described in further detail by way of a detailed description of preferred embodiments, taken in conjunction with the accompanying drawings of which illustrates the invention.
As shown in fig. 1, the microsystem architectures for power management for space use include a system communication layer, an optimization control layer, a function setting layer including a shunting module, a discharging adjustment module, a part circuit of the charging adjustment module and a main error amplification module, and an application execution layer including another part circuit of the shunting module, the discharging adjustment module and the charging adjustment module.
The system communication layer is a TTE Ethernet bus.
The optimization control layer includes: the system comprises a secondary power supply module, an intelligent data node and a balance management module;
wherein, the secondary power supply module includes: the secondary power supply comprises a secondary power supply IP core, a secondary power supply SiP, a secondary power supply connected with a secondary power supply SiP circuit, and a secondary power supply communication interface, a secondary power supply instruction control circuit and a secondary power supply sampling interface circuit which are connected with the secondary power supply IP core circuit; the balance management module comprises: the balance management system comprises a balance management IP core, and a single sampling circuit, a balance management communication interface, a balance management instruction control circuit and a balance sampling interface which are connected with the balance management IP core circuit.
The intelligent data node comprises: MCU, Flash, SDRAM, TTE Ethernet bus interface, ADC/DAC interface and I2C bus interface (see FIG. 2) connected by circuit.
The intelligent data node also comprises fault protection and time logic phase-locked loop, intelligent data power interface and module monitoring interface.
The shunt module specifically comprises a shunt IP core, a shunt SiP, a shunt communication interface connected with the shunt IP core circuit, a shunt instruction control circuit, a shunt sampling interface, a shunt MEA interface, a shunt PWM control circuit, a shunt driving circuit connected with the shunt SiP circuit, a shunt protection circuit and a shunt detection circuit, the discharge regulation module specifically comprises a discharge regulation IP core, a discharge regulation SiP, a discharge regulation communication interface connected with the discharge regulation IP core circuit, a discharge regulation instruction control circuit, a discharge regulation sampling interface, a discharge regulation MEA interface and a discharge regulation PWM control circuit, and a discharge regulation driving circuit, a discharge regulation protection circuit and a discharge regulation detection circuit connected with the discharge regulation SiP circuit, the main error amplification module specifically comprises a main error amplification IP core, a main error communication interface connected with the main error amplification IP core circuit, a main error instruction control circuit, a main error sampling interface and a system circuit, and the charge regulation module specifically comprises a charge regulation IP core, a charge regulation SiP, a charge regulation IP interface connected with the charge regulation IP core, a charge regulation control circuit connected with the charge regulation IP core, a charge regulation control circuit and a charge regulation circuit connected with the charge regulation circuit, and a charge regulation circuit.
The shunting IP core, the shunting communication interface, the shunting instruction control circuit, the shunting sampling interface, the shunting MEA interface and the shunting PWM control circuit in the shunting module, the discharging regulation IP core, the discharging regulation communication interface, the discharging regulation instruction control circuit, the discharging regulation sampling interface, the discharging regulation MEA interface and the discharging regulation PWM control circuit in the discharging regulation module, the main error amplification module, the charging regulation IP core, the charging regulation communication interface, the charging regulation instruction control circuit, the charging regulation sampling interface, the charging regulation MEA interface, the charging regulation PWM control circuit and the charging regulation current-sharing control circuit in the charging regulation module form an function setting layer.
The shunt SiP, the shunt driving circuit, the shunt protection circuit and the shunt detection circuit in the shunt module, and the discharge regulation SiP, the discharge regulation driving circuit, the discharge regulation protection circuit and the discharge regulation detection circuit in the discharge regulation module, and the charge regulation SiP, the charge regulation driving circuit, the charge regulation protection circuit and the charge regulation detection circuit in the charge regulation module form an application execution layer.
The method is characterized in that a high-safety TTE (time triggered Ethernet) bus is adopted to carry out external communication with a star computer, the internal communication of an intelligent data node is realized by adopting a TTE external bus to I2C internal bus transmission gateway, and each functional submodule is controlled through an IP (Internet protocol) core of a node data processor and an I2C internal bus; the optimization control layer performs optimization control on the system from the whole power system, which is an important guarantee for realizing a high-performance power system, the functions are realized by an intelligent data node and a secondary power conversion and equalization manager at the same time, and the equalization control is composed of a single sampling unit, an equalization management unit, an instruction control unit and an interface IP core unit; the function setting layer mainly realizes the constant bus voltage through PWM control, is the basis for realizing the high efficiency, high quality, high reliability and the like of a power supply system, and integrates IP core units such as instruction control, a communication interface, a sampling interface, an MEA interface, current sharing control, PWM pulse width modulation and the like; the application execution layer is mainly a power conversion circuit, the control object and the control quantity of the application execution layer are respectively the duty ratio of a power MOS tube, and each unit is respectively a power driving circuit, a protection circuit, a detection circuit and the like, and the unit is a mixed-mode SiP which is composed of an operational amplifier, an MOS tube, an inductor and a capacitor.
The high-performance power supply system based on the hybrid integrated SoC adopts a modular SoC, and comprises a shunt module, a discharge regulation module, a charge regulation module, a main error amplification module, a secondary power supply module, a lithium battery management module and the like, wherein each modules comprise a communication interface, an optimization control interface and a sampling interface IP core, and the general IP cores are responsible for signal acquisition, data processing and module data exchange with an upper layer or a module on the same layer to realize optimization control.
As shown in FIG. 3, to enhance the software structured design, the software of the general-purpose processor module adopts a modular and hierarchical design on the software architecture.
The power management micro-system architecture is designed as follows:
(1) top layer design
The method comprises the following steps of combing the functional characteristics, circuit properties and other characteristics of a power supply system, carrying out top-level design on a power supply system SoC framework, and constructing module composition and functions of a high-integration space power supply micro system;
(2) control component module on-chip
According to the top layer architecture and the module functions thereof, common circuits or functions are extracted, and an ASIC (application specific integrated circuit) technology is adopted for on-chip integration to form a universal function module; and (4) IP coring the general function module, and forming an IP hard core and an IP soft core according to the actual application requirement. Constructing control component IP libraries such as shunting, discharging, charging, secondary power supply, balance management, monomer sampling, MEA error amplification, PI regulation, fault management and the like;
(3) on-chip singulation of cells
According to the requirement of a power supply system, integrating the IP cores to form an integrated module device; according to the power grade of the circuit, the functions of power control, power conversion and the like are respectively integrated. Constructing a signal control circuit IP library to realize SoC of each module;
(4) power supply system SoC
And on the basis of the integration of the early-stage IP core and the SiP, the plug and play of a micro system level is carried out, and the assembly is fast.
Designing a general unit:
on the basis of constructing a reusable IP core, corresponding peripheral circuits are added to each IP cores, ASIC chips are designed, and SiP integration is carried out on a power execution mechanism, wherein the chips mainly comprise:
1) intelligent node chip of general processor
2) Instruction controlled ASIC chip
3) PWM control ASIC chip
4) Lithium battery equalization management ASIC chip
5) Driving unit SiP chip
6) Protection unit SiP chip
7) Detection unit SiP chip
Intelligent data node functional parameters have been developed:
measurement and control processing: remote control data receiving and distributing, and remote measuring data framing;
managing: bus management, integrated I2C/TTE Ethernet (or CAN, optional) communication interface;
power system management: estimating the health state of the power system and estimating the service life;
and (4) housekeeping safety management: energy control, emergency safety management and self-destruction control;
and (3) autonomous management: FDIR (fault diagnosis, isolation and recovery);
collecting remote measuring parameters: collecting part of analog quantity telemetering parameters;
and (3) remote control instruction output: and outputting the control instruction set to the outside.
In summary, the space power management microsystem architecture of the invention has the integrated and miniaturized design of the power control unit for space flight use with the function of disassembling and units, and realizes the plug and play and the rapid assembly of the internal functional units of the space power management microsystem.
While the present invention has been described in detail with reference to the preferred embodiments, it should be understood that the above description should not be taken as limiting the invention. Various modifications and alterations to this invention will become apparent to those skilled in the art upon reading the foregoing description. Accordingly, the scope of the invention should be determined from the following claims.
Claims (7)
1, A power management microsystem architecture for space use, comprising:
a system communication layer;
optimizing a control layer;
the function setting layer comprises part sub-modules of the shunt module, part sub-modules of the discharge regulation module, part sub-modules of the charge regulation module and a main error amplification module;
an application execution layer comprising another sub-module portion of the shunting module, another sub-module portion of the discharge regulation module, and another sub-module portion of the charge regulation module;
the optimization control layer comprises: the system comprises a secondary power supply module, an intelligent data node and a balance management module;
wherein, the secondary power supply module includes: the secondary power supply comprises a secondary power supply IP core, a secondary power supply SiP, a secondary power supply connected with a secondary power supply SiP circuit, and a secondary power supply communication interface, a secondary power supply instruction control circuit and a secondary power supply sampling interface circuit which are connected with the secondary power supply IP core circuit;
the balance management module comprises: the balance management system comprises a balance management IP core, and a single sampling circuit, a balance management communication interface, a balance management instruction control circuit and a balance sampling interface which are connected with the balance management IP core circuit.
2. The space power management microsystem architecture as claimed in claim 1, wherein the system communication layer is a TTE ethernet bus.
3. The space power management microsystem architecture as claimed in claim 1, wherein the intelligent data node comprises:
MCU, Flash, SDRAM, TTE Ethernet bus interface, ADC/DAC interface and I2C bus interface.
4. The space power management microsystem architecture as claimed in claim 3, wherein the intelligent data node further comprises fault protection and time logic phase locked loop, intelligent data power interface and module monitor interface.
5. The space-oriented power management microsystem architecture as claimed in claim 1, wherein the shunting module specifically comprises: the system comprises a shunt IP core, a shunt SiP, a shunt communication interface, a shunt instruction control circuit, a shunt sampling interface, a shunt MEA interface and a shunt PWM control circuit which are connected with a shunt IP core circuit, and a shunt driving circuit, a shunt protection circuit and a shunt detection circuit which are connected with the shunt SiP circuit;
the discharge regulation module specifically comprises: the system comprises a discharge regulation IP core, a discharge regulation SiP, a discharge regulation communication interface, a discharge regulation instruction control circuit, a discharge regulation sampling interface, a discharge regulation MEA interface and a discharge regulation PWM control circuit, which are connected with a discharge regulation IP core circuit, and a discharge regulation driving circuit, a discharge regulation protection circuit and a discharge regulation detection circuit, which are connected with the discharge regulation SiP circuit;
the main error amplifying module specifically comprises a main error amplifying IP core, a main error communication interface connected with a main error amplifying IP core circuit, a main error instruction control circuit, a main error sampling interface and a system MEA circuit;
the charging regulation module specifically comprises: the charging regulation system comprises a charging regulation IP core, a charging regulation SiP, a charging regulation communication interface connected with a charging regulation IP core circuit, a charging regulation instruction control circuit, a charging regulation sampling interface, a charging regulation MEA interface, a charging regulation PWM control circuit, a charging regulation current sharing control circuit, a charging regulation driving circuit connected with the charging regulation SiP circuit, a charging regulation protection circuit and a charging regulation detection circuit.
6. The power management microsystem architecture for space use according to claim 5, wherein the shunting IP core, shunting communication interface, shunting command control circuit, shunting sampling interface, shunting MEA interface, shunting PWM control circuit in the shunting module, and the discharging regulation IP core, discharging regulation communication interface, discharging regulation command control circuit, discharging regulation sampling interface, discharging regulation MEA interface, and discharging regulation PWM control circuit in the discharging regulation module, and the main error amplification module, and the charging regulation IP core, charging regulation communication interface, charging regulation command control circuit, charging regulation sampling interface, charging regulation MEA interface, charging regulation PWM control circuit, charging regulation current sharing control circuit in the charging regulation module are configured as function setting layers.
7. The power management microsystem architecture for space use according to claim 5, wherein the shunting SiP, shunting driver circuit, shunting protection circuit, shunting detection circuit in the shunting module, and the discharging regulation SiP, discharging regulation driver circuit, discharging regulation protection circuit, discharging regulation detection circuit in the discharging regulation module, and the charging regulation SiP, charging regulation driver circuit, charging regulation protection circuit, charging regulation detection circuit in the charging regulation module constitute an application execution layer.
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| CN107831686B (en) * | 2017-10-25 | 2020-08-11 | 上海空间电源研究所 | Digital control system for satellite power supply controller |
| CN109085504A (en) * | 2018-07-12 | 2018-12-25 | 上海空间电源研究所 | The in-orbit Work condition analogue integrated test system of satellite power supply platform |
| CN109143091B (en) * | 2018-10-15 | 2020-12-29 | 四川长虹电器股份有限公司 | Battery management system fault FDIR system and method based on double redundancy |
| CN111898174A (en) * | 2020-07-31 | 2020-11-06 | 北京大学 | Free reconfigurable system based on standardized module and magnetic interconnection |
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