CN107273256A - A kind of adjustment method and system of Soc chips - Google Patents
A kind of adjustment method and system of Soc chips Download PDFInfo
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- CN107273256A CN107273256A CN201710479793.3A CN201710479793A CN107273256A CN 107273256 A CN107273256 A CN 107273256A CN 201710479793 A CN201710479793 A CN 201710479793A CN 107273256 A CN107273256 A CN 107273256A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2273—Test methods
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Abstract
This application discloses a kind of adjustment method and system of Soc chips, obtain and analyze Debugging message, export effective Debugging message；Mark effective Debugging message；Effective Debugging message after storage mark；The storage state of effective Debugging message after judge mark, according to the storage state, output meets effective Debugging message of arbitration principle；Meet effective Debugging message of arbitration principle described in encapsulation；Effective Debugging message after distribution encapsulation；Effective Debugging message after conveying distribution.The present processes and system can obtain the accurate process and internal logic of the generation of chip internal problem, and the analysis for solve in existing adjustment method that using jtag interface process that chip goes wrong can not be known, interacting using I/O interface to logic in chip using the mode of Firmware daily records comprehensively and the problem of can not be fine to the operation of logical internal.
Description
Technical field
The application is related to technical field of semiconductors, more particularly to a kind of adjustment method and system of Soc chips.
Background technology
With the development of design and manufacturing technology, the integrated collection that develops into gate of the IC design from transistor
Into present integrated, i.e. Soc (the System on for developing into IP (Interrupt Priority interrupt priority register) again
Chip, on-chip system) designing technique.Soc can be effectively reduced the development cost of electronic information product, shorten exploitation week
Phase, the competitiveness of product is improved, be futurity industry circle by the topmost product development mode of use.
At present, the debugging method of Soc chips mainly has three major types：1) JTAG (Joint Test Action are passed through
Group, joint test behavior tissue) interface is in CPU (Central Processing Unit, central processing unit) debugging mode
The lower register for reading respective logic module, obtains possible effective information to help to analyze and inference problems, because generally existing
Crucial state machine and key signal can be incorporated into register by engineer during design；2) IO (Input of chip are passed through
Output, input and output) internal key control signal and data-signal be incorporated into chip exterior by interface, passes through logic analyser
Or oscillograph carries out dynamic case study and positioning；3) whole business is recorded by way of Firmware (firmware) daily record
Operating process and software and hardware interaction.
However, in the first above-mentioned adjustment method, jtag interface reads corresponding logic deposit under CPU debugging modes
The mode of device can only obtain static state state value, that is, can only obtain go wrong after chip internal logic state, without
The process of generation problem can be known, when so in face of major part more complicated system and problem, it is difficult to find in a short time
The root of problem.In second of adjustment method, although can be observed by the way of signal in piece External Observation piece using I/O interface
To dynamic process, but because the pin of chip is limited, it is difficult to the signal of association is more comprehensively output to chip exterior, even if
IO numbers are more than enough, but the measurement pin of such as logic analyser and oscillograph is also limited, therefore this mode can only be very
The analysis of logic interaction in piece is completed unilaterally, analyzes not comprehensive enough.In the third adjustment method, pass through
The mode of Firmware daily records can only macroscopic view check system flow, the interaction of software and hardware in time is unable to essence
The thin operation for arriving logical internal, can not also know the behavior of logical internal.
The content of the invention
This application provides a kind of adjustment method and system of Soc chips, to solve to use JTAG in existing adjustment method
Interface can not know that the process that chip goes wrong, the analysis interacted using I/O interface to logic in chip comprehensively and are not used
The problem of mode of Firmware daily records can not be fine to the operation of logical internal.
On the one hand, this application provides a kind of adjustment method of Soc chips, methods described includes：
Obtain and analyze Debugging message, export effective Debugging message；
Mark effective Debugging message；
Effective Debugging message after storage mark；
The storage state of effective Debugging message after judge mark, according to the storage state, output meets arbitration
Effective Debugging message of principle；
Meet effective Debugging message of arbitration principle described in encapsulation；
Effective Debugging message after distribution encapsulation；
Effective Debugging message after conveying distribution.
Optionally, the storage state of effective Debugging message after the judge mark, defeated according to the storage state
Go out the effective Debugging message for meeting arbitration principle, including：
Judge that effective Debugging message after the mark whether there is, if effective Debugging message after the mark is deposited
Then exporting the effective Debugging message for meeting arbitration principle.
Optionally, mark effective Debugging message includes：Mark time that the effective Debugging message occurs and
Source.
Optionally, the arbitration principle includes：The data length of effective Debugging message is judged, when effective debugging
When the data length of information is not equal to default data length, effective Debugging message is exported.
Optionally, effective Debugging message of arbitration principle is met described in the encapsulation to be included：According to default frame format, system
Meet effective Debugging message of arbitration principle described in one encapsulation.
On the other hand, this application provides a kind of debugging system of Soc chips, the system includes：
High-speed hardware log pattern, the HHSL modules include：
Event analyser module, for obtaining and analyzing Debugging message, exports effective Debugging message；
Timestamp module, for marking effective Debugging message；
Push-up storage, for storing effective Debugging message after mark；
Arbitrator module, for the storage state of effective Debugging message after judge mark, according to the storage shape
State, output meets effective Debugging message of arbitration principle；
Message maker module, for encapsulating the effective Debugging message for meeting arbitration principle；
Selector module, for distributing effective Debugging message after encapsulation；
I/O interface, for conveying effective Debugging message after distribution.
Optionally, the arbitrator module is additionally operable to, and judges that effective Debugging message after the mark whether there is in institute
State in FIFO memory, if effective Debugging message after the mark is present, output meets the described effective of arbitration principle
Debugging message.
From above technical scheme, the embodiment of the present application provides a kind of adjustment method and system of Soc chips, obtains simultaneously
Debugging message is analyzed, effective Debugging message is exported；Mark effective Debugging message；Effective debugging letter after storage mark
Breath；The storage state of effective Debugging message after judge mark, according to the storage state, output meets arbitration principle
Effective Debugging message；Meet effective Debugging message of arbitration principle described in encapsulation；Effective debugging after distribution encapsulation
Information；Effective Debugging message after conveying distribution.The present processes and system can obtain the generation of chip internal problem
Accurate process and internal logic, solve that the mistake that chip goes wrong can not be known using jtag interface in existing adjustment method
Journey, the analysis interacted using I/O interface to logic in chip can not be fine to comprehensively and using the mode of Firmware daily records
The problem of operation of logical internal.
Brief description of the drawings
In order to illustrate more clearly of the technical scheme of the application, the required accompanying drawing used in case study on implementation will be made below
Simply introduce, it should be apparent that, for those of ordinary skills, do not paying the premise of creative labor
Under, other accompanying drawings can also be obtained according to these accompanying drawings.
A kind of flow chart of the adjustment method for Soc chips that Fig. 1 provides for the embodiment of the present application；
A kind of structure chart of the debugging system for Soc chips that Fig. 2 provides for the embodiment of the present application；
Fig. 3 has the structure chart in three Debugging message sources for the Soc chip internals that the embodiment of the present application is provided.
Illustrate：
1- event analyser modules；2- timestamp modules；3- first carries out out memory；4- arbitrator modules；5- message systems
Make device module；6- selector modules；7-IO interfaces；8- high-speed hardware log patterns.
Embodiment
Referring to Fig. 1, a kind of flow chart of the adjustment method of the Soc chips provided for the embodiment of the present application.Methods described bag
Include：
S101, obtains and analyzes Debugging message, exports effective Debugging message；Because Debugging message may be from chip
The different module in portion, and the business of different resume modules is different, the data content of the Debugging message would also vary from, institute
So that according to the actual service condition of chip, selection needs the Debugging message handled, in addition, the type of Debugging message, stream side
To and length etc. be also all the standard of analyzing Debugging message, analysis Debugging message is conducive to obtaining fine chip internal logic；
Effective Debugging message refers to：Need the situation according to actual use, the specific Debugging message of selection；
S102, marks effective Debugging message；Effective Debugging message is marked, is conducive to understanding the debugging letter of chip internal
The order of the data transmission period of breath, can make the chip internal logic got more accurate, when being hardware on Debugging message band
Between stab, therefore the application also has the strict accurately advantage of succession；
Effective Debugging message after S103, storage mark；
Internal normal key order and data interaction are also sent to HHSL by different modules simultaneously in design in system
Module, caches these interactive information in HHSL modules, because inside has multiple information generating sources, and the output port of daily record
Only one of which, and speed is usually less than the process bandwidth of internal module, because the big of caching need to be determined according to frequency and bandwidth
Small and depth, so as to ensure that bandwidth match and FIFO memory will not overflow, each information generating source can correspond to one it is asynchronous
FIFO memory；
The embodiment of the present application is that each information source module specially devises event analyser and push-up storage, therefore
Have the advantages that degree of accuracy height, statistic are big；
The storage state of effective Debugging message after S104, judge mark, according to the storage state, output meets
Arbitrate effective Debugging message of principle；
S105, encapsulation is described to meet the effective Debugging message for arbitrating principle；Encapsulate the debugging that disparate modules can be sent
Information encapsulation is into unified frame format, just as the package of ether network packet, and the Debugging message after encapsulation has identical frame
Form, facilitates other devices of chip exterior to understand Debugging message；
S106, effective Debugging message after distribution encapsulation；
S107, effective Debugging message after conveying distribution.Effective Debugging message is transported to using special interface
Chip exterior, improves efficiency of transmission, meets the requirement of chip system clock, also allow for the logic inside analysis chip.
From above technical scheme, the embodiment of the present application provides a kind of adjustment method of Soc chips, obtains and analyze tune
Information is tried, effective Debugging message is exported；Mark effective Debugging message；Effective Debugging message after storage mark；Sentence
The storage state of effective Debugging message after disconnected mark, according to the storage state, output meets the described of arbitration principle
Effective Debugging message；Meet effective Debugging message of arbitration principle described in encapsulation；Effective Debugging message after distribution encapsulation；
Effective Debugging message after conveying distribution.The present processes can obtain chip internal problem generation accurate process and
Internal logic, is solved in existing adjustment method that using jtag interface process that chip goes wrong can not be known, is connect using IO
The analysis that mouth is interacted to logic in chip can not be fine to logical internal comprehensively and using the mode of Firmware daily records
The problem of operation.
Optionally, step S104, including：
Judge that effective Debugging message after the mark whether there is, if effective Debugging message after the mark is deposited
Then exporting the effective Debugging message for meeting arbitration principle.
Optionally, mark effective Debugging message includes：Mark time that the effective Debugging message occurs and
Source.
Optionally, the arbitration principle includes：The data length of effective Debugging message is judged, when effective debugging
When the data length of information is not equal to default data length, effective Debugging message is exported.
Optionally, step S105 includes：According to default frame format, effective tune of arbitration principle is met described in unified encapsulation
Try information.
Debugging message after the I/O interface output of chip, is sent to Covert Board processing with fixed frame format, this
Covert Board can be the agreement adapter realized with CPLD, FPGA or MCU, by the letter of customized HHSL forms
Breath is converted to usb protocol data, is transferred to eventually through USB cable in display or the storage device of such as PC.
After Debugging message is sent on PC, and display software on PC (can be third party, or independent development is soft
Part) it can show or achieve in the way of text log.The daily record so exported just have recorded chip internal module in detail
Between data command transmission details, include the particular content of transmission, the sequencing of transmission, uninterrupted, in chip exterior
It is very clear.The purpose of quick positioning is so just reached.
From above technical scheme, the embodiment of the present application provides a kind of adjustment method of Soc chips, can obtain chip
Accurate process and internal logic that internal problem occurs, solve that chip can not be known using jtag interface in existing adjustment method
The process gone wrong, not comprehensive and using Firmware daily records the mode of analysis interacted using I/O interface to logic in chip
The problem of operation of logical internal can not be fine to.
Referring to Fig. 2, a kind of structure chart of the debugging system of the Soc chips provided for the embodiment of the present application, the system bag
Include：
High-speed hardware daily record (Hardware High Speed Logger, HHSL) module 8, the HHSL modules include：
Event analyser module 1, for obtaining and analyzing Debugging message, exports effective Debugging message；
Timestamp module 2, for marking effective Debugging message；
Push-up storage 3, for storing effective Debugging message after mark；
Further, the FIFO memory in the present embodiment is asynchronous FIFIO memories；
Arbitrator module 4, for the storage state of effective Debugging message after judge mark, according to the storage shape
State, output meets effective Debugging message of arbitration principle；
Message maker module 5, for encapsulating the effective Debugging message for meeting arbitration principle；
Selector module 6, for distributing effective Debugging message after encapsulation；
I/O interface 7, for conveying effective Debugging message after distribution.
Using I/O interface rather than traditional JTAG, UART (Universal Asynchronous Receiver/
Transmitter, universal asynchronous receiving-transmitting transmitter), the slow interface such as I2C (Inter-Integrated Circuit), significantly
Efficiency of transmission is improved, and meets the chip system clock increasingly lifted.
Internal Debugging message can be output in the way of interface is transmitted in display/storage device outside piece, can be with
The free memory cell such as SRAM being stored in piece or by the plug-in DDR of chip (Double Data Rate) memories or
In person's flash storage；It can be applied in the environment of being inconvenient to connect display device, by by the log information of external memory storage
Secondary export is carried out, so as to the reproduction of problem of implementation application scenarios, such as chip is positioned and remote the problem of curstomer's site
Cheng Dingwei.
Due to that can develop customized daily record print software on the display device, thus can easily by Debugging message with
The mode of human language is showed, and is had the advantages that readable high.
The present embodiment cannot be only used for the debugging exploitation of Soc chips, apply also for CPLD/FPGA system debugs exploitation.
HHSL agreement is self-defined, and the I/O pin situation that can be originally used according to chip is multiplexed, less chip
Cost.
Optionally, the arbitrator module 4 is additionally operable to, and judges that effective Debugging message after the mark whether there is in institute
State in FIFO memory, if effective Debugging message after the mark is present, output meets the described effective of arbitration principle
Debugging message.
Due to the daily record implementation using pure hardware, the coffret of HHSL and logic module is directly docked, therefore tool
Have the advantages that real-time.
Below, the above embodiments are illustrated with reference to specific example：
So that a Soc chip internal has three Debugging message sources as an example, as shown in figure 3, event A (Event-A), event B
(Event-B) and event C (Event-C) is the input of the Debugging message of three modules of chip internal respectively, and three are assumed
Module is respectively from three different clock zones, and is different clock zones with HHSL modules；
EP modules can be first passed through after event enters HHSL modules to be analyzed, because the business of each resume module is not to the utmost
Identical, data content also has difference, therefore the module is mainly the effective data message of analysis, abandons in unnecessary information
Hold, and the Debugging message that can be inputted according to CPU configuration sweetly disposition.EP modules be considered correct and be need output
Debugging message after, current timestamp can be obtained from TS modules, and stamp UID (User Identification, user
Proof of identification), time point and source that mark Debugging message occurs.
The clock is 16bits in the clock that TS modules are generated according to system clock, the present embodiment, according to specific
Chip can increase or reduce the digit of clock.
The Debugging message marked is deposited into asynchronous FIFO memory after EP resume modules and kept in, FIFO
The depth of memory according to correspondence source module (Debugging message generation module) service traffics continuity and with HHSL modules
Clock ratio relation and design, it is ensured that the matching of bandwidth, and can guarantee that FIFO memory will not overflow, then in the event of overflowing
Produce abnormal.The width of FIFO memory is then depending on the direct data width according to input Debugging message.
Follow-up WRR Arbiter (Weight Round-Robin Arbiter, the fair arbitration device of Weight) module meeting
Whether be empty, if sky, then take out to debug in caching according to current arbitration principle and believe if checking each asynchronous FIFO memory
The data of breath give the encapsulation that Msg Builder modules carry out HHSL data formats.Here by the data frame of encapsulation be designed as
Lower form：
WD0 is Header part：
UID is to prove the source module in Debug information (Debugging message) source, and 4 bits can support 16 information sources here；
Length is not include the data length including Header, in units of Byte；
Crc_en is that data are wanted plus CRC check；
Reserve is used as reserved；
WD1~WDn-1 is Debugging message data, because the data format is according to 32bits width tissues, therefore works as data
, it is necessary to be packaged when length is not 32bits；
WDn is CRC check data, and verified data include Header and Data part.
Data according to above frame format after being encapsulated, and Debugging message is sent to I/O interface by Dest Select modules, but by
In chip pin resource-constrained, before I/O interface is sent to, Debugging message will also by P2S (Point to Server,
Point is to server) module, P2S modules can carry out and turn the processing of string, using a small amount of pin progress serial transmission, this implementation
Carried out data transmission in example using 4 PIN, that is to say, that 32bits data at least need 8 cycles.
Debugging message is output to outside the piece of chip carry in NAND in addition, Dest Select modules are also an option that.
From above technical scheme, the embodiment of the present application provides a kind of debugging system of Soc chips, obtains and analyze tune
Information is tried, effective Debugging message is exported；Mark effective Debugging message；Effective Debugging message after storage mark；Sentence
The storage state of effective Debugging message after disconnected mark, according to the storage state, output meets the described of arbitration principle
Effective Debugging message；Meet effective Debugging message of arbitration principle described in encapsulation；Effective Debugging message after distribution encapsulation；
Effective Debugging message after conveying distribution.The present processes and system can obtain the accurate of chip internal problem generation
Process and internal logic, solve in existing adjustment method that using jtag interface process that chip goes wrong can not be known, make
The analysis interacted with I/O interface to logic in chip can not be fine to logic comprehensively and using the mode of Firmware daily records
The problem of operation of inside.
In the specific implementation, the application also provides a kind of computer-readable storage medium, wherein, the computer-readable storage medium can be stored
There is program, the program may include the part or all of step in each embodiment for the method for calling that the present invention is provided when performing.Institute
The storage medium stated can be magnetic disc, CD, read-only memory (English：Read-only memory, referred to as：ROM) or with
Machine storage memory (English：Random access memory, referred to as：RAM) etc..
It is required that those skilled in the art can be understood that the technology in the embodiment of the present application can add by software
The mode of general hardware platform realize.Understood based on such, the technical scheme in the embodiment of the present application substantially or
Say that the part contributed to prior art can be embodied in the form of software product, the computer software product can be deposited
Storage is in storage medium, such as ROM/RAM, magnetic disc, CD, including some instructions are to cause a computer equipment (can be with
It is personal computer, server, or network equipment etc.) perform some part institutes of each of the invention embodiment or embodiment
The method stated.
Between the embodiment of each in this specification identical similar part mutually referring to.Implement especially for system
For example, because it is substantially similar to embodiment of the method, so description is fairly simple, related part is referring in embodiment of the method
Explanation.
Above-described the application embodiment does not constitute the restriction to the application protection domain.
Claims (7)
1. a kind of adjustment method of Soc chips, it is characterised in that methods described includes：
Obtain and analyze Debugging message, export effective Debugging message；
Mark effective Debugging message；
Effective Debugging message after storage mark；
The storage state of effective Debugging message after judge mark, according to the storage state, output meets arbitration principle
Effective Debugging message；
Meet effective Debugging message of arbitration principle described in encapsulation；
Effective Debugging message after distribution encapsulation；
Effective Debugging message after conveying distribution.
2. according to the method described in claim 1, it is characterised in that effective Debugging message after the judge mark is deposited
Storage state, according to the storage state, output meets effective Debugging message of arbitration principle, including：
Judge that effective Debugging message after the mark whether there is, if effective Debugging message after the mark is present,
Output meets effective Debugging message of arbitration principle.
3. according to the method described in claim 1, it is characterised in that mark effective Debugging message includes：Mark institute
State time and source that effective Debugging message occurs.
4. according to the method described in claim 1, it is characterised in that the arbitration principle includes：Judge effective debugging letter
The data length of breath, when the data length of effective Debugging message is not equal to default data length, exports described effective
Debugging message.
5. according to the method described in claim 1, it is characterised in that meet effective debugging letter of arbitration principle described in the encapsulation
Breath includes：According to default frame format, effective Debugging message of arbitration principle is met described in unified encapsulation.
6. a kind of debugging system of Soc chips, it is characterised in that the system includes：
High-speed hardware daily record (Hardware High Speed Logger, HHSL) module, the HHSL modules include：
Event analyser (Event Parser, EP) module, for obtaining and analyzing Debugging message, exports effective Debugging message；
Timestamp (Timestamp, TS) module, for marking effective Debugging message；
First in first out (First in first out, FIFO) memory, for storing effective Debugging message after mark；
Moderator (Arbiter) module, for the storage state of effective Debugging message after judge mark, is deposited according to described
Storage state, output meets effective Debugging message of arbitration principle；
Message maker (Msg Builder) module, for encapsulating the effective Debugging message for meeting arbitration principle；
Selector (Dest Select) module, for distributing effective Debugging message after encapsulation；
I/O interface, for conveying effective Debugging message after distribution.
7. system according to claim 6, it is characterised in that the arbitrator module is additionally operable to, judges after the mark
Effective Debugging message whether there is in the FIFO memory, if effective Debugging message after the mark is present,
Output meets effective Debugging message of arbitration principle.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111737155A (en) * | 2020-08-04 | 2020-10-02 | 北京燧原智能科技有限公司 | Chip debugging system, method, device, equipment and storage medium |
| CN112559336A (en) * | 2020-12-09 | 2021-03-26 | 成都海光集成电路设计有限公司 | Method, device and system for adaptively debugging heterogeneous computing chip and mainboard chip |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111737155A (en) * | 2020-08-04 | 2020-10-02 | 北京燧原智能科技有限公司 | Chip debugging system, method, device, equipment and storage medium |
| CN112559336A (en) * | 2020-12-09 | 2021-03-26 | 成都海光集成电路设计有限公司 | Method, device and system for adaptively debugging heterogeneous computing chip and mainboard chip |
| CN112559336B (en) * | 2020-12-09 | 2023-05-19 | 成都海光集成电路设计有限公司 | Method, device and system for self-adaptively debugging heterogeneous computing chip and main board chip |
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Application publication date: 20171020 |