CN107247681A - A kind of big data engine prototype based on multinuclear isomery CPU GPU FPGA - Google Patents

Abstract

The present invention discloses a kind of big data engine prototype based on multinuclear isomery CPU GPU FPGA.Framework is characterized by independent parallel C PU and parallel GPU, there is respective magnetic random storage subsystem, may have access to the magnetic RAM of other side, and outside FPGA structure；GPU is connected to chipset by I/O buses, is then connected again by I/O bridges with CPU；CPU is cached by ALU, register file and intelligent flash and EBI is constituted.System transplantation is carried out, to support multinuclear isomery CPU GPU FPGA big data exchange architectures, a kind of big data engine prototype is constituted.

Description

A kind of big data engine prototype based on multinuclear isomery CPU-GPU-FPGA

Technical field

The present invention relates to a kind of big data engine prototype based on multinuclear isomery CPU-GPU-FPGA

Background technology

With cloud computing and virtualization, the features such as " extensive ", " high density ", " high energy consumption ", " complication " is showed, is built If with development New Generation of IDC, lifting data center infrastructure management will become increasingly important, the basis of data center The new trend that framework fusion management will develop with intelligence as data center.

Ultra-large type data center provide from infrastructure to data analysis below, screening, application whole application take Business.It is not only data analysis, in addition to the special service different from the generalization service that public cloud is provided is in the cloud of intelligence manufacture Calculate, and super computing, this just proposes requirements at the higher level to the disposal ability of big data.

Heterogeneous Computing refers to the calculation that system is constituted using the computing unit of different type instruction set and architectural framework. Common computing unit classification includes：CUP (central processing unit), GPU (graphics processor), FPGA (field programmable gate array) Deng.It has been trend of the times that CPU is merged with GPU height, but this is more than the change of hardware view, is more calculating theory Change.How different calculating tasks is automatically assigned to be most appropriate to the chip of the processing task, highest energy is realized whereby Effect ratio and highest transistor utilization rate, as the new programming mode of exploration or the computation schema significant problem to be faced.

After increasing special stone is integrated into FPGA, FPGA design method needs occur essence Change.The SoC design method progressively accepted in IC design fields is likewise introduced into FPGA design field, this side The core of method is to surround CPU core Method of Spreading Design, and the system bus drawn using CPU is trunk, and other modules all hang over this In bus, such as, the system based on CPU is developed on FPGA, after electricity on FPGA, hardware logic passes through chip configuration successful Afterwards, read software document and go in SDRAM (synchronous DRAM), software is run in SDRAM.

It is overall with more interior check figures and computation capability although the dedicated computing unit working frequency such as GPU is relatively low The ratio and performance/power dissipation ratio of performance/chip area are all very high, are but far from being fully used.Particularly GPU general meter Calculation is imported into high parallel computation field, to fusion multi-sensor information of the processing including vision sensor, plays new core Effect.

Intelligent flash caching is read buffer.When unmodified data block because the pressure in space is removed out caching Area's cache, these data blocks are just moved into flash cache；If needing these data again, database will be again this A little data blocks are moved back to from flash cache.Flash cache utilizes the I/O speed of flash memory device, higher than the storage performance based on disk Much；With enough CPU, flash cache can be used.

Magnetic RAM (Magnetic Random Access Memory, abbreviation MRAM) possesses static random and deposited The high speed of reservoir (SRAM) reads write capability, and dynamic RAM (DRAM) high integration, and substantially may be used To be repeatedly written infinitely.

The invention provides a kind of big data engine prototype based on multinuclear isomery CPU-GPU-FPGA.The feature of framework is With independent parallel C PU and parallel GPU, there is respective magnetic random storage subsystem, may have access to the magnetic random of other side Memory, and outside FPGA structure；GPU is connected to chipset by I/O buses, then passes through I/O bridges and CPU phases again Even；CPU is cached by ALU, register file and intelligent flash and EBI is constituted.System transplantation is carried out, to support multinuclear Isomery CPU-GPU-FPGA big data exchange architectures, constitute a kind of big data engine prototype.

The content of the invention

It is an object of the invention to provide a kind of big data exchange architecture based on multinuclear isomery CPU-GPU-FPGA.This hair It is bright including following characteristics：

Inventive technique scheme

1. a kind of big data exchange architecture based on multinuclear isomery CPU-GPU-FPGA, the feature of framework：

1) there is independent parallel C PU and parallel GPU, there is respective magnetic random storage subsystem, other side is may have access to Magnetic RAM, and outside the FPGA structure；

2) GPU is connected to chipset by I/O buses, is then connected again by I/O bridges with CPU；

3) CPU is cached by ALU, register file and intelligent flash and EBI is constituted.

2. the hardware structure based on claim 1, carries out system transplantation, to support the big numbers of multinuclear isomery CPU-GPU-FPGA According to exchange architecture, a kind of big data engine prototype is constituted.

Brief description of the drawings

Accompanying drawing 1 is the big data engine prototype figure based on multinuclear isomery CPU-GPU-FPGA.

Embodiment

This big data engine prototype based on multinuclear isomery CPU-GPU-FPGA, comprises the following steps feature：

1) there is independent parallel C PU and parallel GPU, there is respective magnetic random storage subsystem, other side is may have access to Magnetic RAM, and outside the FPGA structure；

2) GPU is connected to chipset by I/O buses, is then connected again by I/O bridges with CPU；

3) CPU is cached by ALU, register file and intelligent flash and EBI is constituted；

4) system transplantation is carried out, to support multinuclear isomery CPU-GPU-FPGA big data exchange architectures, a kind of big number is constituted According to engine prototype.

Claims (2)

1. a kind of big data exchange architecture based on multinuclear isomery CPU-GPU-FPGA, the feature of framework：

1) there is independent parallel C PU and parallel GPU, have respective magnetic random storage subsystem, may have access to the magnetic of other side Property random access memory, and outside the FPGA structure；

2) GPU is connected to chipset by I/O buses, is then connected again by I/O bridges with CPU；

3) CPU is cached by ALU, register file and intelligent flash and EBI is constituted.

2. the hardware structure based on claim 1, carries out system transplantation, to support multinuclear isomery CPU-GPU-FPGA big datas to draw Framework is held up, a kind of big data engine prototype is constituted.